From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E065FC5519F for ; Wed, 18 Nov 2020 12:39:27 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 283D424180 for ; Wed, 18 Nov 2020 12:39:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="yNY3Mfvb" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 283D424180 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=emSgyBKkb6QBLN3xxTqRyMNxvlLt6EVtVx29o3AKkgQ=; b=yNY3MfvbyD1dAjqCj9ccZ1tIw HSj36J04Dm6Ly1MgkC6k4Rp5bL4DLmTNypvMa9dNPGpxTedRswFMD55SRRrAfviQjq76CarV/fil7 n5RAhh+jVDKTzhmB+HRfWrCnHOMB8mRJrB8Dvspb0ZRuYz3m3OJQYLmjTOvyZPBdqY96ibecm7mX5 PbZ0j59BTNij10MTsKl1ZZwRWXzOlJliQOgzijJA8ObJHuO8uzkViHGfJ0ZFWpFN4Tb1FMK7bV34C GFCAcMut9ZNUj3sc0jH5Kt/51n3EsA1kLrRLxHCeZyUqL2KepozX++Kc4jPKa6jLQx4iXTM0MMomg SgGkBXfZw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kfMj1-0002Xp-SW; Wed, 18 Nov 2020 12:38:15 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kfMiy-0002Wv-H8 for linux-arm-kernel@lists.infradead.org; Wed, 18 Nov 2020 12:38:13 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6029611D4; Wed, 18 Nov 2020 04:38:04 -0800 (PST) Received: from [10.57.26.234] (unknown [10.57.26.234]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7C2A23F70D; Wed, 18 Nov 2020 04:38:03 -0800 (PST) Subject: Re: [RFC PATCH 1/2] arm64: Support execute-only permissions with Enhanced PAN To: Catalin Marinas References: <20201113152023.102855-1-vladimir.murzin@arm.com> <20201113152023.102855-2-vladimir.murzin@arm.com> From: Vladimir Murzin Message-ID: <5e4cdc4a-d8be-6df7-e096-018cc3fe3463@arm.com> Date: Wed, 18 Nov 2020 12:37:40 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201118_073812_696720_0C1C494E X-CRM114-Status: GOOD ( 22.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: keescook@chromium.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 11/17/20 4:48 PM, Catalin Marinas wrote: > On Fri, Nov 13, 2020 at 03:20:22PM +0000, Vladimir Murzin wrote: >> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h >> index 4ff12a7..d1f68d2 100644 >> --- a/arch/arm64/include/asm/pgtable.h >> +++ b/arch/arm64/include/asm/pgtable.h >> @@ -113,8 +113,15 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; >> #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) >> >> #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) >> -#define pte_valid_not_user(pte) \ >> - ((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID) >> +#define pte_valid_not_user(pte) \ >> +({ \ >> + int __val; \ >> + if (cpus_have_const_cap(ARM64_HAS_EPAN)) \ >> + __val = (pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN); \ >> + else \ >> + __val = (pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID; \ >> + __val; \ > > Is it worth having the cap check here? I'd go with the PTE_VALID|PTE_UXN > check only. > I do not know to be honest. I do not have full picture in mind and what could be side effects of the change (that's why RFC). 24cecc377463 the PTE_VALID|PTE_UXN moved to PTE_VALID, so I decided to be safe than sorry... >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index dcc165b..2033e0b 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -1602,6 +1602,13 @@ static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) >> } >> #endif /* CONFIG_ARM64_PAN */ >> >> +#ifdef CONFIG_ARM64_EPAN >> +static void cpu_enable_epan(const struct arm64_cpu_capabilities *__unused) >> +{ >> + sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_EPAN); >> +} >> +#endif /* CONFIG_ARM64_EPAN */ > > I checked the spec (2020 arch updates) and the EPAN bit is permitted to > be cached in the TLB. I think we get away with this because this > function is called before cnp is enabled. Maybe we should make it > explicit and move the CnP entry last with a comment. > Hmm, so we rely on CnP's enable method to (indirectly) involve local_flush_tlb_all()? It doesn't seem robust since CONFIG_ARM64_CNP could be unset. I can add local_flush_tlb_all() into cpu_enable_epan() or we can have something like diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index bb2016c..0f0a27b 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2416,6 +2416,8 @@ static int cpu_enable_non_boot_scope_capabilities(void *__unused) if (cap->cpu_enable) cap->cpu_enable(cap); } + + local_flush_tlb_all(); return 0; } @@ -2467,6 +2469,8 @@ static void __init enable_cpu_capabilities(u16 scope_mask) if (!boot_scope) stop_machine(cpu_enable_non_boot_scope_capabilities, NULL, cpu_online_mask); + else + local_flush_tlb_all(); } /* What would be your preference? Cheers Vladimir _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel