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[68.111.84.250]) by smtp.gmail.com with ESMTPSA id v7sm16070092edq.82.2020.06.09.21.22.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Jun 2020 21:22:31 -0700 (PDT) Subject: Re: [PATCH 1/6] dt-bindings: usb: dwc3: add property to disable xhci 64bit support To: Peter Chen , Jun Li References: <1591701165-12872-1-git-send-email-jun.li@nxp.com> <1591701165-12872-2-git-send-email-jun.li@nxp.com> <20200610024816.GA18494@b29397-desktop> From: Florian Fainelli Message-ID: <5e4d7227-afd7-27cf-720c-defeadff8450@gmail.com> Date: Tue, 9 Jun 2020 21:22:28 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Firefox/68.0 Thunderbird/68.9.0 MIME-Version: 1.0 In-Reply-To: <20200610024816.GA18494@b29397-desktop> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200609_212234_614330_35A467E2 X-CRM114-Status: GOOD ( 14.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "balbi@kernel.org" , "gregkh@linuxfoundation.org" , "s.hauer@pengutronix.de" , "linux-usb@vger.kernel.org" , "robh+dt@kernel.org" , dl-linux-imx , "kernel@pengutronix.de" , "shawnguo@kernel.org" , "festevam@gmail.com" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 6/9/2020 7:47 PM, Peter Chen wrote: > On 20-06-09 19:12:40, Li Jun wrote: >> Add a property "snps,xhci-dis-64bit-support-quirk" to disable xhci 64bit >> address support, this is due to SoC integration can't support it but >> the AC64 bit (bit 0) of HCCPARAMS1 is set to be 1. >> >> Signed-off-by: Li Jun >> --- >> Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt >> index d03edf9..d16cba7 100644 >> --- a/Documentation/devicetree/bindings/usb/dwc3.txt >> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt >> @@ -109,6 +109,9 @@ Optional properties: >> When just one value, which means INCRX burst mode enabled. When >> more than one value, which means undefined length INCR burst type >> enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256. >> + - snps,xhci-dis-64bit-support-quirk: set if the AC64 bit (bit 0) of HCCPARAMS1 is set >> + to be 1, but the controller actually can't handle 64-bit address >> + due to SoC integration. >> >> - in addition all properties from usb-xhci.txt from the current directory are >> supported as well > > Why not adding it at usb-xhci.txt directly? It is more like general > property, I see Renesas rcar platforms also have this quirk. > Or rather define a compatible string for the specific SoC integration here and based upon that compatibility string set the xhci->quirks to have XHCI_NO_64BIT_SUPPORT set. -- Florian _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel