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mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=detlev.casanova@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1749686457; s=zohomail; d=collabora.com; i=detlev.casanova@collabora.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Content-Type:Message-Id:Reply-To; bh=vGmPNxgIyEoEQtADc8X3nicC6jEVHqGcMDg8y3I/t3o=; b=B89YEpc18TsrakKZypLJ7xGiQ6kWyg6E59pyj89kKZmDWb8r5NGmKQEPYBR0D3Fx NOmEBD89GluYxB12j6rZV/ZLix7X6ZnTqRW+Xn5Cg0Q5qqzsIW6u1ft1kCPfBt/+hqq pup6vSnHDcfX3ZuwlZ+C2RdyjA7nJpHzR9/gtB8U= Received: by mx.zohomail.com with SMTPS id 1749686454865928.7893063021048; Wed, 11 Jun 2025 17:00:54 -0700 (PDT) From: Detlev Casanova To: Sandy Huang , Heiko =?UTF-8?B?U3TDvGJuZXI=?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Cristian Ciocaltea Cc: kernel@collabora.com, Andy Yan , Krzysztof Kozlowski , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH 3/3] arm64: dts: rockchip: Add HDMI PHY PLL clock source to VOP2 on rk3576 Date: Wed, 11 Jun 2025 20:00:52 -0400 Message-ID: <6011857.DvuYhMxLoT@trenzalore> In-Reply-To: <20250612-rk3576-hdmitx-fix-v1-3-4b11007d8675@collabora.com> References: <20250612-rk3576-hdmitx-fix-v1-0-4b11007d8675@collabora.com> <20250612-rk3576-hdmitx-fix-v1-3-4b11007d8675@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="utf-8" X-ZohoMailClient: External X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250611_170126_415953_9336FBED X-CRM114-Status: GOOD ( 19.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Cristian, On Wednesday, 11 June 2025 17:47:49 EDT Cristian Ciocaltea wrote: > Since commit c871a311edf0 ("phy: rockchip: samsung-hdptx: Setup TMDS > char rate via phy_configure_opts_hdmi"), the workaround of passing the > rate from DW HDMI QP bridge driver via phy_set_bus_width() became > partially broken, as it cannot reliably handle mode switches anymore. > > Attempting to fix this up at PHY level would not only introduce > additional hacks, but it would also fail to adequately resolve the > display issues that are a consequence of the system CRU limitations. > > Instead, proceed with the solution already implemented for RK3588: make > use of the HDMI PHY PLL as a better suited DCLK source for VOP2. This > will not only address the aforementioned problem, but it should also > facilitate the proper operation of display modes up to 4K@60Hz. > > It's worth noting that anything above 4K@30Hz still requires high TMDS > clock ratio and scrambling support, which hasn't been mainlined yet. > > Fixes: d74b842cab08 ("arm64: dts: rockchip: Add vop for rk3576") > Cc: stable@vger.kernel.org > Signed-off-by: Cristian Ciocaltea > --- > arch/arm64/boot/dts/rockchip/rk3576.dtsi | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi > b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index > 6a13fe0c3513fb2ff7cd535aa70e3386c37696e4..b1ac23035dd789f0478bf10c78c74ef16 > 7d94904 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi > @@ -1155,12 +1155,14 @@ vop: vop@27d00000 { > <&cru HCLK_VOP>, > <&cru DCLK_VP0>, > <&cru DCLK_VP1>, > - <&cru DCLK_VP2>; > + <&cru DCLK_VP2>, > + <&hdptxphy>; > clock-names = "aclk", > "hclk", > "dclk_vp0", > "dclk_vp1", > - "dclk_vp2"; > + "dclk_vp2", > + "pll_hdmiphy0"; > iommus = <&vop_mmu>; > power-domains = <&power RK3576_PD_VOP>; > rockchip,grf = <&sys_grf>; I tested this on the ROCK 4D and can confirm that: - New modes like 2K are now working - Mode changes is now correctly supported So, Tested-By: Detlev Casanova Regards, Detlev.