From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: "Nicolas Frattaroli" <nicolas.frattaroli@collabora.com>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Dong Aisheng" <aisheng.dong@nxp.com>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
"Yassine Oudjana" <y.oudjana@protonmail.com>,
"Laura Nao" <laura.nao@collabora.com>,
"Nícolas F. R. A. Prado" <nfraprado@collabora.com>,
"Chia-I Wu" <olvaffe@gmail.com>,
"Chen-Yu Tsai" <wenst@chromium.org>
Cc: kernel@collabora.com, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Stephen Boyd <sboyd@codeaurora.org>
Subject: Re: [PATCH v2 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc
Date: Thu, 9 Oct 2025 10:01:06 +0200 [thread overview]
Message-ID: <602158eb-472c-4443-9dda-aadf2a6c9f6d@collabora.com> (raw)
In-Reply-To: <20251008-mtk-pll-rpm-v2-1-170ed0698560@collabora.com>
Il 08/10/25 18:05, Nicolas Frattaroli ha scritto:
> When CLK_OPS_PARENT_ENABLE was introduced, it guarded various clock
> operations, such as setting the rate or switching parents. However,
> another operation that can and often does touch actual hardware state is
> recalc_rate, which may also be affected by such a dependency.
>
> Add parent enables/disables where the recalc_rate op is called directly.
>
> Fixes: fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)")
> Fixes: a4b3518d146f ("clk: core: support clocks which requires parents enable (part 1)")
> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
next prev parent reply other threads:[~2025-10-09 8:01 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-08 16:05 [PATCH v2 0/5] MediaTek PLL Refactors and Fixes Nicolas Frattaroli
2025-10-08 16:05 ` [PATCH v2 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc Nicolas Frattaroli
2025-10-09 7:07 ` Chen-Yu Tsai
2025-10-09 8:01 ` AngeloGioacchino Del Regno [this message]
2025-10-08 16:05 ` [PATCH v2 2/5] clk: mediatek: Refactor pll registration to pass device Nicolas Frattaroli
2025-10-09 7:09 ` Chen-Yu Tsai
2025-10-09 7:19 ` Chen-Yu Tsai
2025-10-09 8:09 ` AngeloGioacchino Del Regno
2025-10-09 8:18 ` Chen-Yu Tsai
2025-10-09 8:52 ` AngeloGioacchino Del Regno
2025-10-10 20:11 ` Nicolas Frattaroli
2025-10-08 16:05 ` [PATCH v2 3/5] clk: mediatek: Pass device to clk_hw_register for PLLs Nicolas Frattaroli
2025-10-09 8:11 ` AngeloGioacchino Del Regno
2025-10-09 8:32 ` Chen-Yu Tsai
2025-10-08 16:05 ` [PATCH v2 4/5] clk: mediatek: Refactor pllfh registration to pass device Nicolas Frattaroli
2025-10-09 7:33 ` Chen-Yu Tsai
2025-10-10 20:06 ` Nicolas Frattaroli
2025-10-09 8:12 ` AngeloGioacchino Del Regno
2025-10-08 16:05 ` [PATCH v2 5/5] clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks Nicolas Frattaroli
2025-10-09 8:22 ` AngeloGioacchino Del Regno
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