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Mon, 21 Apr 2025 15:59:54 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by HK3PEPF00000221.mail.protection.outlook.com (10.167.8.43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8655.12 via Frontend Transport; Mon, 21 Apr 2025 15:59:53 +0000 Received: from [172.16.64.208] (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 548CA41604FA; Mon, 21 Apr 2025 23:59:52 +0800 (CST) Message-ID: <60a41564-43ed-41ea-af5c-eb8409b47ad1@cixtech.com> Date: Mon, 21 Apr 2025 23:59:48 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] PCI: dw-rockchip: Configure max payload size on host init To: Manivannan Sadhasivam , Hans Zhang <18255117159@163.com> Cc: Niklas Cassel , Bjorn Helgaas , Shawn Lin , lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, heiko@sntech.de, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org References: <20250417165219.GA115235@bhelgaas> <22720eef-f5a3-4e72-9c41-35335ec20f80@163.com> <225CC628-432C-4E88-AF2B-17C948B3790B@kernel.org> <8af8a418-b808-4a14-9969-1c6d549e1633@163.com> Content-Language: en-US From: Hans Zhang In-Reply-To: Content-Type: text/plain; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2025 15:59:53.4035 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 348ec270-357c-425f-77e9-08dd80ed8e1d X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: HK3PEPF00000221.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY0PR06MB5593 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250421_090015_473764_D35B8A23 X-CRM114-Status: GOOD ( 27.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2025/4/21 22:53, Manivannan Sadhasivam wrote: > EXTERNAL EMAIL > > On Sat, Apr 19, 2025 at 01:21:54AM +0800, Hans Zhang wrote: >> >> >> On 2025/4/18 22:55, Niklas Cassel wrote: >>> >>> >>> On 18 April 2025 14:33:08 CEST, Hans Zhang <18255117159@163.com> wrote: >>>> >>>> Dear Bjorn, >>>> >>>> Thanks your for reply. Niklas and I attempted to modify the relevant logic in drivers/pci/probe.c and found that there was a lot of code judging the global variable pcie_bus_config. At present, there is no good method. I will keep trying. >>>> >>>> I wonder if you have any good suggestions? It seems that the code logic regarding pcie_bus_config is a little complicated and cannot be modified for the time being? >>> >>> >>> Hans, >>> >>> If: >>> >>> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c >>> index 364fa2a514f8..2e1c92fdd577 100644 >>> --- a/drivers/pci/probe.c >>> +++ b/drivers/pci/probe.c >>> @@ -2983,6 +2983,13 @@ void pcie_bus_configure_settings(struct pci_bus *bus) >>> if (!pci_is_pcie(bus->self)) >>> return; >>> + /* >>> + * Start off with DevCtl.MPS == DevCap.MPS, unless PCIE_BUS_TUNE_OFF. >>> + * This might get overriden by a MPS strategy below. >>> + */ >>> + if (pcie_bus_config != PCIE_BUS_TUNE_OFF) >>> + smpss = pcie_get_mps(bus->self); >>> + >> >> Dear Niklas, >> >> Thank you very much for your reply and thoughts. >> >> pcie_get_mps: Returns maximum payload size in bytes >> >> I guess you want to obtain the DevCap MPS. But the purpose of the smpss >> variable is to save the DevCtl MPS. >> >>> /* >>> * FIXME - Peer to peer DMA is possible, though the endpoint would need >>> * to be aware of the MPS of the destination. To work around this, >>> >>> >>> >>> does not work, can't you modify the code slightly so that it works? >>> >>> I haven't tried myself, but considering that it works when walking the bus, it seems that it should be possible to get something working. >>> >> >> >> After making the following modifications, my test shows that it is normal. >> If the consideration is not comprehensive. Could Bjorn and Niklas please >> review my revisions? >> >> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c >> index 364fa2a514f8..5b54f1b0a91d 100644 >> --- a/drivers/pci/probe.c >> +++ b/drivers/pci/probe.c >> @@ -2951,8 +2951,7 @@ static int pcie_bus_configure_set(struct pci_dev *dev, >> void *data) >> if (!pci_is_pcie(dev)) >> return 0; >> >> - if (pcie_bus_config == PCIE_BUS_TUNE_OFF || >> - pcie_bus_config == PCIE_BUS_DEFAULT) >> + if (pcie_bus_config == PCIE_BUS_TUNE_OFF) >> return 0; >> >> mps = 128 << *(u8 *)data; >> @@ -2991,7 +2990,8 @@ void pcie_bus_configure_settings(struct pci_bus *bus) >> if (pcie_bus_config == PCIE_BUS_PEER2PEER) >> smpss = 0; >> >> - if (pcie_bus_config == PCIE_BUS_SAFE) { >> + if ((pcie_bus_config == PCIE_BUS_SAFE) || >> + (pcie_bus_config != PCIE_BUS_TUNE_OFF)) { >> smpss = bus->self->pcie_mpss; >> >> pcie_find_smpss(bus->self, &smpss); >> >> > > As I replied to Niklas, I'd like to limit the changes to platforms having > controller drivers. So here is my proposal: > > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c > index 364fa2a514f8..d32a0f90beb1 100644 > --- a/drivers/pci/probe.c > +++ b/drivers/pci/probe.c > @@ -3228,6 +3228,17 @@ int pci_host_probe(struct pci_host_bridge *bridge) > */ > pci_assign_unassigned_root_bus_resources(bus); > > + if (pcie_bus_config != PCIE_BUS_TUNE_OFF) { > + /* Configure root ports MPS to be MPSS by default */ > + for_each_pci_bridge(dev, bus) { > + if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) > + continue; > + > + pcie_write_mps(dev, 128 << dev->pcie_mpss); > + pcie_write_mrrs(dev); > + } > + } > + Sorry. Since the reply just now was made by logging into the email through the browser, there are some errors. I reply again as follows: [My personal computer is not at hand. I reply using the company email.] Hi Mani, Thank you very much for your reply and suggestions. The following is the test on our platform and it works properly. I wonder if others have any other opinions? If not, I will send the next version and then see everyone's opinions. root@cix-localhost:~# cat /proc/version Linux version 6.15.0-rc2-00015-gced1536aaf04-dirty (hans@hans) ...... root@cix-localhost:~# lspci 0000:c0:00.0 PCI bridge: Device 1f6c:0001 0000:c1:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe SSD Controller S4LV008[Pascal] 0001:90:00.0 PCI bridge: Device 1f6c:0001 0001:91:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe SSD Controller PM9A1/PM9A3/980PRO 0003:30:00.0 PCI bridge: Device 1f6c:0001 0003:31:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8125 2.5GbE Controller (rev 05)root@cix-localhost:~# lspci -vvv 0000:c0:00.0 PCI bridge: Device 1f6c:0001 (prog-if 00 [Normal decode]) ...... Capabilities: [c0] Express (v2) Root Port (Slot-), MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0 ExtTag+ RBE+ DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+ RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ MaxPayload 512 bytes, MaxReadReq 1024 bytes ...... 0000:c1:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe SSD Controller S4LV008[Pascal] (prog-if 02 [NVM Express]) ...... Capabilities: [70] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0W DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+ RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset- MaxPayload 512 bytes, MaxReadReq 512 bytes ...... 0001:90:00.0 PCI bridge: Device 1f6c:0001 (prog-if 00 [Normal decode]) ...... Capabilities: [c0] Express (v2) Root Port (Slot-), MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0 ExtTag- RBE+ DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 512 bytes, MaxReadReq 1024 bytes ...... 0001:91:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe SSD Controller PM9A1/PM9A3/980PRO (prog-if 02 [NVM Express]) ...... Capabilities: [70] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0W DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+ RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset- MaxPayload 256 bytes, MaxReadReq 512 bytes ...... 0003:30:00.0 PCI bridge: Device 1f6c:0001 (prog-if 00 [Normal decode]) ...... Capabilities: [c0] Express (v2) Root Port (Slot-), MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0 ExtTag- RBE+ DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 512 bytes, MaxReadReq 1024 bytes ...... 0003:31:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8125 2.5GbE Controller (rev 05) ...... Capabilities: [70] Express (v2) Endpoint, MSI 01 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0W DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 256 bytes, MaxReadReq 4096 bytes ...... Best regards, Hans > list_for_each_entry(child, &bus->children, node) > pcie_bus_configure_settings(child); > > - Mani > > -- > மணிவண்ணன் சதாசிவம் >