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Sun, 14 Apr 2024 08:53:37 -0700 (PDT) Received: from [10.230.29.214] ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id z76-20020a63334f000000b005dc87f5dfcfsm5616241pgz.78.2024.04.14.08.53.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 14 Apr 2024 08:53:36 -0700 (PDT) Message-ID: <60e3fefc-1600-47f8-8bd5-b92dac56be2d@broadcom.com> Date: Sun, 14 Apr 2024 08:53:32 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/6] mmc: sdhci-brcmstb: Add BCM2712 support To: Andrea della Porta , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Broadcom internal kernel review list , Linus Walleij , Adrian Hunter , Kamal Dasu , Al Cooper , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Jonathan Bell , Phil Elwell References: <7a75876def65f6282b7b3ca17ef8008c305d6c32.1713036964.git.andrea.porta@suse.com> From: Florian Fainelli Autocrypt: addr=florian.fainelli@broadcom.com; keydata= xsBNBFPAG8ABCAC3EO02urEwipgbUNJ1r6oI2Vr/+uE389lSEShN2PmL3MVnzhViSAtrYxeT M0Txqn1tOWoIc4QUl6Ggqf5KP6FoRkCrgMMTnUAINsINYXK+3OLe7HjP10h2jDRX4Ajs4Ghs JrZOBru6rH0YrgAhr6O5gG7NE1jhly+EsOa2MpwOiXO4DE/YKZGuVe6Bh87WqmILs9KvnNrQ PcycQnYKTVpqE95d4M824M5cuRB6D1GrYovCsjA9uxo22kPdOoQRAu5gBBn3AdtALFyQj9DQ KQuc39/i/Kt6XLZ/RsBc6qLs+p+JnEuPJngTSfWvzGjpx0nkwCMi4yBb+xk7Hki4kEslABEB AAHNMEZsb3JpYW4gRmFpbmVsbGkgPGZsb3JpYW4uZmFpbmVsbGlAYnJvYWRjb20uY29tPsLB IQQQAQgAywUCZWl41AUJI+Jo+hcKAAG/SMv+fS3xUQWa0NryPuoRGjsA3SAUAAAAAAAWAAFr ZXktdXNhZ2UtbWFza0BwZ3AuY29tjDAUgAAAAAAgAAdwcmVmZXJyZWQtZW1haWwtZW5jb2Rp bmdAcGdwLmNvbXBncG1pbWUICwkIBwMCAQoFF4AAAAAZGGxkYXA6Ly9rZXlzLmJyb2FkY29t Lm5ldAUbAwAAAAMWAgEFHgEAAAAEFQgJChYhBNXZKpfnkVze1+R8aIExtcQpvGagAAoJEIEx tcQpvGagWPEH/2l0DNr9QkTwJUxOoP9wgHfmVhqc0ZlDsBFv91I3BbhGKI5UATbipKNqG13Z TsBrJHcrnCqnTRS+8n9/myOF0ng2A4YT0EJnayzHugXm+hrkO5O9UEPJ8a+0553VqyoFhHqA zjxj8fUu1px5cbb4R9G4UAySqyeLLeqnYLCKb4+GklGSBGsLMYvLmIDNYlkhMdnnzsSUAS61 WJYW6jjnzMwuKJ0ZHv7xZvSHyhIsFRiYiEs44kiYjbUUMcXor/uLEuTIazGrE3MahuGdjpT2 IOjoMiTsbMc0yfhHp6G/2E769oDXMVxCCbMVpA+LUtVIQEA+8Zr6mX0Yk4nDS7OiBlvOwE0E U8AbwQEIAKxr71oqe+0+MYCc7WafWEcpQHFUwvYLcdBoOnmJPxDwDRpvU5LhqSPvk/yJdh9k 4xUDQu3rm1qIW2I9Puk5n/Jz/lZsqGw8T13DKyu8eMcvaA/irm9lX9El27DPHy/0qsxmxVmU pu9y9S+BmaMb2CM9IuyxMWEl9ruWFS2jAWh/R8CrdnL6+zLk60R7XGzmSJqF09vYNlJ6Bdbs MWDXkYWWP5Ub1ZJGNJQ4qT7g8IN0qXxzLQsmz6tbgLMEHYBGx80bBF8AkdThd6SLhreCN7Uh IR/5NXGqotAZao2xlDpJLuOMQtoH9WVNuuxQQZHVd8if+yp6yRJ5DAmIUt5CCPcAEQEAAcLB gQQYAQIBKwUCU8AbwgUbDAAAAMBdIAQZAQgABgUCU8AbwQAKCRCTYAaomC8PVQ0VCACWk3n+ obFABEp5Rg6Qvspi9kWXcwCcfZV41OIYWhXMoc57ssjCand5noZi8bKg0bxw4qsg+9cNgZ3P N/DFWcNKcAT3Z2/4fTnJqdJS//YcEhlr8uGs+ZWFcqAPbteFCM4dGDRruo69IrHfyyQGx16s CcFlrN8vD066RKevFepb/ml7eYEdN5SRALyEdQMKeCSf3mectdoECEqdF/MWpfWIYQ1hEfdm C2Kztm+h3Nkt9ZQLqc3wsPJZmbD9T0c9Rphfypgw/SfTf2/CHoYVkKqwUIzI59itl5Lze+R5 wDByhWHx2Ud2R7SudmT9XK1e0x7W7a5z11Q6vrzuED5nQvkhAAoJEIExtcQpvGagugcIAJd5 EYe6KM6Y6RvI6TvHp+QgbU5dxvjqSiSvam0Ms3QrLidCtantcGT2Wz/2PlbZqkoJxMQc40rb fXa4xQSvJYj0GWpadrDJUvUu3LEsunDCxdWrmbmwGRKqZraV2oG7YEddmDqOe0Xm/NxeSobc MIlnaE6V0U8f5zNHB7Y46yJjjYT/Ds1TJo3pvwevDWPvv6rdBeV07D9s43frUS6xYd1uFxHC 7dZYWJjZmyUf5evr1W1gCgwLXG0PEi9n3qmz1lelQ8lSocmvxBKtMbX/OKhAfuP/iIwnTsww 95A2SaPiQZA51NywV8OFgsN0ITl2PlZ4Tp9hHERDe6nQCsNI/Us= In-Reply-To: <7a75876def65f6282b7b3ca17ef8008c305d6c32.1713036964.git.andrea.porta@suse.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240414_085345_284926_84655F14 X-CRM114-Status: GOOD ( 32.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============7457493409832880524==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============7457493409832880524== Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="0000000000001617b60616108254" --0000000000001617b60616108254 Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 4/13/2024 3:14 PM, Andrea della Porta wrote: > Broadcom BCM2712 SoC has an SDHCI card controller using the SDIO CFG > register block present on other STB chips. Add support for BCM2712 > SD capabilities of this chipset. > The silicon is SD Express capable but this driver port does not currently > include that feature yet. > Based on downstream driver by raspberry foundation maintained kernel. > > Signed-off-by: Andrea della Porta > --- > drivers/mmc/host/sdhci-brcmstb.c | 130 +++++++++++++++++++++++++++++++ > 1 file changed, 130 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c > index 9053526fa212..907a4947abe5 100644 > --- a/drivers/mmc/host/sdhci-brcmstb.c > +++ b/drivers/mmc/host/sdhci-brcmstb.c > @@ -12,6 +12,8 @@ > #include > #include > #include > +#include > +#include > > #include "sdhci-cqhci.h" > #include "sdhci-pltfm.h" > @@ -30,15 +32,31 @@ > > #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 > > +#define SDIO_CFG_CTRL 0x0 > +#define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31) > +#define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30) > + > +#define SDIO_CFG_SD_PIN_SEL 0x44 > +#define SDIO_CFG_SD_PIN_SEL_MASK 0x3 > +#define SDIO_CFG_SD_PIN_SEL_SD BIT(1) > +#define SDIO_CFG_SD_PIN_SEL_MMC BIT(0) > + > +#define SDIO_CFG_MAX_50MHZ_MODE 0x1ac > +#define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) > +#define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) > + > struct sdhci_brcmstb_priv { > void __iomem *cfg_regs; > unsigned int flags; > struct clk *base_clk; > u32 base_freq_hz; > + struct pinctrl *pinctrl; > + struct pinctrl_state *pins_default; > }; > > struct brcmstb_match_priv { > void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); > + void (*cfginit)(struct sdhci_host *host); > struct sdhci_ops *ops; > const unsigned int flags; > }; > @@ -124,6 +142,42 @@ static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) > writel(reg, host->ioaddr + SDHCI_VENDOR); > } > > +static void sdhci_bcm2712_set_clock(struct sdhci_host *host, unsigned int clock) > +{ > + u16 clk; > + u32 reg; > + bool is_emmc_rate = false; > + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > + struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host); Reverse christmas tree declaration please, longest lines first and shortest lines next. > + > + host->mmc->actual_clock = 0; > + > + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); > + > + switch (host->mmc->ios.timing) { > + case MMC_TIMING_MMC_HS400: > + case MMC_TIMING_MMC_HS200: > + case MMC_TIMING_MMC_DDR52: > + case MMC_TIMING_MMC_HS: > + is_emmc_rate = true; > + break; Both lines are mis-aligned and requiren an additional tab. > + } > + > + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_SD_PIN_SEL); > + reg &= ~SDIO_CFG_SD_PIN_SEL_MASK; > + if (is_emmc_rate) > + reg |= SDIO_CFG_SD_PIN_SEL_MMC; > + else > + reg |= SDIO_CFG_SD_PIN_SEL_SD; > + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_SD_PIN_SEL); > + > + if (clock == 0) > + return; > + > + clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); > + sdhci_enable_clk(host, clk); > +} > + > static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock) > { > u16 clk; > @@ -139,6 +193,17 @@ static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock) > sdhci_enable_clk(host, clk); > } > > +static void sdhci_brcmstb_set_power(struct sdhci_host *host, unsigned char mode, > + unsigned short vdd) > +{ > + if (!IS_ERR(host->mmc->supply.vmmc)) { > + struct mmc_host *mmc = host->mmc; > + > + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); > + } > + sdhci_set_power_noreg(host, mode, vdd); > +} > + > static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, > unsigned int timing) > { > @@ -168,6 +233,36 @@ static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, > sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); > } > > +static void sdhci_brcmstb_cfginit_2712(struct sdhci_host *host) > +{ > + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > + struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host); > + u32 uhs_mask = (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104); > + u32 hsemmc_mask = (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS200_1_2V_SDR | > + MMC_CAP2_HS400_1_8V | MMC_CAP2_HS400_1_2V); > + u32 reg; > + > + /* > + * If we support a speed that requires tuning, > + * then select the delay line PHY as the clock source. > + */ > + if ((host->mmc->caps & uhs_mask) || (host->mmc->caps2 & hsemmc_mask)) { > + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); > + reg &= ~SDIO_CFG_MAX_50MHZ_MODE_ENABLE; > + reg |= SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE; > + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); > + } > + > + if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || > + (host->mmc->caps & MMC_CAP_NEEDS_POLL)) { > + /* Force presence */ > + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); > + reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV; > + reg |= SDIO_CFG_CTRL_SDCD_N_TEST_EN; > + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); > + } > +} > + > static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) > { > sdhci_dumpregs(mmc_priv(mmc)); > @@ -200,6 +295,14 @@ static struct sdhci_ops sdhci_brcmstb_ops = { > .set_uhs_signaling = sdhci_set_uhs_signaling, > }; > > +static struct sdhci_ops sdhci_brcmstb_ops_2712 = { > + .set_clock = sdhci_bcm2712_set_clock, > + .set_power = sdhci_brcmstb_set_power, > + .set_bus_width = sdhci_set_bus_width, > + .reset = sdhci_reset, > + .set_uhs_signaling = sdhci_set_uhs_signaling, > +}; > + > static struct sdhci_ops sdhci_brcmstb_ops_7216 = { > .set_clock = sdhci_brcmstb_set_clock, > .set_bus_width = sdhci_set_bus_width, > @@ -237,7 +340,13 @@ static struct brcmstb_match_priv match_priv_74165b0 = { > .ops = &sdhci_brcmstb_ops_74165b0, > }; > > +static const struct brcmstb_match_priv match_priv_2712 = { > + .cfginit = sdhci_brcmstb_cfginit_2712, > + .ops = &sdhci_brcmstb_ops_2712, > +}; > + > static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = { > + { .compatible = "brcm,bcm2712-sdhci", .data = &match_priv_2712 }, > { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, > { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, > { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, > @@ -314,11 +423,16 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) > struct sdhci_brcmstb_priv *priv; > u32 actual_clock_mhz; > struct sdhci_host *host; > + bool no_pinctrl = false; > struct clk *clk; > struct clk *base_clk = NULL; > int res; > > match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node); > + if (!match) { > + dev_err(&pdev->dev, "fail to get matching of_match struct\n"); > + return -EINVAL; > + } > match_priv = match->data; > > dev_dbg(&pdev->dev, "Probe found match for %s\n", match->compatible); > @@ -354,6 +468,19 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) > if (res) > goto err; > > + priv->pinctrl = devm_pinctrl_get(&pdev->dev); > + if (IS_ERR(priv->pinctrl)) { > + no_pinctrl = true; One too many tabs here. > + } > + priv->pins_default = pinctrl_lookup_state(priv->pinctrl, "default"); > + if (IS_ERR(priv->pins_default)) { > + dev_dbg(&pdev->dev, "No pinctrl default state\n"); > + no_pinctrl = true; One too many tabs here. Please just run checkpatch on your patches, thanks. -- Florian --0000000000001617b60616108254 Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="smime.p7s" Content-Description: S/MIME Cryptographic Signature MIIQeQYJKoZIhvcNAQcCoIIQajCCEGYCAQExDzANBglghkgBZQMEAgEFADALBgkqhkiG9w0BBwGg gg3QMIIFDTCCA/WgAwIBAgIQeEqpED+lv77edQixNJMdADANBgkqhkiG9w0BAQsFADBMMSAwHgYD VQQLExdHbG9iYWxTaWduIFJvb3QgQ0EgLSBSMzETMBEGA1UEChMKR2xvYmFsU2lnbjETMBEGA1UE AxMKR2xvYmFsU2lnbjAeFw0yMDA5MTYwMDAwMDBaFw0yODA5MTYwMDAwMDBaMFsxCzAJBgNVBAYT AkJFMRkwFwYDVQQKExBHbG9iYWxTaWduIG52LXNhMTEwLwYDVQQDEyhHbG9iYWxTaWduIEdDQyBS MyBQZXJzb25hbFNpZ24gMiBDQSAyMDIwMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA vbCmXCcsbZ/a0fRIQMBxp4gJnnyeneFYpEtNydrZZ+GeKSMdHiDgXD1UnRSIudKo+moQ6YlCOu4t rVWO/EiXfYnK7zeop26ry1RpKtogB7/O115zultAz64ydQYLe+a1e/czkALg3sgTcOOcFZTXk38e aqsXsipoX1vsNurqPtnC27TWsA7pk4uKXscFjkeUE8JZu9BDKaswZygxBOPBQBwrA5+20Wxlk6k1 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/+Dy --0000000000001617b60616108254-- --===============7457493409832880524== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============7457493409832880524==--