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Wed, 6 Nov 2024 13:28:01 -0600 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 6 Nov 2024 13:28:00 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 6 Nov 2024 13:28:00 -0600 Received: from [10.249.42.149] ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4A6JS0er095001; Wed, 6 Nov 2024 13:28:00 -0600 Message-ID: <610d6b2d-a041-48cb-90f1-d53114e475f7@ti.com> Date: Wed, 6 Nov 2024 13:28:00 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 04/21] dt-bindings: gpu: img: Allow dma-coherent To: Conor Dooley , Matt Coster CC: Frank Binns , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , "dri-devel@lists.freedesktop.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Randolph Sapp , Darren Etheridge References: <20241105-sets-bxs-4-64-patch-v1-v1-0-4ed30e865892@imgtec.com> <20241105-sets-bxs-4-64-patch-v1-v1-4-4ed30e865892@imgtec.com> <20241105-linseed-steadfast-98cd8abe898c@spud> <5e26957f-dc79-42ef-a8a1-597fb386ae51@imgtec.com> <20241106-dried-spoils-f6ddd8020f40@spud> Content-Language: en-US From: Andrew Davis In-Reply-To: <20241106-dried-spoils-f6ddd8020f40@spud> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241106_112815_358960_FC6D9020 X-CRM114-Status: GOOD ( 15.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 11/6/24 12:30 PM, Conor Dooley wrote: > On Wed, Nov 06, 2024 at 10:18:06AM +0000, Matt Coster wrote: >> On 05/11/2024 18:06, Conor Dooley wrote: >>> On Tue, Nov 05, 2024 at 03:58:10PM +0000, Matt Coster wrote: >>>> This attribute will be required for the BXS-4-64 MC1 and will be enabled in >>>> the DTS for the TI k3-j721s2 in a subsequent patch; add it now so >>>> dtbs_check doesn't complain later. >>> >>> Sounds like the property should be made required for that integration. >> >> This is something I went back and forth on. Where is the line drawn >> between things that should be enforced in bindings and things that only >> ever need to be specified once, so should just be left to the dt itself >> to be the source of truth? >> >> Having said that, I realise TI could spin a new SoC with a new dt but >> use the same compatible string for the GPU; > > No they can't. New SoC, new compatible. > We don't need to make a new SoC for that, our bus infra allows us to selectively include or exclude peripherals from coherency. The GPU being `dma-coherent` is selectable at boot time. Andrew >> the "single" source of truth >> then wouldn't be so single anymore. I guess by making this property >> required for this compatible string, we're saying any use of it must >> behave in exactly the same way, right?