[PATCH v3 0/6] add basic rk3288 smp support

[PATCH v3 0/6] add basic rk3288 smp support

[Kever Yang]

rk3288 is qual-core CPU Soc, we enable the smp in this patch.

In version 3 we use regmap and pmu syscon for cpu power on/off.
This should be work after Pankaj Dubey's patch applied:
(https://lkml.org/lkml/2014/9/30/156)

Changes in v3:
- add pmu regmap patches in version 3
- use one ops and secondary_starup for all rockchip SOCs
- pick back the power domain operation for cpu hotplug
- add compitable name "rockchip,rk3288-pmu-sram" for pmu-intmem

Changes in v2:
- use rk3288_boot_secondary instead ofsmp_boot_secondary
- discards the power domain operation
- handle the per cpu starup when actived by 'sev'
- adjust the alignment

Kever Yang (6):
  ARM: rockchip: convert to regmap and use pmu syscon if available
  ARM: dts: rockchip: use the same pmu node name as before
  ARM: rockchip: add option to access the pmu via a phandle in
    smp_operations
  ARM: dts: rockchip: add pmu references to cpus nodes
  ARM: rockchip: add basic smp support for rk3288
  ARM: dts: rockchip: add intmem node for rk3288 smp support

 arch/arm/boot/dts/rk3288.dtsi    |  21 ++++-
 arch/arm/mach-rockchip/headsmp.S |   5 +-
 arch/arm/mach-rockchip/platsmp.c | 188 +++++++++++++++++++++++++++++----------
 3 files changed, 167 insertions(+), 47 deletions(-)

-- 
1.9.1

[PATCH v3 1/6] ARM: rockchip: convert to regmap and use pmu syscon if available

[Kever Yang]

The pmu register space is - like the GRF - shared by quite some peripherals.
On the rk3188 and rk3288 even parts of the pinctrl are living there.
Therefore we normally shouldn't map it a second time when the syscon
does this already.

Therefore convert the cpu power-domain handling to access the pmu via a
regmap and at first try to get it via the syscon interface.
Getting this syscon will only fail if the pmu node does not have the
"syscon" compatible and thus does not get shared with other drivers.

In this case we map it like before and create the necessary regmap on
top of it.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

Changes in v3:
- add this patch in version 3

Changes in v2: None

 arch/arm/mach-rockchip/platsmp.c | 104 +++++++++++++++++++++++++++++----------
 1 file changed, 78 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 189684f..4c36fbf 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -19,6 +19,8 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
 
 #include <asm/cacheflush.h>
 #include <asm/cp15.h>
@@ -37,23 +39,42 @@ static int ncores;
 
 #define PMU_PWRDN_SCU		4
 
-static void __iomem *pmu_base_addr;
+static struct regmap *pmu;
 
-static inline bool pmu_power_domain_is_on(int pd)
+static int pmu_power_domain_is_on(int pd)
 {
-	return !(readl_relaxed(pmu_base_addr + PMU_PWRDN_ST) & BIT(pd));
+	u32 val;
+	int ret;
+
+	ret = regmap_read(pmu, PMU_PWRDN_ST, &val);
+	if (ret < 0)
+		return ret;
+
+	return !(val & BIT(pd));
 }
 
-static void pmu_set_power_domain(int pd, bool on)
+static int pmu_set_power_domain(int pd, bool on)
 {
-	u32 val = readl_relaxed(pmu_base_addr + PMU_PWRDN_CON);
-	if (on)
-		val &= ~BIT(pd);
-	else
-		val |=  BIT(pd);
-	writel(val, pmu_base_addr + PMU_PWRDN_CON);
-
-	while (pmu_power_domain_is_on(pd) != on) { }
+	u32 val = (on) ? 0 : BIT(pd);
+	int ret;
+
+	ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
+	if (ret < 0) {
+		pr_err("%s: could not update power domain\n", __func__);
+		return ret;
+	}
+
+	ret = -1;
+	while (ret != on) {
+		ret = pmu_power_domain_is_on(pd);
+		if (ret < 0) {
+			pr_err("%s: could not read power domain state\n",
+				 __func__);
+			return ret;
+		}
+	}
+
+	return 0;
 }
 
 /*
@@ -63,7 +84,7 @@ static void pmu_set_power_domain(int pd, bool on)
 static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
 					     struct task_struct *idle)
 {
-	if (!sram_base_addr || !pmu_base_addr) {
+	if (!sram_base_addr || !pmu) {
 		pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
 		return -ENXIO;
 	}
@@ -75,9 +96,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
 	}
 
 	/* start the core */
-	pmu_set_power_domain(0 + cpu, true);
-
-	return 0;
+	return pmu_set_power_domain(0 + cpu, true);
 }
 
 /**
@@ -125,6 +144,48 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
 	return 0;
 }
 
+static struct regmap_config rockchip_pmu_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+};
+
+static int __init rockchip_smp_prepare_pmu(void)
+{
+	struct device_node *node;
+	void __iomem *pmu_base;
+
+	pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
+	if (!IS_ERR(pmu))
+		return 0;
+
+	/* fallback, create our own regmap for the pmu area */
+	pmu = NULL;
+	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
+	if (!node) {
+		pr_err("%s: could not find pmu dt node\n", __func__);
+		return -ENODEV;
+	}
+
+	pmu_base = of_iomap(node, 0);
+	if (!pmu_base) {
+		pr_err("%s: could not map pmu registers\n", __func__);
+		return -ENOMEM;
+	}
+
+	pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config);
+	if (IS_ERR(pmu)) {
+		int ret = PTR_ERR(pmu);
+
+		iounmap(pmu_base);
+		pmu = NULL;
+		pr_err("%s: regmap init failed\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
+
 static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
 {
 	struct device_node *node;
@@ -151,17 +212,8 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
 	if (rockchip_smp_prepare_sram(node))
 		return;
 
-	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
-	if (!node) {
-		pr_err("%s: could not find pmu dt node\n", __func__);
+	if (rockchip_smp_prepare_pmu())
 		return;
-	}
-
-	pmu_base_addr = of_iomap(node, 0);
-	if (!pmu_base_addr) {
-		pr_err("%s: could not map pmu registers\n", __func__);
-		return;
-	}
 
 	/* enable the SCU power domain */
 	pmu_set_power_domain(PMU_PWRDN_SCU, true);
-- 
1.9.1

[PATCH v3 2/6] ARM: dts: rockchip: use the same pmu node name as before

[Kever Yang]

We use the "rockchip,rk3066-pmu" for rk3288 instead of creat
a new one.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

Changes in v3:
- add this patch in version 3

Changes in v2: None

 arch/arm/boot/dts/rk3288.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66d..06f39be 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -440,7 +440,7 @@
 	};
 
 	pmu: power-management at ff730000 {
-		compatible = "rockchip,rk3288-pmu", "syscon";
+		compatible = "rockchip,rk3066-pmu", "syscon";
 		reg = <0xff730000 0x100>;
 	};
 
-- 
1.9.1

[PATCH v3 3/6] ARM: rockchip: add option to access the pmu via a phandle in smp_operations

[Kever Yang]

Makes it possible to define a rockchip,pmu phandle in the cpus node directly
referencing the pmu syscon instead of searching for specific compatible.

The old way of finding the pmu stays of course available.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

Changes in v3:
- add this patch

Changes in v2: None

 arch/arm/mach-rockchip/platsmp.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 4c36fbf..57b53b3 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -155,6 +155,19 @@ static int __init rockchip_smp_prepare_pmu(void)
 	struct device_node *node;
 	void __iomem *pmu_base;
 
+	/*
+	 * This function is only called via smp_ops->smp_prepare_cpu().
+	 * That only happens if a "/cpus" device tree node exists
+	 * and has an "enable-method" property that selects the SMP
+	 * operations defined herein.
+	 */
+	node = of_find_node_by_path("/cpus");
+
+	pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu");
+	of_node_put(node);
+	if (!IS_ERR(pmu))
+		return 0;
+
 	pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
 	if (!IS_ERR(pmu))
 		return 0;
-- 
1.9.1

[PATCH v3 4/6] ARM: dts: rockchip: add pmu references to cpus nodes

[Kever Yang]

This patch add pmu reference and enable-method for smp

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

Changes in v3:
- add this patch

Changes in v2: None

 arch/arm/boot/dts/rk3288.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 06f39be..44108fe 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -46,6 +46,8 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "rockchip,rk3066-smp";
+		rockchip,pmu = <&pmu>;
 
 		cpu at 500 {
 			device_type = "cpu";
-- 
1.9.1

[PATCH v3 5/6] ARM: rockchip: add basic smp support for rk3288

[Kever Yang]

This patch add basic rk3288 smp support.

Only cortex-A9 need invalid L1, A7/A12/A15/A17 should not invalid L1, since
for A7/A12/A15, the invalidation would be taken as clean and invalidate.

If you use the software manual invalidation instead of hardware invalidation
(assert l1/l2rstdisable during reset) after reset, there is tiny change that
some cachelines would be in dirty and valid state after reset(since the ram
content would be random value after reset), then the unexpected clean might
lead to system crash.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

Changes in v3:
- use one ops and secondary_starup for all rockchip SOCs
- pick back the power domain operation for cpu hotplug

Changes in v2:
- use rk3288_boot_secondary instead ofsmp_boot_secondary
- discards the power domain operation
- handle the per cpu starup when actived by 'sev'

 arch/arm/mach-rockchip/headsmp.S |  5 ++-
 arch/arm/mach-rockchip/platsmp.c | 81 ++++++++++++++++++++++++++++------------
 2 files changed, 61 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-rockchip/headsmp.S b/arch/arm/mach-rockchip/headsmp.S
index 73206e3..46c22de 100644
--- a/arch/arm/mach-rockchip/headsmp.S
+++ b/arch/arm/mach-rockchip/headsmp.S
@@ -16,7 +16,10 @@
 #include <linux/init.h>
 
 ENTRY(rockchip_secondary_startup)
-	bl	v7_invalidate_l1
+	mrc	p15, 0, r0, c0, c0, 0	@ read main ID register
+	ldr	r1, =0x00000c09		@ Cortex-A9 primary part number
+	teq	r0, r1
+	beq	v7_invalidate_l1
 	b	secondary_startup
 ENDPROC(rockchip_secondary_startup)
 
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 57b53b3..d1f858e 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -84,6 +84,8 @@ static int pmu_set_power_domain(int pd, bool on)
 static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
 					     struct task_struct *idle)
 {
+	int ret;
+
 	if (!sram_base_addr || !pmu) {
 		pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
 		return -ENXIO;
@@ -96,7 +98,26 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
 	}
 
 	/* start the core */
-	return pmu_set_power_domain(0 + cpu, true);
+	ret = pmu_set_power_domain(0 + cpu, true);
+	if (ret < 0)
+		return ret;
+
+	if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
+		/* We communicate with the bootrom to active the cpus other
+		 * than cpu0, after a blob of initialize code, they will
+		 * stay@wfe state, once they are actived, they will check
+		 * the mailbox:
+		 * sram_base_addr + 4: 0xdeadbeaf
+		 * sram_base_addr + 8: start address for pc
+		 * */
+		udelay(10);
+		writel(virt_to_phys(rockchip_secondary_startup),
+			sram_base_addr + 8);
+		writel(0xDEADBEAF, sram_base_addr + 4);
+		dsb_sev();
+	}
+
+	return 0;
 }
 
 /**
@@ -129,8 +150,6 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
 		return -EINVAL;
 	}
 
-	sram_base_addr = of_iomap(node, 0);
-
 	/* set the boot function for the sram code */
 	rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup);
 
@@ -203,18 +222,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
 {
 	struct device_node *node;
 	unsigned int i;
-
-	node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
-	if (!node) {
-		pr_err("%s: missing scu\n", __func__);
-		return;
-	}
-
-	scu_base_addr = of_iomap(node, 0);
-	if (!scu_base_addr) {
-		pr_err("%s: could not map scu registers\n", __func__);
-		return;
-	}
+	unsigned int l2ctlr;
 
 	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
 	if (!node) {
@@ -222,22 +230,47 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
 		return;
 	}
 
-	if (rockchip_smp_prepare_sram(node))
+	sram_base_addr = of_iomap(node, 0);
+	if (!sram_base_addr) {
+		pr_err("%s: could not map sram registers\n", __func__);
 		return;
+	}
 
 	if (rockchip_smp_prepare_pmu())
 		return;
 
-	/* enable the SCU power domain */
-	pmu_set_power_domain(PMU_PWRDN_SCU, true);
+	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
+		if (rockchip_smp_prepare_sram(node))
+			return;
 
-	/*
-	 * While the number of cpus is gathered from dt, also get the number
-	 * of cores from the scu to verify this value when booting the cores.
-	 */
-	ncores = scu_get_core_count(scu_base_addr);
+		/* enable the SCU power domain */
+		pmu_set_power_domain(PMU_PWRDN_SCU, true);
+
+		node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+		if (!node) {
+			pr_err("%s: missing scu\n", __func__);
+			return;
+		}
 
-	scu_enable(scu_base_addr);
+		scu_base_addr = of_iomap(node, 0);
+		if (!scu_base_addr) {
+			pr_err("%s: could not map scu registers\n", __func__);
+			return;
+		}
+
+		/*
+		 * While the number of cpus is gathered from dt, also get the
+		 * number of cores from the scu to verify this value when
+		 * booting the cores.
+		 */
+		ncores = scu_get_core_count(scu_base_addr);
+		pr_err("%s: ncores %d\n", __func__, ncores);
+
+		scu_enable(scu_base_addr);
+	} else {
+		asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
+		ncores = ((l2ctlr >> 24) & 0x3) + 1;
+	}
 
 	/* Make sure that all cores except the first are really off */
 	for (i = 1; i < ncores; i++)
-- 
1.9.1

[PATCH v3 6/6] ARM: dts: rockchip: add intmem node for rk3288 smp support

[Kever Yang]

This patch add intmem node des which is needed by platsmp.c

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

Changes in v3:
- remove 'enable-method' from this patch
- add compitable name "rockchip,rk3288-pmu-sram" for pmu-intmem

Changes in v2:
- adjust the alignment

 arch/arm/boot/dts/rk3288.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 44108fe..5e9c56d 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -441,6 +441,23 @@
 		status = "disabled";
 	};
 
+	bus_intmem at ff700000 {
+		compatible = "mmio-sram";
+		reg = <0xff700000 0x18000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xff700000 0x18000>;
+		smp-sram at 0 {
+			compatible = "rockchip,rk3066-smp-sram";
+			reg = <0x00 0x10>;
+		};
+	};
+
+	pmu_intmem at ff720000 {
+		compatible = "mmio-sram", "rockchip,rk3288-pmu-sram";
+		reg = <0xff720000 0x4000>;
+	};
+
 	pmu: power-management at ff730000 {
 		compatible = "rockchip,rk3066-pmu", "syscon";
 		reg = <0xff730000 0x100>;
-- 
1.9.1

[PATCH v3 1/6] ARM: rockchip: convert to regmap and use pmu syscon if available

[Heiko Stübner]

Hi Kever,

it would be nice if we could keep my authorship of this patch ;-)

So it should have a line
From: Heiko Stuebner <heiko@sntech.de>

at the top followed by a blank line before the commit message below.

Heiko

Am Freitag, 10. Oktober 2014, 14:26:05 schrieb Kever Yang:
> The pmu register space is - like the GRF - shared by quite some peripherals.
> On the rk3188 and rk3288 even parts of the pinctrl are living there.
> Therefore we normally shouldn't map it a second time when the syscon does
> this already.
> 
> Therefore convert the cpu power-domain handling to access the pmu via a
> regmap and at first try to get it via the syscon interface.
> Getting this syscon will only fail if the pmu node does not have the
> "syscon" compatible and thus does not get shared with other drivers.
> 
> In this case we map it like before and create the necessary regmap on
> top of it.
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
> Changes in v3:
> - add this patch in version 3
> 
> Changes in v2: None
> 
>  arch/arm/mach-rockchip/platsmp.c | 104
> +++++++++++++++++++++++++++++---------- 1 file changed, 78 insertions(+),
> 26 deletions(-)
> 
> diff --git a/arch/arm/mach-rockchip/platsmp.c
> b/arch/arm/mach-rockchip/platsmp.c index 189684f..4c36fbf 100644
> --- a/arch/arm/mach-rockchip/platsmp.c
> +++ b/arch/arm/mach-rockchip/platsmp.c
> @@ -19,6 +19,8 @@
>  #include <linux/io.h>
>  #include <linux/of.h>
>  #include <linux/of_address.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> 
>  #include <asm/cacheflush.h>
>  #include <asm/cp15.h>
> @@ -37,23 +39,42 @@ static int ncores;
> 
>  #define PMU_PWRDN_SCU		4
> 
> -static void __iomem *pmu_base_addr;
> +static struct regmap *pmu;
> 
> -static inline bool pmu_power_domain_is_on(int pd)
> +static int pmu_power_domain_is_on(int pd)
>  {
> -	return !(readl_relaxed(pmu_base_addr + PMU_PWRDN_ST) & BIT(pd));
> +	u32 val;
> +	int ret;
> +
> +	ret = regmap_read(pmu, PMU_PWRDN_ST, &val);
> +	if (ret < 0)
> +		return ret;
> +
> +	return !(val & BIT(pd));
>  }
> 
> -static void pmu_set_power_domain(int pd, bool on)
> +static int pmu_set_power_domain(int pd, bool on)
>  {
> -	u32 val = readl_relaxed(pmu_base_addr + PMU_PWRDN_CON);
> -	if (on)
> -		val &= ~BIT(pd);
> -	else
> -		val |=  BIT(pd);
> -	writel(val, pmu_base_addr + PMU_PWRDN_CON);
> -
> -	while (pmu_power_domain_is_on(pd) != on) { }
> +	u32 val = (on) ? 0 : BIT(pd);
> +	int ret;
> +
> +	ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
> +	if (ret < 0) {
> +		pr_err("%s: could not update power domain\n", __func__);
> +		return ret;
> +	}
> +
> +	ret = -1;
> +	while (ret != on) {
> +		ret = pmu_power_domain_is_on(pd);
> +		if (ret < 0) {
> +			pr_err("%s: could not read power domain state\n",
> +				 __func__);
> +			return ret;
> +		}
> +	}
> +
> +	return 0;
>  }
> 
>  /*
> @@ -63,7 +84,7 @@ static void pmu_set_power_domain(int pd, bool on)
>  static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
>  					     struct task_struct *idle)
>  {
> -	if (!sram_base_addr || !pmu_base_addr) {
> +	if (!sram_base_addr || !pmu) {
>  		pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
>  		return -ENXIO;
>  	}
> @@ -75,9 +96,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int
> cpu, }
> 
>  	/* start the core */
> -	pmu_set_power_domain(0 + cpu, true);
> -
> -	return 0;
> +	return pmu_set_power_domain(0 + cpu, true);
>  }
> 
>  /**
> @@ -125,6 +144,48 @@ static int __init rockchip_smp_prepare_sram(struct
> device_node *node) return 0;
>  }
> 
> +static struct regmap_config rockchip_pmu_regmap_config = {
> +	.reg_bits = 32,
> +	.val_bits = 32,
> +	.reg_stride = 4,
> +};
> +
> +static int __init rockchip_smp_prepare_pmu(void)
> +{
> +	struct device_node *node;
> +	void __iomem *pmu_base;
> +
> +	pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
> +	if (!IS_ERR(pmu))
> +		return 0;
> +
> +	/* fallback, create our own regmap for the pmu area */
> +	pmu = NULL;
> +	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
> +	if (!node) {
> +		pr_err("%s: could not find pmu dt node\n", __func__);
> +		return -ENODEV;
> +	}
> +
> +	pmu_base = of_iomap(node, 0);
> +	if (!pmu_base) {
> +		pr_err("%s: could not map pmu registers\n", __func__);
> +		return -ENOMEM;
> +	}
> +
> +	pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config);
> +	if (IS_ERR(pmu)) {
> +		int ret = PTR_ERR(pmu);
> +
> +		iounmap(pmu_base);
> +		pmu = NULL;
> +		pr_err("%s: regmap init failed\n", __func__);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
>  static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
>  {
>  	struct device_node *node;
> @@ -151,17 +212,8 @@ static void __init rockchip_smp_prepare_cpus(unsigned
> int max_cpus) if (rockchip_smp_prepare_sram(node))
>  		return;
> 
> -	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
> -	if (!node) {
> -		pr_err("%s: could not find pmu dt node\n", __func__);
> +	if (rockchip_smp_prepare_pmu())
>  		return;
> -	}
> -
> -	pmu_base_addr = of_iomap(node, 0);
> -	if (!pmu_base_addr) {
> -		pr_err("%s: could not map pmu registers\n", __func__);
> -		return;
> -	}
> 
>  	/* enable the SCU power domain */
>  	pmu_set_power_domain(PMU_PWRDN_SCU, true);

[PATCH v3 2/6] ARM: dts: rockchip: use the same pmu node name as before

[Heiko Stübner]

Am Freitag, 10. Oktober 2014, 14:26:06 schrieb Kever Yang:
> We use the "rockchip,rk3066-pmu" for rk3288 instead of creat
> a new one.

No, it should stay keep the rk3288-pmu compatible. While the 4 powerdomains 
for the cores are similar, the pmu in general is very much specific to the 
rk3288.

Also, this renaming of the pmu compatible only is a workaround for the 
underlying problem, that your tree is probably missing the early syscon 
support and there falling back to mapping the node directly.

If you apply the patch 
	[PATCH v7] mfd: syscon: Decouple syscon interface from platform devices
to your tree, it will work as expected by really using the pmu reference from 
patch3 - it did for me - making this patch unnecessary.


Heiko

> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
> Changes in v3:
> - add this patch in version 3
> 
> Changes in v2: None
> 
>  arch/arm/boot/dts/rk3288.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index 874e66d..06f39be 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -440,7 +440,7 @@
>  	};
> 
>  	pmu: power-management at ff730000 {
> -		compatible = "rockchip,rk3288-pmu", "syscon";
> +		compatible = "rockchip,rk3066-pmu", "syscon";
>  		reg = <0xff730000 0x100>;
>  	};

[PATCH v3 3/6] ARM: rockchip: add option to access the pmu via a phandle in smp_operations

[Heiko Stübner]

Hi Kever,

again authorship please :-) .

Also my original patch did include a change to document the new rockchip,pmu 
property in Documentation/devicetree/bindings/arm/cpus.txt which should of 
course be again included here.


Heiko

Am Freitag, 10. Oktober 2014, 14:26:07 schrieb Kever Yang:
> Makes it possible to define a rockchip,pmu phandle in the cpus node directly
> referencing the pmu syscon instead of searching for specific compatible.
> 
> The old way of finding the pmu stays of course available.
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
> Changes in v3:
> - add this patch
> 
> Changes in v2: None
> 
>  arch/arm/mach-rockchip/platsmp.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/arm/mach-rockchip/platsmp.c
> b/arch/arm/mach-rockchip/platsmp.c index 4c36fbf..57b53b3 100644
> --- a/arch/arm/mach-rockchip/platsmp.c
> +++ b/arch/arm/mach-rockchip/platsmp.c
> @@ -155,6 +155,19 @@ static int __init rockchip_smp_prepare_pmu(void)
>  	struct device_node *node;
>  	void __iomem *pmu_base;
> 
> +	/*
> +	 * This function is only called via smp_ops->smp_prepare_cpu().
> +	 * That only happens if a "/cpus" device tree node exists
> +	 * and has an "enable-method" property that selects the SMP
> +	 * operations defined herein.
> +	 */
> +	node = of_find_node_by_path("/cpus");
> +
> +	pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu");
> +	of_node_put(node);
> +	if (!IS_ERR(pmu))
> +		return 0;
> +
>  	pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
>  	if (!IS_ERR(pmu))
>  		return 0;

[PATCH v3 4/6] ARM: dts: rockchip: add pmu references to cpus nodes

[Heiko Stübner]

Am Freitag, 10. Oktober 2014, 14:26:08 schrieb Kever Yang:
> This patch add pmu reference and enable-method for smp
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>

there should be no Signed-off from me be included here.


> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
> Changes in v3:
> - add this patch
> 
> Changes in v2: None
> 
>  arch/arm/boot/dts/rk3288.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index 06f39be..44108fe 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -46,6 +46,8 @@
>  	cpus {
>  		#address-cells = <1>;
>  		#size-cells = <0>;
> +		enable-method = "rockchip,rk3066-smp";
> +		rockchip,pmu = <&pmu>;
> 
>  		cpu at 500 {
>  			device_type = "cpu";

[PATCH v3 5/6] ARM: rockchip: add basic smp support for rk3288

[Heiko Stübner]

Am Freitag, 10. Oktober 2014, 14:26:09 schrieb Kever Yang:
> This patch add basic rk3288 smp support.
> 
> Only cortex-A9 need invalid L1, A7/A12/A15/A17 should not invalid L1, since
> for A7/A12/A15, the invalidation would be taken as clean and invalidate.
> 
> If you use the software manual invalidation instead of hardware invalidation
> (assert l1/l2rstdisable during reset) after reset, there is tiny change
> that some cachelines would be in dirty and valid state after reset(since
> the ram content would be random value after reset), then the unexpected
> clean might lead to system crash.
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
> Changes in v3:
> - use one ops and secondary_starup for all rockchip SOCs
> - pick back the power domain operation for cpu hotplug
> 
> Changes in v2:
> - use rk3288_boot_secondary instead ofsmp_boot_secondary
> - discards the power domain operation
> - handle the per cpu starup when actived by 'sev'
> 
>  arch/arm/mach-rockchip/headsmp.S |  5 ++-
>  arch/arm/mach-rockchip/platsmp.c | 81
> ++++++++++++++++++++++++++++------------ 2 files changed, 61 insertions(+),
> 25 deletions(-)
> 
> diff --git a/arch/arm/mach-rockchip/headsmp.S
> b/arch/arm/mach-rockchip/headsmp.S index 73206e3..46c22de 100644
> --- a/arch/arm/mach-rockchip/headsmp.S
> +++ b/arch/arm/mach-rockchip/headsmp.S
> @@ -16,7 +16,10 @@
>  #include <linux/init.h>
> 
>  ENTRY(rockchip_secondary_startup)
> -	bl	v7_invalidate_l1
> +	mrc	p15, 0, r0, c0, c0, 0	@ read main ID register
> +	ldr	r1, =0x00000c09		@ Cortex-A9 primary part number
> +	teq	r0, r1
> +	beq	v7_invalidate_l1
>  	b	secondary_startup
>  ENDPROC(rockchip_secondary_startup)
> 
> diff --git a/arch/arm/mach-rockchip/platsmp.c
> b/arch/arm/mach-rockchip/platsmp.c index 57b53b3..d1f858e 100644
> --- a/arch/arm/mach-rockchip/platsmp.c
> +++ b/arch/arm/mach-rockchip/platsmp.c
> @@ -84,6 +84,8 @@ static int pmu_set_power_domain(int pd, bool on)
>  static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
>  					     struct task_struct *idle)
>  {
> +	int ret;
> +
>  	if (!sram_base_addr || !pmu) {
>  		pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
>  		return -ENXIO;
> @@ -96,7 +98,26 @@ static int __cpuinit rockchip_boot_secondary(unsigned int
> cpu, }
> 
>  	/* start the core */
> -	return pmu_set_power_domain(0 + cpu, true);
> +	ret = pmu_set_power_domain(0 + cpu, true);
> +	if (ret < 0)
> +		return ret;
> +
> +	if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
> +		/* We communicate with the bootrom to active the cpus other
> +		 * than cpu0, after a blob of initialize code, they will
> +		 * stay at wfe state, once they are actived, they will check
> +		 * the mailbox:
> +		 * sram_base_addr + 4: 0xdeadbeaf
> +		 * sram_base_addr + 8: start address for pc
> +		 * */
> +		udelay(10);
> +		writel(virt_to_phys(rockchip_secondary_startup),
> +			sram_base_addr + 8);
> +		writel(0xDEADBEAF, sram_base_addr + 4);
> +		dsb_sev();
> +	}
> +
> +	return 0;
>  }
> 
>  /**
> @@ -129,8 +150,6 @@ static int __init rockchip_smp_prepare_sram(struct
> device_node *node) return -EINVAL;
>  	}
> 
> -	sram_base_addr = of_iomap(node, 0);
> -
>  	/* set the boot function for the sram code */
>  	rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup);
> 
> @@ -203,18 +222,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned
> int max_cpus) {
>  	struct device_node *node;
>  	unsigned int i;
> -
> -	node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
> -	if (!node) {
> -		pr_err("%s: missing scu\n", __func__);
> -		return;
> -	}
> -
> -	scu_base_addr = of_iomap(node, 0);
> -	if (!scu_base_addr) {
> -		pr_err("%s: could not map scu registers\n", __func__);
> -		return;
> -	}
> +	unsigned int l2ctlr;

please move this l2ctlr below inside the else branch - as it's only used 
there.


> 
>  	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
>  	if (!node) {
> @@ -222,22 +230,47 @@ static void __init rockchip_smp_prepare_cpus(unsigned
> int max_cpus) return;
>  	}
> 
> -	if (rockchip_smp_prepare_sram(node))
> +	sram_base_addr = of_iomap(node, 0);
> +	if (!sram_base_addr) {
> +		pr_err("%s: could not map sram registers\n", __func__);
>  		return;
> +	}
> 
>  	if (rockchip_smp_prepare_pmu())
>  		return;
> 
> -	/* enable the SCU power domain */
> -	pmu_set_power_domain(PMU_PWRDN_SCU, true);
> +	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
> +		if (rockchip_smp_prepare_sram(node))
> +			return;
> 
> -	/*
> -	 * While the number of cpus is gathered from dt, also get the number
> -	 * of cores from the scu to verify this value when booting the cores.
> -	 */
> -	ncores = scu_get_core_count(scu_base_addr);
> +		/* enable the SCU power domain */
> +		pmu_set_power_domain(PMU_PWRDN_SCU, true);
> +
> +		node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
> +		if (!node) {
> +			pr_err("%s: missing scu\n", __func__);
> +			return;
> +		}
> 
> -	scu_enable(scu_base_addr);
> +		scu_base_addr = of_iomap(node, 0);
> +		if (!scu_base_addr) {
> +			pr_err("%s: could not map scu registers\n", __func__);
> +			return;
> +		}
> +
> +		/*
> +		 * While the number of cpus is gathered from dt, also get the
> +		 * number of cores from the scu to verify this value when
> +		 * booting the cores.
> +		 */
> +		ncores = scu_get_core_count(scu_base_addr);
> +		pr_err("%s: ncores %d\n", __func__, ncores);
> +
> +		scu_enable(scu_base_addr);
> +	} else {

-> here

> +		asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
> +		ncores = ((l2ctlr >> 24) & 0x3) + 1;
> +	}
> 
>  	/* Make sure that all cores except the first are really off */
>  	for (i = 1; i < ncores; i++)

[PATCH v3 6/6] ARM: dts: rockchip: add intmem node for rk3288 smp support

[Heiko Stübner]

Am Freitag, 10. Oktober 2014, 14:26:10 schrieb Kever Yang:
> This patch add intmem node des which is needed by platsmp.c
> 
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>

again without this Signed-off please (also true for patch 5/6 where I forgot to 
mention it)

> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
> Changes in v3:
> - remove 'enable-method' from this patch
> - add compitable name "rockchip,rk3288-pmu-sram" for pmu-intmem
> 
> Changes in v2:
> - adjust the alignment
> 
>  arch/arm/boot/dts/rk3288.dtsi | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index 44108fe..5e9c56d 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -441,6 +441,23 @@
>  		status = "disabled";
>  	};
> 
> +	bus_intmem at ff700000 {
> +		compatible = "mmio-sram";
> +		reg = <0xff700000 0x18000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0xff700000 0x18000>;
> +		smp-sram at 0 {
> +			compatible = "rockchip,rk3066-smp-sram";
> +			reg = <0x00 0x10>;
> +		};
> +	};
> +
> +	pmu_intmem at ff720000 {
> +		compatible = "mmio-sram", "rockchip,rk3288-pmu-sram";

general rule, the more specific compatible should be in front, so
		compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";

This way, if there is a driver for "rockchip,rk3288-pmu-sram" at some point in 
the future, it will grab the node before the more generic sram driver does.

But in general, what is the pmu sram necessary for, as no part of this series 
uses it?

> +		reg = <0xff720000 0x4000>;
> +	};
> +
>  	pmu: power-management at ff730000 {
>  		compatible = "rockchip,rk3066-pmu", "syscon";
>  		reg = <0xff730000 0x100>;

[PATCH v3 0/6] add basic rk3288 smp support

[Heiko Stübner]

Hi Kever,

Am Freitag, 10. Oktober 2014, 14:26:04 schrieb Kever Yang:
> rk3288 is qual-core CPU Soc, we enable the smp in this patch.
> 
> In version 3 we use regmap and pmu syscon for cpu power on/off.
> This should be work after Pankaj Dubey's patch applied:
> (https://lkml.org/lkml/2014/9/30/156)

I've tested this series on both a rk3188 as well as a rk3288 and was 
sucessfully getting the secondary cores bootet.

I did not include patch2 in this, as the whole thing also works when applying 
the syscon-patch I mention in an individual reply - which also already got 
accepted for 3.19.


Heiko