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Thu, 20 Aug 2026 18:02:22 +0200 (CEST) Message-ID: <61537689daa428a577e6bdab794d044f5405128e.camel@collabora.com> Subject: Re: [PATCH 5/7] media: verisilicon: Add Rockchip VPU720 JPEG decoder From: Nicolas Dufresne To: Sascha Hauer Cc: Benjamin Gaignard , Philipp Zabel , Mauro Carvalho Chehab , Heiko Stuebner , Ezequiel Garcia , Andrzej Pietrasiewicz , Hans Verkuil , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lucas Sinn , Mauro Carvalho Chehab , linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Date: Thu, 20 Aug 2026 12:02:20 -0400 In-Reply-To: <5436875c-9724-41f3-aaf9-76d43e05f0a8@pengutronix.de> References: <20260819-rk3588-jpegdec-v1-0-33d74cdf369c@pengutronix.de> <20260819-rk3588-jpegdec-v1-5-33d74cdf369c@pengutronix.de> <2816bd84651dcbfd0cd76bbc56e461bd409f9611.camel@collabora.com> <5436875c-9724-41f3-aaf9-76d43e05f0a8@pengutronix.de> Autocrypt: addr=nicolas.dufresne@collabora.com; prefer-encrypt=mutual; keydata=mDMEaCN2ixYJKwYBBAHaRw8BAQdAM0EHepTful3JOIzcPv6ekHOenE1u0vDG1gdHFrChD /e0J05pY29sYXMgRHVmcmVzbmUgPG5pY29sYXNAbmR1ZnJlc25lLmNhPoicBBMWCgBEAhsDBQsJCA cCAiICBhUKCQgLAgQWAgMBAh4HAheABQkJZfd1FiEE7w1SgRXEw8IaBG8S2UGUUSlgcvQFAmibrjo CGQEACgkQ2UGUUSlgcvQlQwD/RjpU1SZYcKG6pnfnQ8ivgtTkGDRUJ8gP3fK7+XUjRNIA/iXfhXMN abIWxO2oCXKf3TdD7aQ4070KO6zSxIcxgNQFtDFOaWNvbGFzIER1ZnJlc25lIDxuaWNvbGFzLmR1Z nJlc25lQGNvbGxhYm9yYS5jb20+iJkEExYKAEECGwMFCwkIBwICIgIGFQoJCAsCBBYCAwECHgcCF4 AWIQTvDVKBFcTDwhoEbxLZQZRRKWBy9AUCaCyyxgUJCWX3dQAKCRDZQZRRKWBy9ARJAP96pFmLffZ smBUpkyVBfFAf+zq6BJt769R0al3kHvUKdgD9G7KAHuioxD2v6SX7idpIazjzx8b8rfzwTWyOQWHC AAS0LU5pY29sYXMgRHVmcmVzbmUgPG5pY29sYXMuZHVmcmVzbmVAZ21haWwuY29tPoiZBBMWCgBBF iEE7w1SgRXEw8IaBG8S2UGUUSlgcvQFAmibrGYCGwMFCQll93UFCwkIBwICIgIGFQoJCAsCBBYCAw ECHgcCF4AACgkQ2UGUUSlgcvRObgD/YnQjfi4+L8f4fI7p1pPMTwRTcaRdy6aqkKEmKsCArzQBAK8 bRLv9QjuqsE6oQZra/RB4widZPvphs78H0P6NmpIJ Organization: Collabora Canada Content-Type: multipart/signed; micalg="pgp-sha512"; protocol="application/pgp-signature"; boundary="=-Sh7xuFpFF+Uoq55bNVgI" User-Agent: Evolution 3.60.2 (3.60.2-1.fc44) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260820_090227_995212_66CF8B9B X-CRM114-Status: GOOD ( 17.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --=-Sh7xuFpFF+Uoq55bNVgI Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Sascha, Le jeudi 20 ao=C3=BBt 2026 =C3=A0 10:03 +0000, Sascha Hauer a =C3=A9crit=C2= =A0: > On 2026-08-19 11:48, Nicolas Dufresne wrote: > > Hi Sascha, > >=20 > > Le mercredi 19 ao=C3=BBt 2026 =C3=A0 12:37 +0200, Sascha Hauer a =C3=A9= crit=C2=A0: > > > +/* -----------------------------------------------------------------= - */ > > > +/* Register byte offsets from dec_base=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 */ > > > +/* -----------------------------------------------------------------= - */ > > > + > > > +/* REG0: IP version / product ID */ > > > +#define VDPU720_REG_VERSION 0x000 > > > +#define VDPU720_PROD_NUM GENMASK(31, 16) > > > +#define VDPU720_BIT_DEPTH BIT(8) > >=20 > > Can you share a dump and share these register reset values. Looking at = the > > layout, clearly its highly modified, but probably derived from VSI mult= i-codec, > > but I'm thinking perhaps we'll learn more from that. Its always nice to= justify > > when adding more chips that are not strictly VSI designs (or maybe it i= s) to the > > hantro dirver. >=20 > Here's a full register dump right after reset: >=20 > 00000000: db1f0005 00000004 00120000 00000000 I've look around as much as I could, and could not find any indication that= this is an IP from VSI or derived from a VSI core. It is entirely different from vdpu1 in mpp (proper G1, rk3288 and similar) and vdpu2 (modified G1 / VDPU1= 21). In short, this is not a multi-codec core. So that ball is on your end to show that this driver belongs to hantro rath= er then its own driver. In absence of evidence, this driver should be part of rockchip vendor folder, not vsi. Don't read me wrong, I trust that you have tested what the LLM have chosen, but anything can be implement in Hantro re= ally, it does not mean it should be there. Nicolas > 00000010: 00004400 00000000 00000000 00000000 > 00000020: 00000000 00000000 00000000 00000000 > 00000030: 00000000 00000000 00000000 00000000 > 00000040: 000000ff 00000000 00000000 00000000 > 00000050: 00000000 00000000 00000000 00000000 > 00000060: 00000000 00000000 00000000 00000000 > 00000070: 00000000 00000000 000000a8 00000001 > 00000080: 00200000 00080f06 00000000 00000000 > 00000090: 00000000 00000000 00000000 00000000 > 000000a0: 00040000 00001556 00000000 00000000 > 000000b0: 00000000 00000000 00000000 00000000 > ... > 000003f0: 00000000 00000000 00000000 00000000 >=20 > Sascha --=-Sh7xuFpFF+Uoq55bNVgI Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTvDVKBFcTDwhoEbxLZQZRRKWBy9AUCaoclDAAKCRDZQZRRKWBy 9J71AQDIPC+bWNjjlyxNCjQSdvKc/XKLnolosfjxhlZ4DMvNMQD/U+0qQgLG7T19 Z4oo+bnV8HuZ4bzEtkpq2qUeEgaEiwk= =SqwL -----END PGP SIGNATURE----- --=-Sh7xuFpFF+Uoq55bNVgI--