[PATCH 0/5] clock: imx95: Add LVDS/DISPLAY CSR for i.MX94

[PATCH 0/5] clock: imx95: Add LVDS/DISPLAY CSR for i.MX94

[Peng Fan]

Similar to i.MX95, i.MX94 also has LVDS/DISPLAY CSR to provide
clock gate for LVDS and DISPLAY Controller. So following same approach
to add the support, as what have been done for i.MX95.

Patch 1 is to add the binding doc.
Patch 2 and 3 are fixes when supporting i.MX94, but the issues are
also exposed to i.MX95 even not triggered. No need to rush the
two patches for 6.16.
Patch 4 and 5 is to add the clk driver. Patch 4 is almost picked from
NXP downstream with a minor update. Patch 5 is modified from NXP
downstream with a few minor patches merged and updated.
Patch 6 is the dts part to give reviewer a whole view on how it is used.

Thanks for Frank Li helping do NXP internal review for the patchset.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Laurentiu Palcu (1):
      clk: imx95-blk-ctl: Fix synchronous abort

Peng Fan (3):
      dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR
      clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR
      arm64: dts: imx943: Add LVDS/DISPLAY CSR nodes

Sandor Yu (1):
      clk: imx95-blk-ctl: Rename lvds and displaymix csr blk

 .../bindings/clock/nxp,imx95-blk-ctl.yaml          |  2 +
 arch/arm64/boot/dts/freescale/imx943.dtsi          | 34 ++++++++
 drivers/clk/imx/clk-imx95-blk-ctl.c                | 93 +++++++++++++++++-----
 include/dt-bindings/clock/nxp,imx94-clock.h        | 13 +++
 4 files changed, 120 insertions(+), 22 deletions(-)
---
base-commit: ecb259c4f70dd5c83907809f45bf4dc6869961d7
change-id: 20250701-imx95-blk-ctl-7-1-e9f82be61980

Best regards,
-- 
Peng Fan <peng.fan@nxp.com>

[PATCH 1/5] dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR

[Peng Fan]

Add i.MX94 LVDS/DISPLAY CSR compatible string.

Add clock index for the two CSRs.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 .../devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml        |  2 ++
 include/dt-bindings/clock/nxp,imx94-clock.h                 | 13 +++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
index d0291bfff23a27cb55683880fe3a1f8b3e2ada5a..4e20e8c8663b3b6665ff91ae63e1539aa8e9cc9b 100644
--- a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
+++ b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
@@ -19,6 +19,8 @@ properties:
           - nxp,imx95-lvds-csr
           - nxp,imx95-netcmix-blk-ctrl
           - nxp,imx95-vpu-csr
+          - nxp,imx94-display-csr
+          - nxp,imx94-lvds-csr
       - const: syscon
 
   reg:
diff --git a/include/dt-bindings/clock/nxp,imx94-clock.h b/include/dt-bindings/clock/nxp,imx94-clock.h
new file mode 100644
index 0000000000000000000000000000000000000000..b47f74f00f119ff1c1e6dad885b5b1e3b1f248a1
--- /dev/null
+++ b/include/dt-bindings/clock/nxp,imx94-clock.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX94_H
+#define __DT_BINDINGS_CLOCK_IMX94_H
+
+#define IMX94_CLK_DISPMIX_CLK_SEL	0
+
+#define IMX94_CLK_DISPMIX_LVDS_CLK_GATE	0
+
+#endif /* __DT_BINDINGS_CLOCK_IMX94_H */

-- 
2.37.1

Re: [PATCH 1/5] dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR

[Alexander Stein]

Hi,

thanks for the patch.

Am Dienstag, 1. Juli 2025, 09:04:37 CEST schrieb Peng Fan:
> Add i.MX94 LVDS/DISPLAY CSR compatible string.
> 
> Add clock index for the two CSRs.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  .../devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml        |  2 ++
>  include/dt-bindings/clock/nxp,imx94-clock.h                 | 13 +++++++++++++
>  2 files changed, 15 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
> index d0291bfff23a27cb55683880fe3a1f8b3e2ada5a..4e20e8c8663b3b6665ff91ae63e1539aa8e9cc9b 100644
> --- a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
> +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
> @@ -19,6 +19,8 @@ properties:
>            - nxp,imx95-lvds-csr
>            - nxp,imx95-netcmix-blk-ctrl
>            - nxp,imx95-vpu-csr
> +          - nxp,imx94-display-csr
> +          - nxp,imx94-lvds-csr

Please sort them properly

Best regards,
Alexander

>        - const: syscon
>  
>    reg:
> diff --git a/include/dt-bindings/clock/nxp,imx94-clock.h b/include/dt-bindings/clock/nxp,imx94-clock.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..b47f74f00f119ff1c1e6dad885b5b1e3b1f248a1
> --- /dev/null
> +++ b/include/dt-bindings/clock/nxp,imx94-clock.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
> +/*
> + * Copyright 2025 NXP
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_IMX94_H
> +#define __DT_BINDINGS_CLOCK_IMX94_H
> +
> +#define IMX94_CLK_DISPMIX_CLK_SEL	0
> +
> +#define IMX94_CLK_DISPMIX_LVDS_CLK_GATE	0
> +
> +#endif /* __DT_BINDINGS_CLOCK_IMX94_H */
> 
> 


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Re: [PATCH 1/5] dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR

[Krzysztof Kozlowski]

On 01/07/2025 09:04, Peng Fan wrote:
> Add i.MX94 LVDS/DISPLAY CSR compatible string.
> 
> Add clock index for the two CSRs.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  .../devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml        |  2 ++
>  include/dt-bindings/clock/nxp,imx94-clock.h                 | 13 +++++++++++++
>  2 files changed, 15 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
> index d0291bfff23a27cb55683880fe3a1f8b3e2ada5a..4e20e8c8663b3b6665ff91ae63e1539aa8e9cc9b 100644
> --- a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
> +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
> @@ -19,6 +19,8 @@ properties:
>            - nxp,imx95-lvds-csr
>            - nxp,imx95-netcmix-blk-ctrl
>            - nxp,imx95-vpu-csr
> +          - nxp,imx94-display-csr
> +          - nxp,imx94-lvds-csr

Wrong order. You received that comment on your previous patches, no?

Best regards,
Krzysztof

RE: [PATCH 1/5] dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR

[Peng Fan]

> Subject: Re: [PATCH 1/5] dt-bindings: clock: Add support for i.MX94
> LVDS/DISPLAY CSR
> 
> On 01/07/2025 09:04, Peng Fan wrote:
> > Add i.MX94 LVDS/DISPLAY CSR compatible string.
> >
> > Add clock index for the two CSRs.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  .../devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml        |  2 ++
> >  include/dt-bindings/clock/nxp,imx94-clock.h                 | 13
> +++++++++++++
> >  2 files changed, 15 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-
> ctl.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-
> ctl.yaml
> > index
> d0291bfff23a27cb55683880fe3a1f8b3e2ada5a..4e20e8c8663b3b666
> 5ff91ae63e1539aa8e9cc9b 100644
> > --- a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-
> ctl.yaml
> > +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-
> ctl.yaml
> > @@ -19,6 +19,8 @@ properties:
> >            - nxp,imx95-lvds-csr
> >            - nxp,imx95-netcmix-blk-ctrl
> >            - nxp,imx95-vpu-csr
> > +          - nxp,imx94-display-csr
> > +          - nxp,imx94-lvds-csr
> 
> Wrong order. You received that comment on your previous patches, no?

Ah, alphabet order, I thought number does not matter.

Regards
Peng.

> 
> Best regards,
> Krzysztof

Re: [PATCH 1/5] dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR

[Krzysztof Kozlowski]

On 01/07/2025 15:04, Peng Fan wrote:
>>> @@ -19,6 +19,8 @@ properties:
>>>            - nxp,imx95-lvds-csr
>>>            - nxp,imx95-netcmix-blk-ctrl
>>>            - nxp,imx95-vpu-csr
>>> +          - nxp,imx94-display-csr
>>> +          - nxp,imx94-lvds-csr
>>
>> Wrong order. You received that comment on your previous patches, no?
> 
> Ah, alphabet order, I thought number does not matter.

The number is the only thing that matters here. Otherwise everyone would
add their stuff to the end...

Best regards,
Krzysztof

RE: [PATCH 1/5] dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR

[Peng Fan]

> Subject: Re: [PATCH 1/5] dt-bindings: clock: Add support for i.MX94
> LVDS/DISPLAY CSR
> 
> On 01/07/2025 15:04, Peng Fan wrote:
> >>> @@ -19,6 +19,8 @@ properties:
> >>>            - nxp,imx95-lvds-csr
> >>>            - nxp,imx95-netcmix-blk-ctrl
> >>>            - nxp,imx95-vpu-csr
> >>> +          - nxp,imx94-display-csr
> >>> +          - nxp,imx94-lvds-csr
> >>
> >> Wrong order. You received that comment on your previous patches,
> no?
> >
> > Ah, alphabet order, I thought number does not matter.
> 
> The number is the only thing that matters here. Otherwise everyone
> would add their stuff to the end...

My bad. I will move nxp,imx94-[xyz] to the top.

Thanks,
Peng.

> 
> Best regards,
> Krzysztof

[PATCH 2/5] clk: imx95-blk-ctl: Fix synchronous abort

[Peng Fan]

From: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>

When enabling runtime PM for clock suppliers that also belong to a power
domain, the following crash is thrown:

---
Internal error: synchronous external abort: 0000000096000010 [#1] PREEMPT SMP
Workqueue: events_unbound deferred_probe_work_func
pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : clk_mux_get_parent+0x60/0x90
lr : clk_core_reparent_orphans_nolock+0x58/0xd8
Call trace:
 clk_mux_get_parent+0x60/0x90
 clk_core_reparent_orphans_nolock+0x58/0xd8
 of_clk_add_hw_provider.part.0+0x90/0x100
 of_clk_add_hw_provider+0x1c/0x38
 imx95_bc_probe+0x2e0/0x3f0
 platform_probe+0x70/0xd8

Enabling runtime PM without explicitly resuming the device caused
the power domain cut off after clk_register() is called. As a result,
a crash happens when the clock hardware provider is added and attempts
to access the BLK_CTL register

Fix this by using devm_pm_runtime_enable() instead of pm_runtime_enable()
and getting rid of the pm_runtime_disable() in the cleanup path.

Fixes: 5224b189462f ("clk: imx: add i.MX95 BLK CTL clk driver")
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx95-blk-ctl.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
index cc2ee2be18195f0e05e911bcb26e284b1a894244..86bdcd21753102b7d160288e7b69bf73da5a5706 100644
--- a/drivers/clk/imx/clk-imx95-blk-ctl.c
+++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
@@ -342,8 +342,10 @@ static int imx95_bc_probe(struct platform_device *pdev)
 	if (!clk_hw_data)
 		return -ENOMEM;
 
-	if (bc_data->rpm_enabled)
-		pm_runtime_enable(&pdev->dev);
+	if (bc_data->rpm_enabled) {
+		devm_pm_runtime_enable(&pdev->dev);
+		pm_runtime_resume_and_get(&pdev->dev);
+	}
 
 	clk_hw_data->num = bc_data->num_clks;
 	hws = clk_hw_data->hws;
@@ -383,8 +385,10 @@ static int imx95_bc_probe(struct platform_device *pdev)
 		goto cleanup;
 	}
 
-	if (pm_runtime_enabled(bc->dev))
+	if (pm_runtime_enabled(bc->dev)) {
+		pm_runtime_put_sync(&pdev->dev);
 		clk_disable_unprepare(bc->clk_apb);
+	}
 
 	return 0;
 
@@ -395,9 +399,6 @@ static int imx95_bc_probe(struct platform_device *pdev)
 		clk_hw_unregister(hws[i]);
 	}
 
-	if (bc_data->rpm_enabled)
-		pm_runtime_disable(&pdev->dev);
-
 	return ret;
 }
 

-- 
2.37.1

[PATCH 3/5] clk: imx95-blk-ctl: Rename lvds and displaymix csr blk

[Peng Fan]

From: Sandor Yu <Sandor.yu@nxp.com>

Rename i.MX95 lvds and displaymix csr blk drvdata in order to add
support for i.MX943.

Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx95-blk-ctl.c | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
index 86bdcd21753102b7d160288e7b69bf73da5a5706..828ee0a81ff62c6e4f61eef350b9073f19f5351f 100644
--- a/drivers/clk/imx/clk-imx95-blk-ctl.c
+++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
@@ -156,7 +156,7 @@ static const struct imx95_blk_ctl_dev_data camblk_dev_data = {
 	.clk_reg_offset = 0,
 };
 
-static const struct imx95_blk_ctl_clk_dev_data lvds_clk_dev_data[] = {
+static const struct imx95_blk_ctl_clk_dev_data imx95_lvds_clk_dev_data[] = {
 	[IMX95_CLK_DISPMIX_LVDS_PHY_DIV] = {
 		.name = "ldb_phy_div",
 		.parent_names = (const char *[]){ "ldbpll", },
@@ -213,21 +213,21 @@ static const struct imx95_blk_ctl_clk_dev_data lvds_clk_dev_data[] = {
 	},
 };
 
-static const struct imx95_blk_ctl_dev_data lvds_csr_dev_data = {
-	.num_clks = ARRAY_SIZE(lvds_clk_dev_data),
-	.clk_dev_data = lvds_clk_dev_data,
+static const struct imx95_blk_ctl_dev_data imx95_lvds_csr_dev_data = {
+	.num_clks = ARRAY_SIZE(imx95_lvds_clk_dev_data),
+	.clk_dev_data = imx95_lvds_clk_dev_data,
 	.clk_reg_offset = 0,
 };
 
-static const char * const disp_engine_parents[] = {
+static const char * const imx95_disp_engine_parents[] = {
 	"videopll1", "dsi_pll", "ldb_pll_div7"
 };
 
-static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data[] = {
+static const struct imx95_blk_ctl_clk_dev_data imx95_dispmix_csr_clk_dev_data[] = {
 	[IMX95_CLK_DISPMIX_ENG0_SEL] = {
 		.name = "disp_engine0_sel",
-		.parent_names = disp_engine_parents,
-		.num_parents = ARRAY_SIZE(disp_engine_parents),
+		.parent_names = imx95_disp_engine_parents,
+		.num_parents = ARRAY_SIZE(imx95_disp_engine_parents),
 		.reg = 0,
 		.bit_idx = 0,
 		.bit_width = 2,
@@ -236,8 +236,8 @@ static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data[] = {
 	},
 	[IMX95_CLK_DISPMIX_ENG1_SEL] = {
 		.name = "disp_engine1_sel",
-		.parent_names = disp_engine_parents,
-		.num_parents = ARRAY_SIZE(disp_engine_parents),
+		.parent_names = imx95_disp_engine_parents,
+		.num_parents = ARRAY_SIZE(imx95_disp_engine_parents),
 		.reg = 0,
 		.bit_idx = 2,
 		.bit_width = 2,
@@ -246,9 +246,9 @@ static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data[] = {
 	}
 };
 
-static const struct imx95_blk_ctl_dev_data dispmix_csr_dev_data = {
-	.num_clks = ARRAY_SIZE(dispmix_csr_clk_dev_data),
-	.clk_dev_data = dispmix_csr_clk_dev_data,
+static const struct imx95_blk_ctl_dev_data imx95_dispmix_csr_dev_data = {
+	.num_clks = ARRAY_SIZE(imx95_dispmix_csr_clk_dev_data),
+	.clk_dev_data = imx95_dispmix_csr_clk_dev_data,
 	.clk_reg_offset = 0,
 };
 
@@ -469,8 +469,8 @@ static const struct dev_pm_ops imx95_bc_pm_ops = {
 static const struct of_device_id imx95_bc_of_match[] = {
 	{ .compatible = "nxp,imx95-camera-csr", .data = &camblk_dev_data },
 	{ .compatible = "nxp,imx95-display-master-csr", },
-	{ .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },
-	{ .compatible = "nxp,imx95-display-csr", .data = &dispmix_csr_dev_data },
+	{ .compatible = "nxp,imx95-lvds-csr", .data = &imx95_lvds_csr_dev_data },
+	{ .compatible = "nxp,imx95-display-csr", .data = &imx95_dispmix_csr_dev_data },
 	{ .compatible = "nxp,imx95-hsio-blk-ctl", .data = &hsio_blk_ctl_dev_data },
 	{ .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
 	{ .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},

-- 
2.37.1

[PATCH 4/5] clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR

[Peng Fan]

i.MX94 BLK CTL LVDS CSR's LVDS_PHY_CLOCK_CONTRL register controls the clock
gating logic of LVDS units. Display CSR's DISPLAY_ENGINES_CLOCK_CONTROL
register controls the selection of the clock feeding the display engine.

Add clock gate support for the two CSRs.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-imx95-blk-ctl.c | 50 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 49 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
index 828ee0a81ff62c6e4f61eef350b9073f19f5351f..5fe582b0d4a9a197f2c1a49dc18f15ca83ccb4a4 100644
--- a/drivers/clk/imx/clk-imx95-blk-ctl.c
+++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
@@ -1,8 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  */
 
+#include <dt-bindings/clock/nxp,imx94-clock.h>
 #include <dt-bindings/clock/nxp,imx95-clock.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
@@ -300,6 +301,51 @@ static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
 	.clk_reg_offset = 0,
 };
 
+static const struct imx95_blk_ctl_clk_dev_data imx94_lvds_clk_dev_data[] = {
+	[IMX94_CLK_DISPMIX_LVDS_CLK_GATE] = {
+		.name = "lvds_clk_gate",
+		.parent_names = (const char *[]){ "ldbpll", },
+		.num_parents = 1,
+		.reg = 0,
+		.bit_idx = 1,
+		.bit_width = 1,
+		.type = CLK_GATE,
+		.flags = CLK_SET_RATE_PARENT,
+		.flags2 = CLK_GATE_SET_TO_DISABLE,
+	},
+};
+
+static const struct imx95_blk_ctl_dev_data imx94_lvds_csr_dev_data = {
+	.num_clks = ARRAY_SIZE(imx94_lvds_clk_dev_data),
+	.clk_dev_data = imx94_lvds_clk_dev_data,
+	.clk_reg_offset = 0,
+	.rpm_enabled = true,
+};
+
+static const char * const imx94_disp_engine_parents[] = {
+	"disppix", "ldb_pll_div7"
+};
+
+static const struct imx95_blk_ctl_clk_dev_data imx94_dispmix_csr_clk_dev_data[] = {
+	[IMX94_CLK_DISPMIX_CLK_SEL] = {
+		.name = "disp_clk_sel",
+		.parent_names = imx94_disp_engine_parents,
+		.num_parents = ARRAY_SIZE(imx94_disp_engine_parents),
+		.reg = 0,
+		.bit_idx = 1,
+		.bit_width = 1,
+		.type = CLK_MUX,
+		.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
+	},
+};
+
+static const struct imx95_blk_ctl_dev_data imx94_dispmix_csr_dev_data = {
+	.num_clks = ARRAY_SIZE(imx94_dispmix_csr_clk_dev_data),
+	.clk_dev_data = imx94_dispmix_csr_clk_dev_data,
+	.clk_reg_offset = 0,
+	.rpm_enabled = true,
+};
+
 static int imx95_bc_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -474,6 +520,8 @@ static const struct of_device_id imx95_bc_of_match[] = {
 	{ .compatible = "nxp,imx95-hsio-blk-ctl", .data = &hsio_blk_ctl_dev_data },
 	{ .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
 	{ .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},
+	{ .compatible = "nxp,imx94-lvds-csr", .data = &imx94_lvds_csr_dev_data },
+	{ .compatible = "nxp,imx94-display-csr", .data = &imx94_dispmix_csr_dev_data },
 	{ /* Sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, imx95_bc_of_match);

-- 
2.37.1

Re: [PATCH 4/5] clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR

[Alexander Stein]

Hi,

thanks for the patch.

Am Dienstag, 1. Juli 2025, 09:04:40 CEST schrieb Peng Fan:
> i.MX94 BLK CTL LVDS CSR's LVDS_PHY_CLOCK_CONTRL register controls the clock
> gating logic of LVDS units. Display CSR's DISPLAY_ENGINES_CLOCK_CONTROL
> register controls the selection of the clock feeding the display engine.
> 
> Add clock gate support for the two CSRs.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/imx/clk-imx95-blk-ctl.c | 50 ++++++++++++++++++++++++++++++++++++-
>  1 file changed, 49 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
> index 828ee0a81ff62c6e4f61eef350b9073f19f5351f..5fe582b0d4a9a197f2c1a49dc18f15ca83ccb4a4 100644
> --- a/drivers/clk/imx/clk-imx95-blk-ctl.c
> +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
> @@ -1,8 +1,9 @@
>  // SPDX-License-Identifier: GPL-2.0
>  /*
> - * Copyright 2024 NXP
> + * Copyright 2024-2025 NXP
>   */
>  
> +#include <dt-bindings/clock/nxp,imx94-clock.h>
>  #include <dt-bindings/clock/nxp,imx95-clock.h>
>  #include <linux/clk.h>
>  #include <linux/clk-provider.h>
> @@ -300,6 +301,51 @@ static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
>  	.clk_reg_offset = 0,
>  };
>  
> +static const struct imx95_blk_ctl_clk_dev_data imx94_lvds_clk_dev_data[] = {
> +	[IMX94_CLK_DISPMIX_LVDS_CLK_GATE] = {
> +		.name = "lvds_clk_gate",
> +		.parent_names = (const char *[]){ "ldbpll", },
> +		.num_parents = 1,
> +		.reg = 0,
> +		.bit_idx = 1,
> +		.bit_width = 1,
> +		.type = CLK_GATE,
> +		.flags = CLK_SET_RATE_PARENT,
> +		.flags2 = CLK_GATE_SET_TO_DISABLE,
> +	},
> +};
> +
> +static const struct imx95_blk_ctl_dev_data imx94_lvds_csr_dev_data = {
> +	.num_clks = ARRAY_SIZE(imx94_lvds_clk_dev_data),
> +	.clk_dev_data = imx94_lvds_clk_dev_data,
> +	.clk_reg_offset = 0,
> +	.rpm_enabled = true,
> +};
> +
> +static const char * const imx94_disp_engine_parents[] = {
> +	"disppix", "ldb_pll_div7"
> +};
> +
> +static const struct imx95_blk_ctl_clk_dev_data imx94_dispmix_csr_clk_dev_data[] = {
> +	[IMX94_CLK_DISPMIX_CLK_SEL] = {
> +		.name = "disp_clk_sel",
> +		.parent_names = imx94_disp_engine_parents,
> +		.num_parents = ARRAY_SIZE(imx94_disp_engine_parents),
> +		.reg = 0,
> +		.bit_idx = 1,
> +		.bit_width = 1,
> +		.type = CLK_MUX,
> +		.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static const struct imx95_blk_ctl_dev_data imx94_dispmix_csr_dev_data = {
> +	.num_clks = ARRAY_SIZE(imx94_dispmix_csr_clk_dev_data),
> +	.clk_dev_data = imx94_dispmix_csr_clk_dev_data,
> +	.clk_reg_offset = 0,
> +	.rpm_enabled = true,
> +};
> +
>  static int imx95_bc_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> @@ -474,6 +520,8 @@ static const struct of_device_id imx95_bc_of_match[] = {
>  	{ .compatible = "nxp,imx95-hsio-blk-ctl", .data = &hsio_blk_ctl_dev_data },
>  	{ .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
>  	{ .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},
> +	{ .compatible = "nxp,imx94-lvds-csr", .data = &imx94_lvds_csr_dev_data },
> +	{ .compatible = "nxp,imx94-display-csr", .data = &imx94_dispmix_csr_dev_data },

Similar to patch 1, sort them properly.

Best regards,
Alexander

>  	{ /* Sentinel */ },
>  };
>  MODULE_DEVICE_TABLE(of, imx95_bc_of_match);
> 
> 


-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/

Re: [PATCH 4/5] clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR

[Peng Fan]

On Tue, Jul 01, 2025 at 11:29:34AM +0200, Alexander Stein wrote:
>Hi,
>
>thanks for the patch.
>
>Am Dienstag, 1. Juli 2025, 09:04:40 CEST schrieb Peng Fan:
>> i.MX94 BLK CTL LVDS CSR's LVDS_PHY_CLOCK_CONTRL register controls the clock
>> gating logic of LVDS units. Display CSR's DISPLAY_ENGINES_CLOCK_CONTROL
>> register controls the selection of the clock feeding the display engine.
>> 
>> Add clock gate support for the two CSRs.
>> 
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> ---
>>  drivers/clk/imx/clk-imx95-blk-ctl.c | 50 ++++++++++++++++++++++++++++++++++++-
>>  1 file changed, 49 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
>> index 828ee0a81ff62c6e4f61eef350b9073f19f5351f..5fe582b0d4a9a197f2c1a49dc18f15ca83ccb4a4 100644
>> --- a/drivers/clk/imx/clk-imx95-blk-ctl.c
>> +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
>> @@ -1,8 +1,9 @@
>>  // SPDX-License-Identifier: GPL-2.0
>>  /*
>> - * Copyright 2024 NXP
>> + * Copyright 2024-2025 NXP
>>   */
>>  
>> +#include <dt-bindings/clock/nxp,imx94-clock.h>
>>  #include <dt-bindings/clock/nxp,imx95-clock.h>
>>  #include <linux/clk.h>
>>  #include <linux/clk-provider.h>
>> @@ -300,6 +301,51 @@ static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
>>  	.clk_reg_offset = 0,
>>  };
>>  
>> +static const struct imx95_blk_ctl_clk_dev_data imx94_lvds_clk_dev_data[] = {
>> +	[IMX94_CLK_DISPMIX_LVDS_CLK_GATE] = {
>> +		.name = "lvds_clk_gate",
>> +		.parent_names = (const char *[]){ "ldbpll", },
>> +		.num_parents = 1,
>> +		.reg = 0,
>> +		.bit_idx = 1,
>> +		.bit_width = 1,
>> +		.type = CLK_GATE,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +		.flags2 = CLK_GATE_SET_TO_DISABLE,
>> +	},
>> +};
>> +
>> +static const struct imx95_blk_ctl_dev_data imx94_lvds_csr_dev_data = {
>> +	.num_clks = ARRAY_SIZE(imx94_lvds_clk_dev_data),
>> +	.clk_dev_data = imx94_lvds_clk_dev_data,
>> +	.clk_reg_offset = 0,
>> +	.rpm_enabled = true,
>> +};
>> +
>> +static const char * const imx94_disp_engine_parents[] = {
>> +	"disppix", "ldb_pll_div7"
>> +};
>> +
>> +static const struct imx95_blk_ctl_clk_dev_data imx94_dispmix_csr_clk_dev_data[] = {
>> +	[IMX94_CLK_DISPMIX_CLK_SEL] = {
>> +		.name = "disp_clk_sel",
>> +		.parent_names = imx94_disp_engine_parents,
>> +		.num_parents = ARRAY_SIZE(imx94_disp_engine_parents),
>> +		.reg = 0,
>> +		.bit_idx = 1,
>> +		.bit_width = 1,
>> +		.type = CLK_MUX,
>> +		.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
>> +	},
>> +};
>> +
>> +static const struct imx95_blk_ctl_dev_data imx94_dispmix_csr_dev_data = {
>> +	.num_clks = ARRAY_SIZE(imx94_dispmix_csr_clk_dev_data),
>> +	.clk_dev_data = imx94_dispmix_csr_clk_dev_data,
>> +	.clk_reg_offset = 0,
>> +	.rpm_enabled = true,
>> +};
>> +
>>  static int imx95_bc_probe(struct platform_device *pdev)
>>  {
>>  	struct device *dev = &pdev->dev;
>> @@ -474,6 +520,8 @@ static const struct of_device_id imx95_bc_of_match[] = {
>>  	{ .compatible = "nxp,imx95-hsio-blk-ctl", .data = &hsio_blk_ctl_dev_data },
>>  	{ .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
>>  	{ .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},
>> +	{ .compatible = "nxp,imx94-lvds-csr", .data = &imx94_lvds_csr_dev_data },
>> +	{ .compatible = "nxp,imx94-display-csr", .data = &imx94_dispmix_csr_dev_data },
>
>Similar to patch 1, sort them properly.

ok, I will move imx94 to top. While at here, I will also sort
the imx95 following alphabet order.

Thanks,
Peng

>
>Best regards,
>Alexander
>
>>  	{ /* Sentinel */ },
>>  };
>>  MODULE_DEVICE_TABLE(of, imx95_bc_of_match);
>> 
>> 
>
>
>-- 
>TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
>Amtsgericht München, HRB 105018
>Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
>http://www.tq-group.com/
>
>

[PATCH 5/5] arm64: dts: imx943: Add LVDS/DISPLAY CSR nodes

[Peng Fan]

Add nodes for LVDS/DISPLAY CSR.

Add ldb_pll_div7 node which is used for clock source of DISPLAY CSR.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx943.dtsi | 34 +++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
index 45b8da758e87771c0775eb799ce2da3aac37c060..cf67dba21e4f6f27fff7e5d29744086e4ec9c021 100644
--- a/arch/arm64/boot/dts/freescale/imx943.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
@@ -3,6 +3,8 @@
  * Copyright 2025 NXP
  */
 
+#include <dt-bindings/clock/nxp,imx94-clock.h>
+
 #include "imx94.dtsi"
 
 / {
@@ -145,4 +147,36 @@ l3_cache: l3-cache {
 			cache-unified;
 		};
 	};
+
+	ldb_pll_pixel: ldb_pll_div7 {
+		compatible = "fixed-factor-clock";
+		#clock-cells = <0>;
+		clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
+		clock-div = <7>;
+		clock-mult = <1>;
+		clock-output-names = "ldb_pll_div7";
+	};
+
+	soc {
+		dispmix_csr: syscon@4b010000 {
+			compatible = "nxp,imx94-display-csr", "syscon";
+			reg = <0x0 0x4b010000 0x0 0x10000>;
+			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
+			#clock-cells = <1>;
+			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
+			assigned-clocks = <&scmi_clk IMX94_CLK_DISPAXI>,
+					  <&scmi_clk IMX94_CLK_DISPAPB>;
+			assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>,
+						 <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
+			assigned-clock-rates = <400000000>,  <133333333>;
+		};
+
+		lvds_csr: syscon@4b0c0000 {
+			compatible = "nxp,imx94-lvds-csr", "syscon";
+			reg = <0x0 0x4b0c0000 0x0 0x10000>;
+			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
+			#clock-cells = <1>;
+			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
+		};
+	};
 };

-- 
2.37.1

Re: [PATCH 5/5] arm64: dts: imx943: Add LVDS/DISPLAY CSR nodes

[Alexander Stein]

Hi,

Am Dienstag, 1. Juli 2025, 09:04:41 CEST schrieb Peng Fan:
> Add nodes for LVDS/DISPLAY CSR.
> 
> Add ldb_pll_div7 node which is used for clock source of DISPLAY CSR.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx943.dtsi | 34 +++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
> index 45b8da758e87771c0775eb799ce2da3aac37c060..cf67dba21e4f6f27fff7e5d29744086e4ec9c021 100644
> --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi

Why is this specific to imx943 but not imx94? What is the difference anyway?

Best regards
Alexander

> @@ -3,6 +3,8 @@
>   * Copyright 2025 NXP
>   */
>  
> +#include <dt-bindings/clock/nxp,imx94-clock.h>
> +
>  #include "imx94.dtsi"
>  
>  / {
> @@ -145,4 +147,36 @@ l3_cache: l3-cache {
>  			cache-unified;
>  		};
>  	};
> +
> +	ldb_pll_pixel: ldb_pll_div7 {
> +		compatible = "fixed-factor-clock";
> +		#clock-cells = <0>;
> +		clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
> +		clock-div = <7>;
> +		clock-mult = <1>;
> +		clock-output-names = "ldb_pll_div7";
> +	};
> +
> +	soc {
> +		dispmix_csr: syscon@4b010000 {
> +			compatible = "nxp,imx94-display-csr", "syscon";
> +			reg = <0x0 0x4b010000 0x0 0x10000>;
> +			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
> +			#clock-cells = <1>;
> +			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> +			assigned-clocks = <&scmi_clk IMX94_CLK_DISPAXI>,
> +					  <&scmi_clk IMX94_CLK_DISPAPB>;
> +			assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>,
> +						 <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
> +			assigned-clock-rates = <400000000>,  <133333333>;
> +		};
> +
> +		lvds_csr: syscon@4b0c0000 {
> +			compatible = "nxp,imx94-lvds-csr", "syscon";
> +			reg = <0x0 0x4b0c0000 0x0 0x10000>;
> +			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
> +			#clock-cells = <1>;
> +			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> +		};
> +	};
>  };
> 
> 


-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/

Re: [PATCH 5/5] arm64: dts: imx943: Add LVDS/DISPLAY CSR nodes

[Peng Fan]

On Tue, Jul 01, 2025 at 11:28:07AM +0200, Alexander Stein wrote:
>Hi,
>
>Am Dienstag, 1. Juli 2025, 09:04:41 CEST schrieb Peng Fan:
>> Add nodes for LVDS/DISPLAY CSR.
>> 
>> Add ldb_pll_div7 node which is used for clock source of DISPLAY CSR.
>> 
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> ---
>>  arch/arm64/boot/dts/freescale/imx943.dtsi | 34 +++++++++++++++++++++++++++++++
>>  1 file changed, 34 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
>> index 45b8da758e87771c0775eb799ce2da3aac37c060..cf67dba21e4f6f27fff7e5d29744086e4ec9c021 100644
>> --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
>
>Why is this specific to imx943 but not imx94? What is the difference anyway?

There is only i.MX943 in i.MX94 family as of now. Other future variants
may not support lvds or display. So Add the nodes in imx943.dtsi.

In future if the family has more and more members, and they
lvds and display supported, we could move back to imx94.dtsi.

No specific reason.

Thanks
Peng

>
>Best regards
>Alexander
>
>> @@ -3,6 +3,8 @@
>>   * Copyright 2025 NXP
>>   */
>>  
>> +#include <dt-bindings/clock/nxp,imx94-clock.h>
>> +
>>  #include "imx94.dtsi"
>>  
>>  / {
>> @@ -145,4 +147,36 @@ l3_cache: l3-cache {
>>  			cache-unified;
>>  		};
>>  	};
>> +
>> +	ldb_pll_pixel: ldb_pll_div7 {
>> +		compatible = "fixed-factor-clock";
>> +		#clock-cells = <0>;
>> +		clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
>> +		clock-div = <7>;
>> +		clock-mult = <1>;
>> +		clock-output-names = "ldb_pll_div7";
>> +	};
>> +
>> +	soc {
>> +		dispmix_csr: syscon@4b010000 {
>> +			compatible = "nxp,imx94-display-csr", "syscon";
>> +			reg = <0x0 0x4b010000 0x0 0x10000>;
>> +			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
>> +			#clock-cells = <1>;
>> +			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
>> +			assigned-clocks = <&scmi_clk IMX94_CLK_DISPAXI>,
>> +					  <&scmi_clk IMX94_CLK_DISPAPB>;
>> +			assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>,
>> +						 <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
>> +			assigned-clock-rates = <400000000>,  <133333333>;
>> +		};
>> +
>> +		lvds_csr: syscon@4b0c0000 {
>> +			compatible = "nxp,imx94-lvds-csr", "syscon";
>> +			reg = <0x0 0x4b0c0000 0x0 0x10000>;
>> +			clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
>> +			#clock-cells = <1>;
>> +			power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
>> +		};
>> +	};
>>  };
>> 
>> 
>
>
>-- 
>TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
>Amtsgericht München, HRB 105018
>Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
>http://www.tq-group.com/
>
>

Re: [PATCH 5/5] arm64: dts: imx943: Add LVDS/DISPLAY CSR nodes

[Krzysztof Kozlowski]

On 01/07/2025 09:04, Peng Fan wrote:
> Add nodes for LVDS/DISPLAY CSR.
> 
> Add ldb_pll_div7 node which is used for clock source of DISPLAY CSR.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx943.dtsi | 34 +++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
> index 45b8da758e87771c0775eb799ce2da3aac37c060..cf67dba21e4f6f27fff7e5d29744086e4ec9c021 100644
> --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
> @@ -3,6 +3,8 @@
>   * Copyright 2025 NXP
>   */
>  
> +#include <dt-bindings/clock/nxp,imx94-clock.h>
> +
>  #include "imx94.dtsi"
>  
>  / {
> @@ -145,4 +147,36 @@ l3_cache: l3-cache {
>  			cache-unified;
>  		};
>  	};
> +
> +	ldb_pll_pixel: ldb_pll_div7 {

Not a DTS coding style.

Please use name for all fixed clocks which matches current format
recommendation: 'clock-<freq>' (see also the pattern in the binding for
any other options).

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1

> +		compatible = "fixed-factor-clock";
> +		#clock-cells = <0>;
> +		clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
> +		clock-div = <7>;
> +		clock-mult = <1>;
> +		clock-output-names = "ldb_pll_div7";
> +	};



Best regards,
Krzysztof

Re: [PATCH 5/5] arm64: dts: imx943: Add LVDS/DISPLAY CSR nodes

[Peng Fan]

On Tue, Jul 01, 2025 at 01:38:11PM +0200, Krzysztof Kozlowski wrote:
>On 01/07/2025 09:04, Peng Fan wrote:
>> Add nodes for LVDS/DISPLAY CSR.
>> 
>> Add ldb_pll_div7 node which is used for clock source of DISPLAY CSR.
>> 
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> ---
>>  arch/arm64/boot/dts/freescale/imx943.dtsi | 34 +++++++++++++++++++++++++++++++
>>  1 file changed, 34 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
>> index 45b8da758e87771c0775eb799ce2da3aac37c060..cf67dba21e4f6f27fff7e5d29744086e4ec9c021 100644
>> --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
>> @@ -3,6 +3,8 @@
>>   * Copyright 2025 NXP
>>   */
>>  
>> +#include <dt-bindings/clock/nxp,imx94-clock.h>
>> +
>>  #include "imx94.dtsi"
>>  
>>  / {
>> @@ -145,4 +147,36 @@ l3_cache: l3-cache {
>>  			cache-unified;
>>  		};
>>  	};
>> +
>> +	ldb_pll_pixel: ldb_pll_div7 {
>
>Not a DTS coding style.
>
>Please use name for all fixed clocks which matches current format
>recommendation: 'clock-<freq>' (see also the pattern in the binding for
>any other options).

oops, I should use '-'. And the rate is not fixed, so not able to
use clock-<freq> for node name.

grep "fixed-factor-clock" ./Documentation/devicetree/bindings/ -rn, I
checked renesas,emev2-smu.yaml, fixed-factor-clock.yaml,
I could use "ldb-pll-div7-clk" in V2.

Thanks,
Peng

>
>https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1
>
>> +		compatible = "fixed-factor-clock";
>> +		#clock-cells = <0>;
>> +		clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
>> +		clock-div = <7>;
>> +		clock-mult = <1>;
>> +		clock-output-names = "ldb_pll_div7";
>> +	};
>
>
>
>Best regards,
>Krzysztof