From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 0/6] 32bit ARM branch predictor hardening
Date: Wed, 31 Jan 2018 19:07:48 +0000 [thread overview]
Message-ID: <61cd49b5-264c-d34b-872f-79c1eaa959ea@arm.com> (raw)
In-Reply-To: <c25089e9-540b-2b09-555c-a2c9d8850610@gmail.com>
On 31/01/18 18:53, Florian Fainelli wrote:
> On 01/31/2018 04:45 AM, Hanjun Guo wrote:
>> On 2018/1/29 22:58, Nishanth Menon wrote:
>>> On Mon, Jan 29, 2018 at 5:36 AM, Hanjun Guo <guohanjun@huawei.com> wrote:
>>> [...]
>>>
>>>> By the way, this patch set just enable branch predictor hardening
>>>> on arm32 unconditionally, but some of machines (such as wireless
>>>> network base station) will not be exposed to user to take advantage
>>>> of variant 2, and those machines will be pretty sensitive for
>>>> performance, so can we introduce Kconfig or boot option to disable
>>>> branch predictor hardening as an option?
>>>
>>> I am curious: Have you seen performance degradation with this series?
>>> If yes, is it possible to share the information?
>>
>> Sorry for the late reply, the performance data for context switch (CFS)
>> is about 6%~12% drop (A9 based machine) for the first around test, but
>> the data is not stable, I need to retest then I will update here.
>
> What tool did you use to measure this? On a Brahma-B15 platform clocked
> at 1.5Ghz, across kernels 4.1, 4.9 (4.15 in progress as we speak), I
> measured the following, with two memory configurations, one giving 256MB
> of usable memory, another giving 3GB of usable memory, results below are
> only the most extreme 256MB case. This is running 13 groups because the
> ASID space is 256bits so this should force at least two full ASID
> generation rollovers (assuming the logic is correct here).
>
> for i in $(seq 0 9)
> do
> hackbench 13 process 10000
> done
>
> Average values, in seconds:
>
> 1) 4.1.45, ACTLR[0] = 0, no spectre variant 2 patches: 114,2666
> 2) 4.1.45, ACTLR[0] = 1, no spectre variant 2 patches: 114,2952
> 3) 4.1.45, ACTLR[0] =1 , spectre variant 2 patches: 115,5853
>
> => 3) is a 1.15% degradation against 1)
>
> 4.9.51, ACTLR[0] = 0, no spectre variant 2 patches: 130,7676
> 4.9.51, ACTLR[0] = 1, no spectre variant 2 patches: 130,6848
> 4.9.51, ACTLR[0] =1 , spectre variant 2 patches: 132,4274
>
> => 3) is a 1.26% degradation against 1)
>
> The relative differences between 4.1 and 4.9 appear consistent (with 4.9
> being slower for a reason I ignore).
>
> Marc, are there any performance tests/results that you ran that you
> could share?
None. I usually don't run benchmarks, because they are not
representative of a real workload. I urge people to run their own real
workload, as it is very unlikely to have hackbench's profile...
Thanks,
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2018-01-31 19:07 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-25 15:21 [PATCH v3 0/6] 32bit ARM branch predictor hardening Marc Zyngier
2018-01-25 15:21 ` [PATCH v3 1/6] arm: Add BTB invalidation on switch_mm for Cortex-A9, A12 and A17 Marc Zyngier
2018-01-26 20:44 ` Florian Fainelli
2018-01-30 17:27 ` Marc Zyngier
2018-01-25 15:21 ` [PATCH v3 2/6] arm: Invalidate BTB on prefetch abort outside of user mapping on Cortex A8, A9, " Marc Zyngier
2018-01-31 2:13 ` Fabio Estevam
2018-01-25 15:21 ` [PATCH v3 3/6] arm: KVM: Invalidate BTB on guest exit for Cortex-A12/A17 Marc Zyngier
2018-01-26 9:23 ` Christoffer Dall
2018-01-26 17:12 ` Robin Murphy
2018-01-31 12:11 ` Marc Zyngier
2018-01-31 14:25 ` Robin Murphy
2018-01-25 15:21 ` [PATCH v3 4/6] arm: Add icache invalidation on switch_mm for Cortex-A15 Marc Zyngier
2018-01-26 9:14 ` Christoffer Dall
2018-01-26 9:30 ` Marc Zyngier
2018-01-26 16:20 ` Florian Fainelli
2018-01-26 16:33 ` Marc Zyngier
2018-01-26 17:20 ` Robin Murphy
2018-01-27 22:23 ` Florian Fainelli
2018-01-28 11:55 ` Marc Zyngier
2018-01-29 18:05 ` Florian Fainelli
2018-01-29 18:13 ` Marc Zyngier
2018-01-25 15:21 ` [PATCH v3 5/6] arm: Invalidate icache on prefetch abort outside of user mapping on Cortex-A15 Marc Zyngier
2018-01-25 15:21 ` [PATCH v3 6/6] arm: KVM: Invalidate icache on guest exit for Cortex-A15 Marc Zyngier
2018-01-26 9:30 ` [PATCH v3 0/6] 32bit ARM branch predictor hardening Christoffer Dall
2018-01-26 16:39 ` Andre Przywara
2018-01-29 11:36 ` Hanjun Guo
2018-01-29 14:58 ` Nishanth Menon
2018-01-31 12:45 ` Hanjun Guo
2018-01-31 18:53 ` Florian Fainelli
2018-01-31 19:07 ` Marc Zyngier [this message]
2018-01-31 19:54 ` André Przywara
2018-01-31 20:37 ` Florian Fainelli
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