From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 93FB8C27C77 for ; Wed, 12 Jun 2024 10:20:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:CC:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=JNs1l8+IwxXvd7kw039pXjFA0Ygz2v4ZLuzxy6QdndA=; b=aJMzHqDIbcO2nnLDtKm88wJ7Bp TVcFUF3ZkPHW9vlHVy0+xUEYG00JW+4FwCKIHcLA7MomOSGRxfVC239pbhzDNG5Bw3wxn3eq0gPsx i+wP/VeYeMokANmAFPQIWGt9lwb/+PxRtKu26S22SyR45ueKiSMymXaHYhdjGuFA+ZCbXDegw9uXl CmEgpGxUhJ0RZJRpR9ovin7yjXC8saTZz46xgGsJuz27IsV9NFzDOpIDB9XETivOKnP0PRqzUFkOn NDRR5GGqsMqZdVx632DdiKRXXVnj6B3Y3wuo9bfiwuj5RrRRIWb3gpc79UP0ncC0J/+3Ni5ACg2GA ZLgSUo1Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sHL5D-0000000CCTD-0gie; Wed, 12 Jun 2024 10:19:59 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sHL5A-0000000CCSE-07Cs for linux-arm-kernel@lists.infradead.org; Wed, 12 Jun 2024 10:19:57 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45CAJp7b015573; Wed, 12 Jun 2024 05:19:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718187591; bh=JNs1l8+IwxXvd7kw039pXjFA0Ygz2v4ZLuzxy6QdndA=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=h46WvgPOzbM7OPScfHJMCzIUTtka7PIJD94JNQUECFxsfCP3hb1CyYvdMjCERN1OZ ix+pFXgb1KX17tDRVM/ERvfJRIaDJV0jJHws1xRFUAYmfWiF+5z0xrjuNdK9mJou6j S8TDhZ2xCzXCMf5GjMbrup1UL6sPzY3sRj3if8cE= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45CAJpVj015825 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 12 Jun 2024 05:19:51 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 12 Jun 2024 05:19:51 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 12 Jun 2024 05:19:51 -0500 Received: from [172.24.227.94] (uda0132425.dhcp.ti.com [172.24.227.94]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45CAJlqU038726; Wed, 12 Jun 2024 05:19:48 -0500 Message-ID: <629a95ac-3f40-412f-b983-312f434bfb2f@ti.com> Date: Wed, 12 Jun 2024 15:49:46 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/4] Add overlays to disable optional hardware in k3-am6xx-phycore-som boards To: Nathan Morrisson , , , , , CC: , , , , References: <20240528225137.3629698-1-nmorrisson@phytec.com> <4ac40139-eda0-4f6a-8bbe-99110605f91e@ti.com> <5a773641-73a6-416e-8c52-eccc136f11ef@phytec.com> From: Vignesh Raghavendra Content-Language: en-US In-Reply-To: <5a773641-73a6-416e-8c52-eccc136f11ef@phytec.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240612_031956_192857_5C8A9DA1 X-CRM114-Status: GOOD ( 21.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 05/06/24 04:45, Nathan Morrisson wrote: > Hi Vignesh, > > On 6/3/24 10:41 AM, Vignesh Raghavendra wrote: >> Hi Nathan, >> >> On 29/05/24 04:21, Nathan Morrisson wrote: >>> Add three overlays to disable the eth phy, rtc, and spi nor. These >>> overlays will be used to disable device tree nodes for components >>> that are optionally not populated. >>> >>> v2: >>>    - Add build time tests in makefile >>> >>> Nathan Morrisson (4): >>>    arm64: dts: ti: k3-am64-phycore-som: Add serial_flash label >> >>>    arm64: dts: ti: k3-am6xx-phycore-som: Add overlay to disable eth phy >>>    arm64: dts: ti: k3-am6xx-phycore-som: Add overlay to disable rtc >>>    arm64: dts: ti: k3-am6xx-phycore-som: Add overlay to disabl spi nor >>> >>>   arch/arm64/boot/dts/ti/Makefile               | 17 +++++++++++++++++ >>>   .../boot/dts/ti/k3-am64-phycore-som.dtsi      |  2 +- >>>   .../ti/k3-am6xx-phycore-disable-eth-phy.dtso  | 19 +++++++++++++++++++ >>>   .../dts/ti/k3-am6xx-phycore-disable-rtc.dtso  | 15 +++++++++++++++ >>>   .../ti/k3-am6xx-phycore-disable-spi-nor.dtso  | 15 +++++++++++++++ >>>   5 files changed, 67 insertions(+), 1 deletion(-) >>>   create mode 100644 >>> arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-eth-phy.dtso >>>   create mode 100644 >>> arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-rtc.dtso >>>   create mode 100644 >>> arch/arm64/boot/dts/ti/k3-am6xx-phycore-disable-spi-nor.dtso >>> >> I am not sure if this a common practice to have overlays to disable >> missing components (at least I dont see such dtso in kernel). I would >> like to see an what DT maintainers feel as such dtsos can explode in >> numbers. >> >> Is this something that U-Boot can detect and fix up for the Linux DT? > We have an EEPROM on our board with information on what is populated on > that particular board. We will apply these overlays based on that EEPROM > data. Typical usage of overlay is to keep the minimum in baseboard and enable optional components in the overlay. But it would also depend on whats information is present in the EEPROM. Could you provide bit more color on whats in EEPROM and how each overlay would be applied? Please add the same to commit message and respin. >> >> Unpopulated SPI flash and RTC should ideally not be an issue as drivers >> would gracefully fail albeit with some sort of error msg. >> Not so sure about Eth PHYs though. >> >> Also, Are these dtso's mutually exclusive? ie can SoM have SPI flash but >> not RTC, have RTC and SPI Flash but no ETH PHY? > > They are not mutually exclusive, you could have any combination of > overlays applied. > > > Regards, > > Nathan > >> -- Regards Vignesh