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Mon, 03 Feb 2025 08:31:12 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 9AEAD40051; Mon, 3 Feb 2025 08:29:51 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B7C9E28E495; Mon, 3 Feb 2025 08:29:42 +0100 (CET) Received: from [10.48.87.62] (10.48.87.62) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 3 Feb 2025 08:29:41 +0100 Message-ID: <62f719a0-357f-406a-92e1-3e8ab4ef9600@foss.st.com> Date: Mon, 3 Feb 2025 08:29:41 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/9] memory: Add STM32 Octo Memory Manager driver To: Philipp Zabel , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexandre Torgue , Maxime Coquelin , Greg Kroah-Hartman , Arnd Bergmann , Catalin Marinas , Will Deacon CC: , , , , , References: <20250128081731.2284457-1-patrice.chotard@foss.st.com> <20250128081731.2284457-5-patrice.chotard@foss.st.com> <3d6cfb082ef8ee0fc66c885a84f64ae0a851234b.camel@pengutronix.de> Content-Language: en-US From: Patrice CHOTARD In-Reply-To: <3d6cfb082ef8ee0fc66c885a84f64ae0a851234b.camel@pengutronix.de> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.48.87.62] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-03_03,2025-01-31_02,2024-11-22_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250202_233133_588317_96F4455E X-CRM114-Status: GOOD ( 19.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 1/28/25 10:17, Philipp Zabel wrote: > On Di, 2025-01-28 at 09:17 +0100, patrice.chotard@foss.st.com wrote: >> From: Patrice Chotard >> >> Octo Memory Manager driver (OMM) manages: >> - the muxing between 2 OSPI busses and 2 output ports. >> There are 4 possible muxing configurations: >> - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 >> output is on port 2 >> - OSPI1 and OSPI2 are multiplexed over the same output port 1 >> - swapped mode (no multiplexing), OSPI1 output is on port 2, >> OSPI2 output is on port 1 >> - OSPI1 and OSPI2 are multiplexed over the same output port 2 >> - the split of the memory area shared between the 2 OSPI instances. >> - chip select selection override. >> - the time between 2 transactions in multiplexed mode. >> - check firewall access. >> >> Signed-off-by: Patrice Chotard >> Signed-off-by: Christophe Kerello >> --- >> drivers/memory/Kconfig | 17 ++ >> drivers/memory/Makefile | 1 + >> drivers/memory/stm32_omm.c | 509 +++++++++++++++++++++++++++++++++++++ >> 3 files changed, 527 insertions(+) >> create mode 100644 drivers/memory/stm32_omm.c >> > [...] >> diff --git a/drivers/memory/stm32_omm.c b/drivers/memory/stm32_omm.c >> new file mode 100644 >> index 000000000000..6f20fe0183ec >> --- /dev/null >> +++ b/drivers/memory/stm32_omm.c >> @@ -0,0 +1,509 @@ > [...] >> +static int stm32_omm_configure(struct device *dev) >> +{ >> + struct stm32_omm *omm = dev_get_drvdata(dev); >> + struct reset_control *rstc; >> + unsigned long clk_rate, clk_rate_max = 0; >> + int ret; >> + u8 i; >> + u32 mux = 0; >> + u32 cssel_ovr = 0; >> + u32 req2ack = 0; >> + >> + omm->clk = devm_clk_get(dev, NULL); >> + if (IS_ERR(omm->clk)) { >> + dev_err(dev, "Failed to get OMM clock (%ld)\n", >> + PTR_ERR(omm->clk)); >> + >> + return PTR_ERR(omm->clk); >> + } >> + >> + ret = pm_runtime_resume_and_get(dev); >> + if (ret < 0) >> + return ret; >> + >> + /* parse children's clock */ >> + for (i = 0; i < omm->nb_child; i++) { >> + clk_rate = clk_get_rate(omm->child[i].clk); >> + if (!clk_rate) { >> + dev_err(dev, "Invalid clock rate\n"); >> + goto err_clk_disable; >> + } >> + >> + if (clk_rate > clk_rate_max) >> + clk_rate_max = clk_rate; >> + } >> + >> + rstc = devm_reset_control_get_optional(dev, NULL); > > Please use devm_reset_control_get_optional_exclusive() directly. ok Thanks Patrice > > regards > Philipp