* [PATCH 00/11] Adding Support for SPEAr Platform under ARM architecture @ 2010-03-03 5:07 Viresh KUMAR 2010-03-03 5:07 ` [PATCH 01/11] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file Viresh KUMAR 2010-03-07 15:54 ` [PATCH 00/11] Adding Support for SPEAr Platform under ARM architecture viresh kumar 0 siblings, 2 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-03 5:07 UTC (permalink / raw) To: linux-arm-kernel Following set of patches are for adding ST Microelctronics SPEAr Platform under ARM architecture in Linux. Hierarchy in SPEAr is as follows: SPEAr (Platform) - SPEAr3XX (3XX SOC series, based on ARM9) - SPEAr300 (SOC) - SPEAr300_EVB (Evaluation Board) - SPEAr310 (SOC) - SPEAr310_EVB (Evaluation Board) - SPEAr320 (SOC) - SPEAr320_EVB (Evaluation Board) - SPEAr6XX (6XX SOC series, based on ARM9) - SPEAr600 (SOC) - SPEAr600_EVB (Evaluation Board) - SPEAr13XX (13XX SOC series, based on ARM CORTEXA9) - SPEAr1300 (SOC) Current patch will add support for SPEAr3XX and SPEAr6XX family. SPEAr13XX is under development phase. Viresh Kumar (11): ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file ST SPEAr: Added basic header files for SPEAr3xx machine family ST SPEAr: Added basic header files for SPEAr6xx machine family ST SPEAr: Added basic header files for SPEAr platform ST SPEAr: Added clock framework for SPEAr platform and machines ST SPEAr: Added source files for SPEAr platform ST SPEAr: Added source files for SPEAr3xx machine family ST SPEAr: Added source files for SPEAr6xx machine family ST SPEAr: Added support for SPEAr platform and machines in arch/arm/ ST SPEAr: Added default configuration files for SPEAr machines ST SPEAr: Updated Maintainers and added Documentation/arm/SPEAr Documentation/arm/SPEAr/overview.txt | 60 + MAINTAINERS | 27 + arch/arm/Kconfig | 11 + arch/arm/Makefile | 5 + arch/arm/configs/spear300_defconfig | 1409 ++++++++++++++++++++ arch/arm/configs/spear310_defconfig | 1410 ++++++++++++++++++++ arch/arm/configs/spear320_defconfig | 1410 ++++++++++++++++++++ arch/arm/configs/spear600_defconfig | 1451 +++++++++++++++++++++ arch/arm/mach-spear3xx/Kconfig | 33 + arch/arm/mach-spear3xx/Kconfig300 | 17 + arch/arm/mach-spear3xx/Kconfig310 | 17 + arch/arm/mach-spear3xx/Kconfig320 | 17 + arch/arm/mach-spear3xx/Makefile | 26 + arch/arm/mach-spear3xx/Makefile.boot | 3 + arch/arm/mach-spear3xx/clock.c | 525 ++++++++ arch/arm/mach-spear3xx/include/mach/clkdev.h | 19 + arch/arm/mach-spear3xx/include/mach/debug-macro.S | 38 + arch/arm/mach-spear3xx/include/mach/dma.h | 18 + arch/arm/mach-spear3xx/include/mach/entry-macro.S | 46 + arch/arm/mach-spear3xx/include/mach/generic.h | 39 + arch/arm/mach-spear3xx/include/mach/hardware.h | 20 + arch/arm/mach-spear3xx/include/mach/io.h | 22 + arch/arm/mach-spear3xx/include/mach/irqs.h | 57 + arch/arm/mach-spear3xx/include/mach/memory.h | 20 + arch/arm/mach-spear3xx/include/mach/misc_regs.h | 163 +++ arch/arm/mach-spear3xx/include/mach/spear.h | 136 ++ arch/arm/mach-spear3xx/include/mach/spear300.h | 64 + arch/arm/mach-spear3xx/include/mach/spear310.h | 43 + arch/arm/mach-spear3xx/include/mach/spear320.h | 69 + arch/arm/mach-spear3xx/include/mach/system.h | 41 + arch/arm/mach-spear3xx/include/mach/timex.h | 19 + arch/arm/mach-spear3xx/include/mach/uncompress.h | 43 + arch/arm/mach-spear3xx/include/mach/vmalloc.h | 22 + arch/arm/mach-spear3xx/spear300.c | 23 + arch/arm/mach-spear3xx/spear300_evb.c | 47 + arch/arm/mach-spear3xx/spear310.c | 23 + arch/arm/mach-spear3xx/spear310_evb.c | 47 + arch/arm/mach-spear3xx/spear320.c | 23 + arch/arm/mach-spear3xx/spear320_evb.c | 47 + arch/arm/mach-spear3xx/spear3xx.c | 118 ++ arch/arm/mach-spear6xx/Kconfig | 20 + arch/arm/mach-spear6xx/Kconfig600 | 17 + arch/arm/mach-spear6xx/Makefile | 12 + arch/arm/mach-spear6xx/Makefile.boot | 3 + arch/arm/mach-spear6xx/clock.c | 656 ++++++++++ arch/arm/mach-spear6xx/include/mach/clkdev.h | 19 + arch/arm/mach-spear6xx/include/mach/debug-macro.S | 38 + arch/arm/mach-spear6xx/include/mach/dma.h | 17 + arch/arm/mach-spear6xx/include/mach/entry-macro.S | 55 + arch/arm/mach-spear6xx/include/mach/generic.h | 37 + arch/arm/mach-spear6xx/include/mach/hardware.h | 21 + arch/arm/mach-spear6xx/include/mach/io.h | 23 + arch/arm/mach-spear6xx/include/mach/irqs.h | 92 ++ arch/arm/mach-spear6xx/include/mach/memory.h | 20 + arch/arm/mach-spear6xx/include/mach/misc_regs.h | 173 +++ arch/arm/mach-spear6xx/include/mach/spear.h | 165 +++ arch/arm/mach-spear6xx/include/mach/spear600.h | 21 + arch/arm/mach-spear6xx/include/mach/system.h | 41 + arch/arm/mach-spear6xx/include/mach/timex.h | 19 + arch/arm/mach-spear6xx/include/mach/uncompress.h | 43 + arch/arm/mach-spear6xx/include/mach/vmalloc.h | 22 + arch/arm/mach-spear6xx/spear600.c | 23 + arch/arm/mach-spear6xx/spear600_evb.c | 48 + arch/arm/mach-spear6xx/spear6xx.c | 149 +++ arch/arm/plat-spear/Kconfig | 31 + arch/arm/plat-spear/Makefile | 6 + arch/arm/plat-spear/clock.c | 433 ++++++ arch/arm/plat-spear/gpt.c | 537 ++++++++ arch/arm/plat-spear/include/plat/clkdev.h | 20 + arch/arm/plat-spear/include/plat/clock.h | 130 ++ arch/arm/plat-spear/include/plat/gpt.h | 108 ++ arch/arm/plat-spear/time.c | 197 +++ include/linux/sysctl_sp810.h | 59 + 73 files changed, 10883 insertions(+), 0 deletions(-) create mode 100644 Documentation/arm/SPEAr/overview.txt create mode 100644 arch/arm/configs/spear300_defconfig create mode 100644 arch/arm/configs/spear310_defconfig create mode 100644 arch/arm/configs/spear320_defconfig create mode 100644 arch/arm/configs/spear600_defconfig create mode 100644 arch/arm/mach-spear3xx/Kconfig create mode 100644 arch/arm/mach-spear3xx/Kconfig300 create mode 100644 arch/arm/mach-spear3xx/Kconfig310 create mode 100644 arch/arm/mach-spear3xx/Kconfig320 create mode 100644 arch/arm/mach-spear3xx/Makefile create mode 100644 arch/arm/mach-spear3xx/Makefile.boot create mode 100755 arch/arm/mach-spear3xx/clock.c create mode 100644 arch/arm/mach-spear3xx/include/mach/clkdev.h create mode 100644 arch/arm/mach-spear3xx/include/mach/debug-macro.S create mode 100644 arch/arm/mach-spear3xx/include/mach/dma.h create mode 100644 arch/arm/mach-spear3xx/include/mach/entry-macro.S create mode 100644 arch/arm/mach-spear3xx/include/mach/generic.h create mode 100644 arch/arm/mach-spear3xx/include/mach/hardware.h create mode 100644 arch/arm/mach-spear3xx/include/mach/io.h create mode 100644 arch/arm/mach-spear3xx/include/mach/irqs.h create mode 100644 arch/arm/mach-spear3xx/include/mach/memory.h create mode 100755 arch/arm/mach-spear3xx/include/mach/misc_regs.h create mode 100644 arch/arm/mach-spear3xx/include/mach/spear.h create mode 100644 arch/arm/mach-spear3xx/include/mach/spear300.h create mode 100644 arch/arm/mach-spear3xx/include/mach/spear310.h create mode 100644 arch/arm/mach-spear3xx/include/mach/spear320.h create mode 100644 arch/arm/mach-spear3xx/include/mach/system.h create mode 100644 arch/arm/mach-spear3xx/include/mach/timex.h create mode 100644 arch/arm/mach-spear3xx/include/mach/uncompress.h create mode 100644 arch/arm/mach-spear3xx/include/mach/vmalloc.h create mode 100644 arch/arm/mach-spear3xx/spear300.c create mode 100644 arch/arm/mach-spear3xx/spear300_evb.c create mode 100644 arch/arm/mach-spear3xx/spear310.c create mode 100644 arch/arm/mach-spear3xx/spear310_evb.c create mode 100644 arch/arm/mach-spear3xx/spear320.c create mode 100644 arch/arm/mach-spear3xx/spear320_evb.c create mode 100644 arch/arm/mach-spear3xx/spear3xx.c create mode 100644 arch/arm/mach-spear6xx/Kconfig create mode 100644 arch/arm/mach-spear6xx/Kconfig600 create mode 100644 arch/arm/mach-spear6xx/Makefile create mode 100644 arch/arm/mach-spear6xx/Makefile.boot create mode 100755 arch/arm/mach-spear6xx/clock.c create mode 100644 arch/arm/mach-spear6xx/include/mach/clkdev.h create mode 100644 arch/arm/mach-spear6xx/include/mach/debug-macro.S create mode 100644 arch/arm/mach-spear6xx/include/mach/dma.h create mode 100644 arch/arm/mach-spear6xx/include/mach/entry-macro.S create mode 100644 arch/arm/mach-spear6xx/include/mach/generic.h create mode 100644 arch/arm/mach-spear6xx/include/mach/hardware.h create mode 100644 arch/arm/mach-spear6xx/include/mach/io.h create mode 100755 arch/arm/mach-spear6xx/include/mach/irqs.h create mode 100644 arch/arm/mach-spear6xx/include/mach/memory.h create mode 100755 arch/arm/mach-spear6xx/include/mach/misc_regs.h create mode 100644 arch/arm/mach-spear6xx/include/mach/spear.h create mode 100644 arch/arm/mach-spear6xx/include/mach/spear600.h create mode 100644 arch/arm/mach-spear6xx/include/mach/system.h create mode 100644 arch/arm/mach-spear6xx/include/mach/timex.h create mode 100644 arch/arm/mach-spear6xx/include/mach/uncompress.h create mode 100644 arch/arm/mach-spear6xx/include/mach/vmalloc.h create mode 100644 arch/arm/mach-spear6xx/spear600.c create mode 100644 arch/arm/mach-spear6xx/spear600_evb.c create mode 100644 arch/arm/mach-spear6xx/spear6xx.c create mode 100644 arch/arm/plat-spear/Kconfig create mode 100644 arch/arm/plat-spear/Makefile create mode 100755 arch/arm/plat-spear/clock.c create mode 100644 arch/arm/plat-spear/gpt.c create mode 100644 arch/arm/plat-spear/include/plat/clkdev.h create mode 100755 arch/arm/plat-spear/include/plat/clock.h create mode 100644 arch/arm/plat-spear/include/plat/gpt.h create mode 100644 arch/arm/plat-spear/time.c create mode 100644 include/linux/sysctl_sp810.h ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 01/11] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file 2010-03-03 5:07 [PATCH 00/11] Adding Support for SPEAr Platform under ARM architecture Viresh KUMAR @ 2010-03-03 5:07 ` Viresh KUMAR 2010-03-03 5:07 ` [PATCH 02/11] ST SPEAr: Added basic header files for SPEAr3xx machine family Viresh KUMAR 2010-03-09 20:14 ` [PATCH 01/11] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file Linus Walleij 2010-03-07 15:54 ` [PATCH 00/11] Adding Support for SPEAr Platform under ARM architecture viresh kumar 1 sibling, 2 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-03 5:07 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Viresh Kumar <viresh.kumar@st.com> --- include/linux/sysctl_sp810.h | 59 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 59 insertions(+), 0 deletions(-) create mode 100644 include/linux/sysctl_sp810.h diff --git a/include/linux/sysctl_sp810.h b/include/linux/sysctl_sp810.h new file mode 100644 index 0000000..9b841b9 --- /dev/null +++ b/include/linux/sysctl_sp810.h @@ -0,0 +1,59 @@ +/* + * linux/sysctl_sp810.h + * + * ARM PrimeXsys System Controller SP810 header file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef SYSCTL_SP810_H +#define SYSCTL_SP810_H + +#include <linux/io.h> + +/* sysctl registers offset */ +#define SCCTRL 0x000 +#define SCSYSSTAT 0x004 +#define SCIMCTRL 0x008 +#define SCIMSTAT 0x00C +#define SCXTALCTRL 0x010 +#define SCPLLCTRL 0x014 +#define SCPLLFCTRL 0x018 +#define SCPERCTRL0 0x01C +#define SCPERCTRL1 0x020 +#define SCPEREN 0x024 +#define SCPERDIS 0x028 +#define SCPERCLKEN 0x02C +#define SCPERSTAT 0x030 +#define SCSYSID0 0xEE0 +#define SCSYSID1 0xEE4 +#define SCSYSID2 0xEE8 +#define SCSYSID3 0xEEC +#define SCITCR 0xF00 +#define SCITIR0 0xF04 +#define SCITIR1 0xF08 +#define SCITOR 0xF0C +#define SCCNTCTRL 0xF10 +#define SCCNTDATA 0xF14 +#define SCCNTSTEP 0xF18 +#define SCPERIPHID0 0xFE0 +#define SCPERIPHID1 0xFE4 +#define SCPERIPHID2 0xFE8 +#define SCPERIPHID3 0xFEC +#define SCPCELLID0 0xFF0 +#define SCPCELLID1 0xFF4 +#define SCPCELLID2 0xFF8 +#define SCPCELLID3 0xFFC + +static inline void sysctl_soft_reset(void __iomem *base) +{ + /* writing any value to SCSYSSTAT reg will reset system */ + writel(0, base + SCSYSSTAT); +} + +#endif /* SYSCTL_SP810_H */ -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH 02/11] ST SPEAr: Added basic header files for SPEAr3xx machine family 2010-03-03 5:07 ` [PATCH 01/11] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file Viresh KUMAR @ 2010-03-03 5:07 ` Viresh KUMAR 2010-03-03 5:07 ` [PATCH 03/11] ST SPEAr: Added basic header files for SPEAr6xx " Viresh KUMAR ` (2 more replies) 2010-03-09 20:14 ` [PATCH 01/11] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file Linus Walleij 1 sibling, 3 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-03 5:07 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Viresh Kumar <viresh.kumar@st.com> --- arch/arm/mach-spear3xx/include/mach/debug-macro.S | 38 +++++ arch/arm/mach-spear3xx/include/mach/dma.h | 18 +++ arch/arm/mach-spear3xx/include/mach/entry-macro.S | 46 ++++++ arch/arm/mach-spear3xx/include/mach/generic.h | 39 +++++ arch/arm/mach-spear3xx/include/mach/hardware.h | 20 +++ arch/arm/mach-spear3xx/include/mach/io.h | 22 +++ arch/arm/mach-spear3xx/include/mach/irqs.h | 57 +++++++ arch/arm/mach-spear3xx/include/mach/memory.h | 20 +++ arch/arm/mach-spear3xx/include/mach/misc_regs.h | 163 +++++++++++++++++++++ arch/arm/mach-spear3xx/include/mach/spear.h | 136 +++++++++++++++++ arch/arm/mach-spear3xx/include/mach/spear300.h | 64 ++++++++ arch/arm/mach-spear3xx/include/mach/spear310.h | 43 ++++++ arch/arm/mach-spear3xx/include/mach/spear320.h | 69 +++++++++ arch/arm/mach-spear3xx/include/mach/system.h | 41 +++++ arch/arm/mach-spear3xx/include/mach/timex.h | 19 +++ arch/arm/mach-spear3xx/include/mach/uncompress.h | 43 ++++++ arch/arm/mach-spear3xx/include/mach/vmalloc.h | 22 +++ 17 files changed, 860 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-spear3xx/include/mach/debug-macro.S create mode 100644 arch/arm/mach-spear3xx/include/mach/dma.h create mode 100644 arch/arm/mach-spear3xx/include/mach/entry-macro.S create mode 100644 arch/arm/mach-spear3xx/include/mach/generic.h create mode 100644 arch/arm/mach-spear3xx/include/mach/hardware.h create mode 100644 arch/arm/mach-spear3xx/include/mach/io.h create mode 100644 arch/arm/mach-spear3xx/include/mach/irqs.h create mode 100644 arch/arm/mach-spear3xx/include/mach/memory.h create mode 100755 arch/arm/mach-spear3xx/include/mach/misc_regs.h create mode 100644 arch/arm/mach-spear3xx/include/mach/spear.h create mode 100644 arch/arm/mach-spear3xx/include/mach/spear300.h create mode 100644 arch/arm/mach-spear3xx/include/mach/spear310.h create mode 100644 arch/arm/mach-spear3xx/include/mach/spear320.h create mode 100644 arch/arm/mach-spear3xx/include/mach/system.h create mode 100644 arch/arm/mach-spear3xx/include/mach/timex.h create mode 100644 arch/arm/mach-spear3xx/include/mach/uncompress.h create mode 100644 arch/arm/mach-spear3xx/include/mach/vmalloc.h diff --git a/arch/arm/mach-spear3xx/include/mach/debug-macro.S b/arch/arm/mach-spear3xx/include/mach/debug-macro.S new file mode 100644 index 0000000..2f6c5bd --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/debug-macro.S @@ -0,0 +1,38 @@ +/* + * arch/arm/mach-spear3xx/include/mach/debug-macro.S + * + * Debugging macro include header spear3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/amba/serial.h> +#include <mach/spear.h> + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, =SPEAR3XX_ICM1_UART_BASE @ Physical base + movne \rx, =VA_SPEAR3XX_ICM1_UART_BASE @ Virtual base + .endm + + .macro senduart, rd, rx + strb \rd, [\rx, #UART01x_DR] @ ASC_TX_BUFFER + .endm + + .macro waituart, rd, rx +1001: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER + tst \rd, #UART01x_FR_TXFF @ TX_FULL + bne 1001b + .endm + + .macro busyuart, rd, rx +1002: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER + tst \rd, #UART011_FR_TXFE @ TX_EMPTY + beq 1002b + .endm diff --git a/arch/arm/mach-spear3xx/include/mach/dma.h b/arch/arm/mach-spear3xx/include/mach/dma.h new file mode 100644 index 0000000..9b93bc6 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/dma.h @@ -0,0 +1,18 @@ +/* + * arch/arm/mach-spear3xx/include/mach/dma.h + * + * Generic DMA support for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#endif /* __ASM_ARCH_DMA_H */ + diff --git a/arch/arm/mach-spear3xx/include/mach/entry-macro.S b/arch/arm/mach-spear3xx/include/mach/entry-macro.S new file mode 100644 index 0000000..947625d --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/entry-macro.S @@ -0,0 +1,46 @@ +/* + * arch/arm/mach-spear3xx/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <mach/hardware.h> +#include <mach/spear.h> +#include <asm/hardware/vic.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =VA_SPEAR3XX_ML1_VIC_BASE + ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status + teq \irqstat, #0 + beq 1001f @ this will set/reset + @ zero register + /* + * Following code will find bit position of least significang + * bit set in irqstat, using following equation + * least significant bit set in n = (n & ~(n-1)) + */ + sub \tmp, \irqstat, #1 @ tmp = irqstat - 1 + mvn \tmp, \tmp @ tmp = ~tmp + and \irqstat, \irqstat, \tmp @ irqstat &= tmp + /* Now, irqstat is = bit no. of 1st bit set in vic irq status */ + clz \tmp, \irqstat @ tmp = leading zeros + rsb \irqnr, \tmp, #0x1F @ irqnr = 32 - tmp - 1 + +1001: /* EQ will be set if no irqs pending */ + .endm diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h new file mode 100644 index 0000000..a659e60 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/generic.h @@ -0,0 +1,39 @@ +/* + * arch/arm/mach-spear3xx/generic.h + * + * SPEAr3XX machine family generic header file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_GENERIC_H +#define __ASM_ARCH_GENERIC_H + +#include <asm/mach/time.h> +#include <asm/mach/map.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/amba/bus.h> + +/* Add spear3xx family device structure declarations here */ +extern struct amba_device uart_device; +extern struct sys_timer spear_sys_timer; + +/* Add spear300 machine device structure declarations here */ + +/* Add spear3xx family function declarations here */ +void __init spear3xx_map_io(void); +void __init spear3xx_init_irq(void); +void __init spear3xx_init(void); +void __init spear300_init(void); +void __init spear310_init(void); +void __init spear320_init(void); +void __init spear_gpt_init(void); +void __init clk_init(void); + +#endif /* __ASM_ARCH_GENERIC_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h new file mode 100644 index 0000000..e92267a --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/hardware.h @@ -0,0 +1,20 @@ +/* + * arch/arm/mach-spear3xx/include/mach/hardware.h + * + * Hardware definitions for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_HARDWARE_H +#define __ASM_MACH_HARDWARE_H + +/* Vitual to physical translation of statically mapped space */ +#define IO_ADDRESS(x) (x | 0xF0000000) + +#endif /* __ASM_MACH_HARDWARE_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/io.h b/arch/arm/mach-spear3xx/include/mach/io.h new file mode 100644 index 0000000..235df7a --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/io.h @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-spear3xx/include/mach/io.h + * + * IO definitions for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_IO_H +#define __ASM_MACH_IO_H + +#define IO_SPACE_LIMIT 0xFFFFFFFF + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif /* __ASM_MACH_IO_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h new file mode 100644 index 0000000..7e451e8 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/irqs.h @@ -0,0 +1,57 @@ +/* + * arch/arm/mach-spear3xx/include/mach/irqs.h + * + * IRQ helper macros for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_IRQS_H +#define __ASM_MACH_IRQS_H + +/* IRQ definitions */ +#define IRQ_HW_ACCEL_MOD_0 0 +#define IRQ_INTRCOMM_RAS_ARM 1 +#define IRQ_CPU_GPT1_1 2 +#define IRQ_CPU_GPT1_2 3 +#define IRQ_BASIC_GPT1_1 4 +#define IRQ_BASIC_GPT1_2 5 +#define IRQ_BASIC_GPT2_1 6 +#define IRQ_BASIC_GPT2_2 7 +#define IRQ_BASIC_DMA 8 +#define IRQ_BASIC_SMI 9 +#define IRQ_BASIC_RTC 10 +#define IRQ_BASIC_GPIO 11 +#define IRQ_BASIC_WDT 12 +#define IRQ_DDR_CONTROLLER 13 +#define IRQ_SYS_ERROR 14 +#define IRQ_WAKEUP_RCV 15 +#define IRQ_JPEG 16 +#define IRQ_IRDA 17 +#define IRQ_ADC 18 +#define IRQ_UART 19 +#define IRQ_SSP 20 +#define IRQ_I2C 21 +#define IRQ_MAC_1 22 +#define IRQ_MAC_2 23 +#define IRQ_USB_DEV 24 +#define IRQ_USB_H_OHCI_0 25 +#define IRQ_USB_H_EHCI_0 26 +#define IRQ_USB_H_EHCI_1 IRQ_USB_H_EHCI_0 +#define IRQ_USB_H_OHCI_1 27 +#define IRQ_GEN_RAS_1 28 +#define IRQ_GEN_RAS_2 29 +#define IRQ_GEN_RAS_3 30 +#define IRQ_HW_ACCEL_MOD_1 31 +#define IRQ_VIC_END 32 + +#define SPEAR_GPIO_INT_BASE IRQ_VIC_END +#define VIRTUAL_IRQS 0 +#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) + +#endif /* __ASM_MACH_IRQS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/memory.h b/arch/arm/mach-spear3xx/include/mach/memory.h new file mode 100644 index 0000000..1090287 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/memory.h @@ -0,0 +1,20 @@ +/* + * arch/arm/mach-spear3xx/include/mach/memory.h + * + * Memory map for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_MEMORY_H +#define __ASM_MACH_MEMORY_H + +/* Physical DRAM offset */ +#define PHYS_OFFSET UL(0x00000000) + +#endif /* __ASM_MACH_MEMORY_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h new file mode 100755 index 0000000..d83dae9 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h @@ -0,0 +1,163 @@ +/* + * arch/arm/mach-spear3xx/include/mach/misc_regs.h + * + * Miscellaneous registers definitions for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_MISC_REGS_H +#define __ASM_MACH_MISC_REGS_H + +#include <mach/spear.h> + +#define MISC_BASE VA_SPEAR3XX_ICM3_MISC_REG_BASE + +#define SOC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x000)) +#define DIAG_CFG_CTR ((unsigned int *)(MISC_BASE + 0x004)) +#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x008)) +#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x00C)) +#define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x010)) +#define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x014)) +/* PLL_CTR register masks */ +#define PLL_ENABLE 2 +#define PLL_MODE_SHIFT 4 +#define PLL_MODE_MASK 0x3 +#define PLL_MODE_NORMAL 0 +#define PLL_MODE_FRACTION 1 +#define PLL_MODE_DITH_DSB 2 +#define PLL_MODE_DITH_SSB 3 + +#define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x018)) +/* PLL FRQ register masks */ +#define PLL_DIV_N_SHIFT 0 +#define PLL_DIV_N_MASK 0xFF +#define PLL_DIV_P_SHIFT 8 +#define PLL_DIV_P_MASK 0x7 +#define PLL_NORM_FDBK_M_SHIFT 24 +#define PLL_NORM_FDBK_M_MASK 0xFF +#define PLL_DITH_FDBK_M_SHIFT 16 +#define PLL_DITH_FDBK_M_MASK 0xFFFF + +#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C)) +#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020)) +#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024)) +/* CORE CLK CFG register masks */ +#define PLL_HCLK_RATIO_SHIFT 10 +#define PLL_HCLK_RATIO_MASK 0x3 +#define HCLK_PCLK_RATIO_SHIFT 8 +#define HCLK_PCLK_RATIO_MASK 0x3 + +#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x028)) +/* PERIP_CLK_CFG register masks */ +#define UART_CLK_SHIFT 4 +#define UART_CLK_MASK 0x1 +#define FIRDA_CLK_SHIFT 5 +#define FIRDA_CLK_MASK 0x3 +#define GPT0_CLK_SHIFT 8 +#define GPT1_CLK_SHIFT 11 +#define GPT2_CLK_SHIFT 12 +#define GPT_CLK_MASK 0x1 +#define AUX_CLK_PLL3_MASK 0 +#define AUX_CLK_PLL1_MASK 1 + +#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C)) +/* PERIP1_CLK_ENB register masks */ +#define UART_CLK_ENB 3 +#define SSP_CLK_ENB 5 +#define I2C_CLK_ENB 7 +#define JPEG_CLK_ENB 8 +#define FIRDA_CLK_ENB 10 +#define GPT1_CLK_ENB 11 +#define GPT2_CLK_ENB 12 +#define ADC_CLK_ENB 15 +#define RTC_CLK_ENB 17 +#define GPIO_CLK_ENB 18 +#define DMA_CLK_ENB 19 +#define SMI_CLK_ENB 21 +#define GMAC_CLK_ENB 23 +#define USBD_CLK_ENB 24 +#define USBH_CLK_ENB 25 +#define C3_CLK_ENB 31 + +#define SOC_CORE_ID ((unsigned int *)(MISC_BASE + 0x030)) +#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x034)) +#define PERIP1_SOF_RST ((unsigned int *)(MISC_BASE + 0x038)) +/* PERIP1_SOF_RST register masks */ +#define JPEG_SOF_RST 8 + +#define SOC_USER_ID ((unsigned int *)(MISC_BASE + 0x03C)) +#define RAS_SOF_RST ((unsigned int *)(MISC_BASE + 0x040)) +#define PRSC1_CLK_CFG ((unsigned int *)(MISC_BASE + 0x044)) +#define PRSC2_CLK_CFG ((unsigned int *)(MISC_BASE + 0x048)) +#define PRSC3_CLK_CFG ((unsigned int *)(MISC_BASE + 0x04C)) +/* gpt synthesizer register masks */ +#define GPT_MSCALE_SHIFT 0 +#define GPT_MSCALE_MASK 0xFFF +#define GPT_NSCALE_SHIFT 12 +#define GPT_NSCALE_MASK 0xF + +#define AMEM_CLK_CFG ((unsigned int *)(MISC_BASE + 0x050)) +#define EXPI_CLK_CFG ((unsigned int *)(MISC_BASE + 0x054)) +#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x05C)) +#define FIRDA_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x060)) +#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x064)) +#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x068)) +#define RAS1_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x06C)) +#define RAS2_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x070)) +#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074)) +#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078)) +/* aux clk synthesiser register masks for irda to ras4 */ +#define AUX_EQ_SEL_SHIFT 30 +#define AUX_EQ_SEL_MASK 1 +#define AUX_EQ1_SEL 0 +#define AUX_EQ2_SEL 1 +#define AUX_XSCALE_SHIFT 16 +#define AUX_XSCALE_MASK 0xFFF +#define AUX_YSCALE_SHIFT 0 +#define AUX_YSCALE_MASK 0xFFF + +#define ICM1_ARB_CFG ((unsigned int *)(MISC_BASE + 0x07C)) +#define ICM2_ARB_CFG ((unsigned int *)(MISC_BASE + 0x080)) +#define ICM3_ARB_CFG ((unsigned int *)(MISC_BASE + 0x084)) +#define ICM4_ARB_CFG ((unsigned int *)(MISC_BASE + 0x088)) +#define ICM5_ARB_CFG ((unsigned int *)(MISC_BASE + 0x08C)) +#define ICM6_ARB_CFG ((unsigned int *)(MISC_BASE + 0x090)) +#define ICM7_ARB_CFG ((unsigned int *)(MISC_BASE + 0x094)) +#define ICM8_ARB_CFG ((unsigned int *)(MISC_BASE + 0x098)) +#define ICM9_ARB_CFG ((unsigned int *)(MISC_BASE + 0x09C)) +#define DMA_CHN_CFG ((unsigned int *)(MISC_BASE + 0x0A0)) +#define USB2_PHY_CFG ((unsigned int *)(MISC_BASE + 0x0A4)) +#define GMAC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0A8)) +#define EXPI_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0AC)) +#define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C0)) +#define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C4)) +#define PRC3_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C8)) +#define PRC4_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0CC)) +#define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D0)) +#define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D4)) +#define PRC3_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D8)) +#define PRC4_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0DC)) +#define PWRDOWN_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0E0)) +#define COMPSSTL_1V8_CFG ((unsigned int *)(MISC_BASE + 0x0E4)) +#define COMPSSTL_2V5_CFG ((unsigned int *)(MISC_BASE + 0x0E8)) +#define COMPCOR_3V3_CFG ((unsigned int *)(MISC_BASE + 0x0EC)) +#define SSTLPAD_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F0)) +#define BIST1_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F4)) +#define BIST2_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F8)) +#define BIST3_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0FC)) +#define BIST4_CFG_CTR ((unsigned int *)(MISC_BASE + 0x100)) +#define BIST5_CFG_CTR ((unsigned int *)(MISC_BASE + 0x104)) +#define BIST1_STS_RES ((unsigned int *)(MISC_BASE + 0x108)) +#define BIST2_STS_RES ((unsigned int *)(MISC_BASE + 0x10C)) +#define BIST3_STS_RES ((unsigned int *)(MISC_BASE + 0x110)) +#define BIST4_STS_RES ((unsigned int *)(MISC_BASE + 0x114)) +#define BIST5_STS_RES ((unsigned int *)(MISC_BASE + 0x118)) +#define SYSERR_CFG_CTR ((unsigned int *)(MISC_BASE + 0x11C)) + +#endif /* __ASM_MACH_MISC_REGS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h new file mode 100644 index 0000000..ade272a --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/spear.h @@ -0,0 +1,136 @@ +/* + * arch/arm/mach-spear3xx/include/mach/spear.h + * + * SPEAr3xx Machine family specific definition + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_SPEAR3XX_H +#define __ASM_MACH_SPEAR3XX_H + +#include <mach/hardware.h> +#include <mach/spear300.h> +#include <mach/spear310.h> +#include <mach/spear320.h> + +#define SPEAR3XX_ICM9_BASE 0xC0000000 +#define SPEAR3XX_ICM9_SIZE 0x10000000 + +/* ICM1 - Low speed connection */ +#define SPEAR3XX_ICM1_2_BASE 0xD0000000 +#define SPEAR3XX_ICM1_2_SIZE 0x10000000 + +#define SPEAR3XX_ICM1_UART_BASE 0xD0000000 +#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE) +#define SPEAR3XX_ICM1_UART_SIZE 0x00080000 + +#define SPEAR3XX_ICM1_ADC_BASE 0xD0080000 +#define SPEAR3XX_ICM1_ADC_SIZE 0x00080000 + +#define SPEAR3XX_ICM1_SSP_BASE 0xD0100000 +#define SPEAR3XX_ICM1_SSP_SIZE 0x00080000 + +#define SPEAR3XX_ICM1_I2C_BASE 0xD0180000 +#define SPEAR3XX_ICM1_I2C_SIZE 0x00080000 + +#define SPEAR3XX_ICM1_JPEG_BASE 0xD0800000 +#define SPEAR3XX_ICM1_JPEG_SIZE 0x00800000 + +#define SPEAR3XX_ICM1_IRDA_BASE 0xD1000000 +#define SPEAR3XX_ICM1_IRDA_SIZE 0x00080000 + +#define SPEAR3XX_ICM1_SRAM_BASE 0xD2800000 +#define SPEAR3XX_ICM1_SRAM_SIZE 0x05800000 + +/* ICM2 - Application Subsystem */ +#define SPEAR3XX_ICM2_HWACCEL0_BASE 0xD8800000 +#define SPEAR3XX_ICM2_HWACCEL0_SIZE 0x00800000 + +#define SPEAR3XX_ICM2_HWACCEL1_BASE 0xD9000000 +#define SPEAR3XX_ICM2_HWACCEL1_SIZE 0x00800000 + +/* ICM4 - High Speed Connection */ +#define SPEAR3XX_ICM4_BASE 0xE0000000 +#define SPEAR3XX_ICM4_SIZE 0x08000000 + +#define SPEAR3XX_ICM4_MII_BASE 0xE0800000 +#define SPEAR3XX_ICM4_MII_SIZE 0x00800000 + +#define SPEAR3XX_ICM4_USBD_FIFO_BASE 0xE1000000 +#define SPEAR3XX_ICM4_USBD_FIFO_SIZE 0x00100000 + +#define SPEAR3XX_ICM4_USBD_CSR_BASE 0xE1100000 +#define SPEAR3XX_ICM4_USBD_CSR_SIZE 0x00100000 + +#define SPEAR3XX_ICM4_USBD_PLDT_BASE 0xE1200000 +#define SPEAR3XX_ICM4_USBD_PLDT_SIZE 0x00100000 + +#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE 0xE1800000 +#define SPEAR3XX_ICM4_USB_EHCI0_1_SIZE 0x00100000 + +#define SPEAR3XX_ICM4_USB_OHCI0_BASE 0xE1900000 +#define SPEAR3XX_ICM4_USB_OHCI0_SIZE 0x00100000 + +#define SPEAR3XX_ICM4_USB_OHCI1_BASE 0xE2100000 +#define SPEAR3XX_ICM4_USB_OHCI1_SIZE 0x00100000 + +#define SPEAR3XX_ICM4_USB_ARB_BASE 0xE2800000 +#define SPEAR3XX_ICM4_USB_ARB_SIZE 0x00010000 + +/* ML1 - Multi Layer CPU Subsystem */ +#define SPEAR3XX_ICM3_ML1_2_BASE 0xF0000000 +#define SPEAR3XX_ICM3_ML1_2_SIZE 0x0F000000 + +#define SPEAR3XX_ML1_SDRAM_BASE 0x00000000 +#define SPEAR3XX_ML1_SDRAM_SIZE 0x40000000 + +#define SPEAR3XX_ML1_TMR_BASE 0xF0000000 +#define SPEAR3XX_ML1_TMR_SIZE 0x00100000 + +#define SPEAR3XX_ML1_VIC_BASE 0xF1100000 +#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE) +#define SPEAR3XX_ML1_VIC_SIZE 0x00100000 + +/* ICM3 - Basic Subsystem */ +#define SPEAR3XX_ICM3_SMEM_BASE 0xF8000000 +#define SPEAR3XX_ICM3_SMEM_SIZE 0x04000000 + +#define SPEAR3XX_ICM3_SMI_CTRL_BASE 0xFC000000 +#define SPEAR3XX_ICM3_SMI_CTRL_SIZE 0x00200000 + +#define SPEAR3XX_ICM3_DMA_BASE 0xFC400000 +#define SPEAR3XX_ICM3_DMA_SIZE 0x00200000 + +#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE 0xFC600000 +#define SPEAR3XX_ICM3_SDRAM_CTRL_SIZE 0x00200000 + +#define SPEAR3XX_ICM3_TMR0_BASE 0xFC800000 +#define SPEAR3XX_ICM3_TMR0_SIZE 0x00080000 + +#define SPEAR3XX_ICM3_WDT_BASE 0xFC880000 +#define SPEAR3XX_ICM3_WDT_SIZE 0x00080000 + +#define SPEAR3XX_ICM3_RTC_BASE 0xFC900000 +#define SPEAR3XX_ICM3_RTC_SIZE 0x00080000 + +#define SPEAR3XX_ICM3_GPIO_BASE 0xFC980000 +#define SPEAR3XX_ICM3_GPIO_SIZE 0x00080000 + +#define SPEAR3XX_ICM3_SYS_CTRL_BASE 0xFCA00000 +#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE) +#define SPEAR3XX_ICM3_SYS_CTRL_SIZE 0x00080000 + +#define SPEAR3XX_ICM3_MISC_REG_BASE 0xFCA80000 +#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE) +#define SPEAR3XX_ICM3_MISC_REG_SIZE 0x00080000 + +#define SPEAR3XX_ICM3_TMR1_BASE 0xFCB00000 +#define SPEAR3XX_ICM3_TMR1_SIZE 0x00080000 + +#endif /* __ASM_MACH_SPEAR3XX_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h new file mode 100644 index 0000000..0cd95be --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/spear300.h @@ -0,0 +1,64 @@ +/* + * arch/arm/mach-spear3xx/include/mach/spear300.h + * + * SPEAr300 Machine specific definition + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifdef CONFIG_MACH_SPEAR300 + +#ifndef __ASM_MACH_SPEAR300_H +#define __ASM_MACH_SPEAR300_H + +/* Base address of various IPs */ +#define SPEAR300_TELECOM_BASE 0x50000000 +#define SPEAR300_TELECOM_SIZE 0x10000000 + +#define SPEAR300_CLCD_BASE 0x60000000 +#define SPEAR300_CLCD_SIZE 0x10000000 + +#define SPEAR300_SDIO_BASE 0x70000000 +#define SPEAR300_SDIO_SIZE 0x10000000 + +#define SPEAR300_NAND_0_BASE 0x80000000 +#define SPEAR300_NAND_0_SIZE 0x04000000 + +#define SPEAR300_NAND_1_BASE 0x84000000 +#define SPEAR300_NAND_1_SIZE 0x04000000 + +#define SPEAR300_NAND_2_BASE 0x88000000 +#define SPEAR300_NAND_2_SIZE 0x04000000 + +#define SPEAR300_NAND_3_BASE 0x8c000000 +#define SPEAR300_NAND_3_SIZE 0x04000000 + +#define SPEAR300_NOR_0_BASE 0x90000000 +#define SPEAR300_NOR_0_SIZE 0x01000000 + +#define SPEAR300_NOR_1_BASE 0x91000000 +#define SPEAR300_NOR_1_SIZE 0x01000000 + +#define SPEAR300_NOR_2_BASE 0x92000000 +#define SPEAR300_NOR_2_SIZE 0x01000000 + +#define SPEAR300_NOR_3_BASE 0x93000000 +#define SPEAR300_NOR_3_SIZE 0x01000000 + +#define SPEAR300_FSMC_BASE 0x94000000 +#define SPEAR300_FSMC_SIZE 0x05000000 + +#define SPEAR300_KEYBOARD_BASE 0xA0000000 +#define SPEAR300_KEYBOARD_SIZE 0x09000000 + +#define SPEAR300_GPIO_BASE 0xA9000000 +#define SPEAR300_GPIO_SIZE 0x07000000 + +#endif /* __ASM_MACH_SPEAR300_H */ + +#endif /* CONFIG_MACH_SPEAR300 */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h new file mode 100644 index 0000000..5c79131 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/spear310.h @@ -0,0 +1,43 @@ +/* + * arch/arm/mach-spear3xx/include/mach/spear310.h + * + * SPEAr310 Machine specific definition + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifdef CONFIG_MACH_SPEAR310 + +#ifndef __ASM_MACH_SPEAR310_H +#define __ASM_MACH_SPEAR310_H + +#define SPEAR310_NAND_BASE 0x40000000 +#define SPEAR310_NAND_SIZE 0x04000000 + +#define SPEAR310_FSMC_BASE 0x44000000 +#define SPEAR310_FSMC_SIZE 0x01000000 + +#define SPEAR310_UART0_BASE 0xB2000000 +#define SPEAR310_UART1_BASE 0xB2080000 +#define SPEAR310_UART2_BASE 0xB2100000 +#define SPEAR310_UART3_BASE 0xB2180000 +#define SPEAR310_UART4_BASE 0xB2200000 +#define SPEAR310_UART_SIZE 0x00080000 + +#define SPEAR310_HDLC_BASE 0xB2800000 +#define SPEAR310_HDLC_SIZE 0x00800000 + +#define SPEAR310_RS485_0_BASE 0xB3000000 +#define SPEAR310_RS485_0_SIZE 0x00800000 + +#define SPEAR310_RS485_1_BASE 0xB3800000 +#define SPEAR310_RS485_1_SIZE 0x00800000 + +#endif /* __ASM_MACH_SPEAR310_H */ + +#endif /* CONFIG_MACH_SPEAR310 */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h new file mode 100644 index 0000000..ab6a85a --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/spear320.h @@ -0,0 +1,69 @@ +/* + * arch/arm/mach-spear3xx/include/mach/spear320.h + * + * SPEAr320 Machine specific definition + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifdef CONFIG_MACH_SPEAR320 + +#ifndef __ASM_MACH_SPEAR320_H +#define __ASM_MACH_SPEAR320_H + +#define SPEAR320_EMI_CTRL_BASE 0x40000000 +#define SPEAR320_EMI_CTRL_SIZE 0x08000000 + +#define SPEAR320_FSMC_BASE 0x4C000000 +#define SPEAR320_FSMC_SIZE 0x01000000 + +#define SPEAR320_I2S_BASE 0x60000000 +#define SPEAR320_I2S_SIZE 0x10000000 + +#define SPEAR320_SDIO_BASE 0x70000000 +#define SPEAR320_SDIO_SIZE 0x10000000 + +#define SPEAR320_CLCD_BASE 0x90000000 +#define SPEAR320_CLCD_SIZE 0x10000000 + +#define SPEAR320_PAR_PORT_BASE 0xA0000000 +#define SPEAR320_PAR_PORT_SIZE 0x01000000 + +#define SPEAR320_CAN0_BASE 0xA1000000 +#define SPEAR320_CAN0_SIZE 0x01000000 + +#define SPEAR320_CAN1_BASE 0xA2000000 +#define SPEAR320_CAN1_SIZE 0x01000000 + +#define SPEAR320_UART0_BASE 0xA3000000 +#define SPEAR320_UART0_SIZE 0x01000000 + +#define SPEAR320_UART1_BASE 0xA4000000 +#define SPEAR320_UART1_SIZE 0x01000000 + +#define SPEAR320_SSP0_BASE 0xA5000000 +#define SPEAR320_SSP0_SIZE 0x01000000 + +#define SPEAR320_SSP1_BASE 0xA6000000 +#define SPEAR320_SSP1_SIZE 0x01000000 + +#define SPEAR320_I2C_BASE 0xA7000000 +#define SPEAR320_I2C_SIZE 0x01000000 + +#define SPEAR320_PWM_BASE 0xA8000000 +#define SPEAR320_PWM_SIZE 0x01000000 + +#define SPEAR320_SMII0_BASE 0xAA000000 +#define SPEAR320_SMII0_SIZE 0x01000000 + +#define SPEAR320_SMII1_BASE 0xAB000000 +#define SPEAR320_SMII1_SIZE 0x01000000 + +#endif /* __ASM_MACH_SPEAR320_H */ + +#endif /* CONFIG_MACH_SPEAR320 */ diff --git a/arch/arm/mach-spear3xx/include/mach/system.h b/arch/arm/mach-spear3xx/include/mach/system.h new file mode 100644 index 0000000..b7bc53f --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/system.h @@ -0,0 +1,41 @@ +/* + * arch/arm/mach-spear3xx/include/mach/system.h + * + * SPEAr3xx Machine family specific architecture functions + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_SYSTEM_H +#define __ASM_MACH_SYSTEM_H + +#include <linux/io.h> +#include <linux/sysctl_sp810.h> +#include <mach/spear.h> + +static inline void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks + */ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + if (mode == 's') { + /* software reset, Jump into ROM at address 0 */ + cpu_reset(0); + } else { + /* hardware reset, Use on-chip reset capability */ + sysctl_soft_reset(SPEAR3XX_ICM3_SYS_CTRL_BASE); + } +} + +#endif /* __ASM_MACH_SYSTEM_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/timex.h b/arch/arm/mach-spear3xx/include/mach/timex.h new file mode 100644 index 0000000..29708db --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/timex.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear3xx/include/mach/timex.h + * + * SPEAr3XX machine family specific timex definitions + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_TIMEX_H +#define __ASM_MACH_TIMEX_H + +#define CLOCK_TICK_RATE 48000000 + +#endif /* __ASM_MACH_TIMEX_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/uncompress.h b/arch/arm/mach-spear3xx/include/mach/uncompress.h new file mode 100644 index 0000000..08ec3b1 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/uncompress.h @@ -0,0 +1,43 @@ +/* + * arch/arm/mach-spear3xx/include/mach/uncompress.h + * + * Serial port stubs for kernel decompress status messages + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/io.h> +#include <linux/amba/serial.h> +#include <mach/spear.h> + +#ifndef __ASM_MACH_UNCOMPRESS_H +#define __ASM_MACH_UNCOMPRESS_H +/* + * This does not append a newline + */ +static inline void putc(int c) +{ + void __iomem *base = (void __iomem *)SPEAR3XX_ICM1_UART_BASE; + + while (readl(base + UART01x_FR) & UART01x_FR_TXFF) + barrier(); + + writel(c, base + UART01x_DR); +} + +static inline void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() + +#endif /* __ASM_MACH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/vmalloc.h b/arch/arm/mach-spear3xx/include/mach/vmalloc.h new file mode 100644 index 0000000..4f236f3 --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/vmalloc.h @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-spear3xx/include/mach/vmalloc.h + * + * Defining Vmalloc area for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_VMALLOC_H +#define __ASM_MACH_VMALLOC_H + +#include <mach/memory.h> + +#define VMALLOC_SIZE (0x30000000) +#define VMALLOC_END (PAGE_OFFSET + VMALLOC_SIZE) + +#endif /* __ASM_MACH_VMALLOC_H */ -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH 03/11] ST SPEAr: Added basic header files for SPEAr6xx machine family 2010-03-03 5:07 ` [PATCH 02/11] ST SPEAr: Added basic header files for SPEAr3xx machine family Viresh KUMAR @ 2010-03-03 5:07 ` Viresh KUMAR 2010-03-03 5:07 ` [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform Viresh KUMAR 2010-03-09 20:42 ` [PATCH 02/11] ST SPEAr: Added basic header files for SPEAr3xx machine family Linus Walleij 2010-03-11 10:33 ` Russell King - ARM Linux 2 siblings, 1 reply; 51+ messages in thread From: Viresh KUMAR @ 2010-03-03 5:07 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Viresh Kumar <viresh.kumar@st.com> --- arch/arm/mach-spear6xx/include/mach/debug-macro.S | 38 +++++ arch/arm/mach-spear6xx/include/mach/dma.h | 17 ++ arch/arm/mach-spear6xx/include/mach/entry-macro.S | 55 +++++++ arch/arm/mach-spear6xx/include/mach/generic.h | 37 +++++ arch/arm/mach-spear6xx/include/mach/hardware.h | 21 +++ arch/arm/mach-spear6xx/include/mach/io.h | 23 +++ arch/arm/mach-spear6xx/include/mach/irqs.h | 92 +++++++++++ arch/arm/mach-spear6xx/include/mach/memory.h | 20 +++ arch/arm/mach-spear6xx/include/mach/misc_regs.h | 173 +++++++++++++++++++++ arch/arm/mach-spear6xx/include/mach/spear.h | 165 ++++++++++++++++++++ arch/arm/mach-spear6xx/include/mach/spear600.h | 21 +++ arch/arm/mach-spear6xx/include/mach/system.h | 41 +++++ arch/arm/mach-spear6xx/include/mach/timex.h | 19 +++ arch/arm/mach-spear6xx/include/mach/uncompress.h | 43 +++++ arch/arm/mach-spear6xx/include/mach/vmalloc.h | 22 +++ 15 files changed, 787 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-spear6xx/include/mach/debug-macro.S create mode 100644 arch/arm/mach-spear6xx/include/mach/dma.h create mode 100644 arch/arm/mach-spear6xx/include/mach/entry-macro.S create mode 100644 arch/arm/mach-spear6xx/include/mach/generic.h create mode 100644 arch/arm/mach-spear6xx/include/mach/hardware.h create mode 100644 arch/arm/mach-spear6xx/include/mach/io.h create mode 100755 arch/arm/mach-spear6xx/include/mach/irqs.h create mode 100644 arch/arm/mach-spear6xx/include/mach/memory.h create mode 100755 arch/arm/mach-spear6xx/include/mach/misc_regs.h create mode 100644 arch/arm/mach-spear6xx/include/mach/spear.h create mode 100644 arch/arm/mach-spear6xx/include/mach/spear600.h create mode 100644 arch/arm/mach-spear6xx/include/mach/system.h create mode 100644 arch/arm/mach-spear6xx/include/mach/timex.h create mode 100644 arch/arm/mach-spear6xx/include/mach/uncompress.h create mode 100644 arch/arm/mach-spear6xx/include/mach/vmalloc.h diff --git a/arch/arm/mach-spear6xx/include/mach/debug-macro.S b/arch/arm/mach-spear6xx/include/mach/debug-macro.S new file mode 100644 index 0000000..a3ac823 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/debug-macro.S @@ -0,0 +1,38 @@ +/* + * arch/arm/mach-spear6xx/include/mach/debug-macro.S + * + * Debugging macro include header for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/amba/serial.h> +#include <mach/spear.h> + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, =SPEAR6XX_ICM1_UART0_BASE @ Physical base + movne \rx, =VA_SPEAR6XX_ICM1_UART0_BASE @ Virtual base + .endm + + .macro senduart, rd, rx + strb \rd, [\rx, #UART01x_DR] @ ASC_TX_BUFFER + .endm + + .macro waituart, rd, rx +1001: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER + tst \rd, #UART01x_FR_TXFF @ TX_FULL + bne 1001b + .endm + + .macro busyuart, rd, rx +1002: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER + tst \rd, #UART011_FR_TXFE @ TX_EMPTY + beq 1002b + .endm diff --git a/arch/arm/mach-spear6xx/include/mach/dma.h b/arch/arm/mach-spear6xx/include/mach/dma.h new file mode 100644 index 0000000..c4afd17 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/dma.h @@ -0,0 +1,17 @@ +/* + * arch/arm/mach-spear6xx/include/mach/dma.h + * + * Generic SPEAr6XX machine family DMA support + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#endif /* __ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/entry-macro.S b/arch/arm/mach-spear6xx/include/mach/entry-macro.S new file mode 100644 index 0000000..9eaecae --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/entry-macro.S @@ -0,0 +1,55 @@ +/* + * arch/arm/mach-spear6xx/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <mach/hardware.h> +#include <mach/spear.h> +#include <asm/hardware/vic.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \base, =VA_SPEAR6XX_CPU_VIC_PRI_BASE + ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status + mov \irqnr, #0 + teq \irqstat, #0 + bne 1001f + ldr \base, =VA_SPEAR6XX_CPU_VIC_SEC_BASE + ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status + teq \irqstat, #0 + beq 1002f @ this will set/reset + @ zero register + mov \irqnr, #32 +1001: + /* + * Following code will find bit position of least significang + * bit set in irqstat, using following equation + * least significant bit set in n = (n & ~(n-1)) + */ + sub \tmp, \irqstat, #1 @ tmp = irqstat - 1 + mvn \tmp, \tmp @ tmp = ~tmp + and \irqstat, \irqstat, \tmp @ irqstat &= tmp + /* Now, irqstat is = bit no. of 1st bit set in vic irq status */ + clz \tmp, \irqstat @ tmp = leading zeros + + rsb \tmp, \tmp, #0x1F @ tmp = 32 - tmp - 1 + add \irqnr, \irqnr, \tmp + +1002: /* EQ will be set if no irqs pending */ + .endm diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h new file mode 100644 index 0000000..9c3f91f --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/generic.h @@ -0,0 +1,37 @@ +/* + * arch/arm/mach-spear6xx/include/mach/generic.h + * + * SPEAr6XX machine family specific generic header file + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_GENERIC_H +#define __ASM_ARCH_GENERIC_H + +#include <asm/mach/time.h> +#include <asm/mach/map.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/amba/bus.h> + +/* Add spear6xx family device structure declarations here */ +extern struct amba_device uart_device[]; +extern struct sys_timer spear_sys_timer; + +/* Add spear600 machine device structure declarations here */ + +/* Add spear6xx family function declarations here */ +void __init spear6xx_map_io(void); +void __init spear6xx_init_irq(void); +void __init spear6xx_init(void); +void __init spear600_init(void); +void __init spear_gpt_init(void); +void __init clk_init(void); + +#endif /* __ASM_ARCH_GENERIC_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h new file mode 100644 index 0000000..e9a268e --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/hardware.h @@ -0,0 +1,21 @@ +/* + * arch/arm/mach-spear6xx/include/mach/hardware.h + * + * Hardware definitions for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_HARDWARE_H +#define __ASM_MACH_HARDWARE_H + +/* Vitual to physical translation of statically mapped space */ +#define IO_ADDRESS(x) (x | 0xF0000000) + +#endif /* __ASM_MACH_HARDWARE_H */ + diff --git a/arch/arm/mach-spear6xx/include/mach/io.h b/arch/arm/mach-spear6xx/include/mach/io.h new file mode 100644 index 0000000..0563910 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/io.h @@ -0,0 +1,23 @@ +/* + * arch/arm/mach-spear6xx/include/mach/io.h + * + * IO definitions for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARM_MACH_IO_H +#define __ASM_ARM_MACH_IO_H + +#define IO_SPACE_LIMIT 0xFFFFFFFF + +#define __io(a) __typesafe_io(a) +#define __mem_pci(a) (a) + +#endif /* __ASM_ARM_MACH_IO_H */ + diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h new file mode 100755 index 0000000..a626068 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/irqs.h @@ -0,0 +1,92 @@ +/* + * arch/arm/mach-spear6xx/include/mach/irqs.h + * + * IRQ helper macros for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_IRQS_H +#define __ASM_MACH_IRQS_H + +/* IRQ definitions */ +/* VIC 1 */ +#define IRQ_INTRCOMM_SW_IRQ 0 +#define IRQ_INTRCOMM_CPU_1 1 +#define IRQ_INTRCOMM_CPU_2 2 +#define IRQ_INTRCOMM_RAS2A11_1 3 +#define IRQ_INTRCOMM_RAS2A11_2 4 +#define IRQ_INTRCOMM_RAS2A12_1 5 +#define IRQ_INTRCOMM_RAS2A12_2 6 +#define IRQ_GEN_RAS_0 7 +#define IRQ_GEN_RAS_1 8 +#define IRQ_GEN_RAS_2 9 +#define IRQ_GEN_RAS_3 10 +#define IRQ_GEN_RAS_4 11 +#define IRQ_GEN_RAS_5 12 +#define IRQ_GEN_RAS_6 13 +#define IRQ_GEN_RAS_7 14 +#define IRQ_GEN_RAS_8 15 +#define IRQ_CPU_GPT1_1 16 +#define IRQ_CPU_GPT1_2 17 +#define IRQ_LOCAL_GPIO 18 +#define IRQ_PLL_UNLOCK 19 +#define IRQ_JPEG 20 +#define IRQ_FSMC 21 +#define IRQ_IRDA 22 +#define IRQ_RESERVED 23 +#define IRQ_UART_0 24 +#define IRQ_UART_1 25 +#define IRQ_SSP_1 26 +#define IRQ_SSP_2 27 +#define IRQ_I2C 28 +#define IRQ_GEN_RAS_9 29 +#define IRQ_GEN_RAS_10 30 +#define IRQ_GEN_RAS_11 31 + +/* VIC 2 */ +#define IRQ_APPL_GPT1_1 32 +#define IRQ_APPL_GPT1_2 33 +#define IRQ_APPL_GPT2_1 34 +#define IRQ_APPL_GPT2_2 35 +#define IRQ_APPL_GPIO 36 +#define IRQ_APPL_SSP 37 +#define IRQ_APPL_ADC 38 +#define IRQ_APPL_RESERVED 39 +#define IRQ_AHB_EXP_MASTER 40 +#define IRQ_DDR_CONTROLLER 41 +#define IRQ_BASIC_DMA 42 +#define IRQ_BASIC_RESERVED1 43 +#define IRQ_BASIC_SMI 44 +#define IRQ_BASIC_CLCD 45 +#define IRQ_EXP_AHB_1 46 +#define IRQ_EXP_AHB_2 47 +#define IRQ_BASIC_GPT1_1 48 +#define IRQ_BASIC_GPT1_2 49 +#define IRQ_BASIC_RTC 50 +#define IRQ_BASIC_GPIO 51 +#define IRQ_BASIC_WDT 52 +#define IRQ_BASIC_RESERVED 53 +#define IRQ_AHB_EXP_SLAVE 54 +#define IRQ_GMAC_1 55 +#define IRQ_GMAC_2 56 +#define IRQ_USB_DEV 57 +#define IRQ_USB_H_OHCI_0 58 +#define IRQ_USB_H_EHCI_0 59 +#define IRQ_USB_H_OHCI_1 60 +#define IRQ_USB_H_EHCI_1 61 +#define IRQ_EXP_AHB_3 62 +#define IRQ_EXP_AHB_4 63 + +#define IRQ_VIC_END 64 + +#define SPEAR_GPIO_INT_BASE IRQ_VIC_END +#define VIRTUAL_IRQS 0 +#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) + +#endif /* __ASM_MACH_IRQS_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/memory.h b/arch/arm/mach-spear6xx/include/mach/memory.h new file mode 100644 index 0000000..f0e4627 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/memory.h @@ -0,0 +1,20 @@ +/* + * arch/arm/mach-spear6xx/include/mach/memory.h + * + * Memory map for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_MEMORY_H +#define __ASM_MACH_MEMORY_H + +/* Physical DRAM offset.*/ +#define PHYS_OFFSET UL(0x00000000) + +#endif /* __ASM_MACH_MEMORY_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h new file mode 100755 index 0000000..6184107 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h @@ -0,0 +1,173 @@ +/* + * arch/arm/mach-spear6xx/include/mach/misc_regs.h + * + * Miscellaneous registers definitions for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_MISC_REGS_H +#define __ASM_MACH_MISC_REGS_H + +#include <mach/spear.h> + +#define MISC_BASE VA_SPEAR6XX_ICM3_MISC_REG_BASE + +#define SOC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x000)) +#define DIAG_CFG_CTR ((unsigned int *)(MISC_BASE + 0x004)) +#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x008)) +#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x00C)) +#define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x010)) +#define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x014)) +/* PLL_CTR register masks */ +#define PLL_ENABLE 2 +#define PLL_MODE_SHIFT 4 +#define PLL_MODE_MASK 0x3 +#define PLL_MODE_NORMAL 0 +#define PLL_MODE_FRACTION 1 +#define PLL_MODE_DITH_DSB 2 +#define PLL_MODE_DITH_SSB 3 + +#define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x018)) +/* PLL FRQ register masks */ +#define PLL_DIV_N_SHIFT 0 +#define PLL_DIV_N_MASK 0xFF +#define PLL_DIV_P_SHIFT 8 +#define PLL_DIV_P_MASK 0x7 +#define PLL_NORM_FDBK_M_SHIFT 24 +#define PLL_NORM_FDBK_M_MASK 0xFF +#define PLL_DITH_FDBK_M_SHIFT 16 +#define PLL_DITH_FDBK_M_MASK 0xFFFF + +#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C)) +#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020)) +#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024)) +/* CORE CLK CFG register masks */ +#define PLL_HCLK_RATIO_SHIFT 10 +#define PLL_HCLK_RATIO_MASK 0x3 +#define HCLK_PCLK_RATIO_SHIFT 8 +#define HCLK_PCLK_RATIO_MASK 0x3 + +#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x028)) +/* PERIP_CLK_CFG register masks */ +#define CLCD_CLK_SHIFT 2 +#define CLCD_CLK_MASK 0x3 +#define UART_CLK_SHIFT 4 +#define UART_CLK_MASK 0x1 +#define FIRDA_CLK_SHIFT 5 +#define FIRDA_CLK_MASK 0x3 +#define GPT0_CLK_SHIFT 8 +#define GPT1_CLK_SHIFT 10 +#define GPT2_CLK_SHIFT 11 +#define GPT3_CLK_SHIFT 12 +#define GPT_CLK_MASK 0x1 +#define AUX_CLK_PLL3_MASK 0 +#define AUX_CLK_PLL1_MASK 1 + +#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C)) +/* PERIP1_CLK_ENB register masks */ +#define UART0_CLK_ENB 3 +#define UART1_CLK_ENB 4 +#define SSP0_CLK_ENB 5 +#define SSP1_CLK_ENB 6 +#define I2C_CLK_ENB 7 +#define JPEG_CLK_ENB 8 +#define FSMC_CLK_ENB 9 +#define FIRDA_CLK_ENB 10 +#define GPT2_CLK_ENB 11 +#define GPT3_CLK_ENB 12 +#define GPIO2_CLK_ENB 13 +#define SSP2_CLK_ENB 14 +#define ADC_CLK_ENB 15 +#define GPT1_CLK_ENB 11 +#define RTC_CLK_ENB 17 +#define GPIO1_CLK_ENB 18 +#define DMA_CLK_ENB 19 +#define SMI_CLK_ENB 21 +#define CLCD_CLK_ENB 22 +#define GMAC_CLK_ENB 23 +#define USBD_CLK_ENB 24 +#define USBH0_CLK_ENB 25 +#define USBH1_CLK_ENB 26 + +#define SOC_CORE_ID ((unsigned int *)(MISC_BASE + 0x030)) +#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x034)) +#define PERIP1_SOF_RST ((unsigned int *)(MISC_BASE + 0x038)) +/* PERIP1_SOF_RST register masks */ +#define JPEG_SOF_RST 8 + +#define SOC_USER_ID ((unsigned int *)(MISC_BASE + 0x03C)) +#define RAS_SOF_RST ((unsigned int *)(MISC_BASE + 0x040)) +#define PRSC1_CLK_CFG ((unsigned int *)(MISC_BASE + 0x044)) +#define PRSC2_CLK_CFG ((unsigned int *)(MISC_BASE + 0x048)) +#define PRSC3_CLK_CFG ((unsigned int *)(MISC_BASE + 0x04C)) +/* gpt synthesizer register masks */ +#define GPT_MSCALE_SHIFT 0 +#define GPT_MSCALE_MASK 0xFFF +#define GPT_NSCALE_SHIFT 12 +#define GPT_NSCALE_MASK 0xF + +#define AMEM_CLK_CFG ((unsigned int *)(MISC_BASE + 0x050)) +#define EXPI_CLK_CFG ((unsigned int *)(MISC_BASE + 0x054)) +#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x05C)) +#define FIRDA_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x060)) +#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x064)) +#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x068)) +#define RAS1_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x06C)) +#define RAS2_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x070)) +#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074)) +#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078)) +/* aux clk synthesiser register masks for irda to ras4 */ +#define AUX_EQ_SEL_SHIFT 30 +#define AUX_EQ_SEL_MASK 1 +#define AUX_EQ1_SEL 0 +#define AUX_EQ2_SEL 1 +#define AUX_XSCALE_SHIFT 16 +#define AUX_XSCALE_MASK 0xFFF +#define AUX_YSCALE_SHIFT 0 +#define AUX_YSCALE_MASK 0xFFF + +#define ICM1_ARB_CFG ((unsigned int *)(MISC_BASE + 0x07C)) +#define ICM2_ARB_CFG ((unsigned int *)(MISC_BASE + 0x080)) +#define ICM3_ARB_CFG ((unsigned int *)(MISC_BASE + 0x084)) +#define ICM4_ARB_CFG ((unsigned int *)(MISC_BASE + 0x088)) +#define ICM5_ARB_CFG ((unsigned int *)(MISC_BASE + 0x08C)) +#define ICM6_ARB_CFG ((unsigned int *)(MISC_BASE + 0x090)) +#define ICM7_ARB_CFG ((unsigned int *)(MISC_BASE + 0x094)) +#define ICM8_ARB_CFG ((unsigned int *)(MISC_BASE + 0x098)) +#define ICM9_ARB_CFG ((unsigned int *)(MISC_BASE + 0x09C)) +#define DMA_CHN_CFG ((unsigned int *)(MISC_BASE + 0x0A0)) +#define USB2_PHY_CFG ((unsigned int *)(MISC_BASE + 0x0A4)) +#define GMAC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0A8)) +#define EXPI_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0AC)) +#define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C0)) +#define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C4)) +#define PRC3_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C8)) +#define PRC4_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0CC)) +#define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D0)) +#define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D4)) +#define PRC3_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D8)) +#define PRC4_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0DC)) +#define PWRDOWN_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0E0)) +#define COMPSSTL_1V8_CFG ((unsigned int *)(MISC_BASE + 0x0E4)) +#define COMPSSTL_2V5_CFG ((unsigned int *)(MISC_BASE + 0x0E8)) +#define COMPCOR_3V3_CFG ((unsigned int *)(MISC_BASE + 0x0EC)) +#define SSTLPAD_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F0)) +#define BIST1_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F4)) +#define BIST2_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F8)) +#define BIST3_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0FC)) +#define BIST4_CFG_CTR ((unsigned int *)(MISC_BASE + 0x100)) +#define BIST5_CFG_CTR ((unsigned int *)(MISC_BASE + 0x104)) +#define BIST1_STS_RES ((unsigned int *)(MISC_BASE + 0x108)) +#define BIST2_STS_RES ((unsigned int *)(MISC_BASE + 0x10C)) +#define BIST3_STS_RES ((unsigned int *)(MISC_BASE + 0x110)) +#define BIST4_STS_RES ((unsigned int *)(MISC_BASE + 0x114)) +#define BIST5_STS_RES ((unsigned int *)(MISC_BASE + 0x118)) +#define SYSERR_CFG_CTR ((unsigned int *)(MISC_BASE + 0x11C)) + +#endif /* __ASM_MACH_MISC_REGS_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h new file mode 100644 index 0000000..9df2ef2 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/spear.h @@ -0,0 +1,165 @@ +/* + * arch/arm/mach-spear6xx/include/mach/spear.h + * + * SPEAr6xx Machine family specific definition + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_SPEAR6XX_H +#define __ASM_MACH_SPEAR6XX_H + +#include <mach/hardware.h> +#include <mach/spear600.h> + +/* ICM1 - Low speed connection */ +#define SPEAR6XX_ICM1_BASE 0xD0000000 +#define SPEAR6XX_ICM1_SIZE 0x10000000 + +#define SPEAR6XX_ICM1_UART0_BASE 0xD0000000 +#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE) +#define SPEAR6XX_ICM1_UART0_SIZE 0x00080000 + +#define SPEAR6XX_ICM1_UART1_BASE 0xD0080000 +#define SPEAR6XX_ICM1_UART1_SIZE 0x00080000 + +#define SPEAR6XX_ICM1_SSP0_BASE 0xD0100000 +#define SPEAR6XX_ICM1_SSP0_SIZE 0x00080000 + +#define SPEAR6XX_ICM1_SSP1_BASE 0xD0180000 +#define SPEAR6XX_ICM1_SSP1_SIZE 0x00080000 + +#define SPEAR6XX_ICM1_I2C_BASE 0xD0200000 +#define SPEAR6XX_ICM1_I2C_SIZE 0x00080000 + +#define SPEAR6XX_ICM1_JPEG_BASE 0xD0800000 +#define SPEAR6XX_ICM1_JPEG_SIZE 0x00800000 + +#define SPEAR6XX_ICM1_IRDA_BASE 0xD1000000 +#define SPEAR6XX_ICM1_IRDA_SIZE 0x00080000 + +#define SPEAR6XX_ICM1_FSMC_BASE 0xD1800000 +#define SPEAR6XX_ICM1_FSMC_SIZE 0x00800000 + +#define SPEAR6XX_ICM1_NAND_BASE 0xD2000000 +#define SPEAR6XX_ICM1_NAND_SIZE 0x00800000 + +#define SPEAR6XX_ICM1_SRAM_BASE 0xD2800000 +#define SPEAR6XX_ICM1_SRAM_SIZE 0x00800000 + +/* ICM2 - Application Subsystem */ +#define SPEAR6XX_ICM2_BASE 0xD8000000 +#define SPEAR6XX_ICM2_SIZE 0x08000000 + +#define SPEAR6XX_ICM2_TMR0_BASE 0xD8000000 +#define SPEAR6XX_ICM2_SRAM_SIZE 0x00800000 + +#define SPEAR6XX_ICM2_TMR1_BASE 0xD8080000 +#define SPEAR6XX_ICM2_SRAM_SIZE 0x00800000 + +#define SPEAR6XX_ICM2_GPIO_BASE 0xD8100000 +#define SPEAR6XX_ICM2_SRAM_SIZE 0x00800000 + +#define SPEAR6XX_ICM2_SPI2_BASE 0xD8180000 +#define SPEAR6XX_ICM2_SPI2_SIZE 0x00800000 + +#define SPEAR6XX_ICM2_ADC_BASE 0xD8200000 +#define SPEAR6XX_ICM2_ADC_SIZE 0x00800000 + +/* ML-1, 2 - Multi Layer CPU Subsystem */ +#define SPEAR6XX_ML_CPU_BASE 0xF0000000 +#define SPEAR6XX_ML_CPU_SIZE 0x0F000000 + +#define SPEAR6XX_ML_SDRAM_BASE 0x00000000 +#define SPEAR6XX_ML_SDRAM_SIZE 0x40000000 + +#define SPEAR6XX_CPU_TMR_BASE 0xF0000000 +#define SPEAR6XX_CPU_TMR_SIZE 0x00100000 + +#define SPEAR6XX_CPU_GPIO_BASE 0xF0100000 +#define SPEAR6XX_CPU_GPIO_SIZE 0x00100000 + +#define SPEAR6XX_CPU_VIC_SEC_BASE 0xF1000000 +#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE) +#define SPEAR6XX_CPU_VIC_SEC_SIZE 0x00100000 + +#define SPEAR6XX_CPU_VIC_PRI_BASE 0xF1100000 +#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE) +#define SPEAR6XX_CPU_VIC_PRI_SIZE 0x00100000 + +/* ICM3 - Basic Subsystem */ +#define SPEAR6XX_ICM3_BASE 0xF8000000 +#define SPEAR6XX_ICM3_SIZE 0x08000000 + +#define SPEAR6XX_ICM3_SFLASH_BASE 0xF8000000 +#define SPEAR6XX_ICM3_SFLASH_SIZE 0x04000000 + +#define SPEAR6XX_ICM3_SFLASH_CTRL_BASE 0xFC000000 +#define SPEAR6XX_ICM3_SFLASH_CTRL_SIZE 0x04000000 + +#define SPEAR6XX_ICM3_CLCD_BASE 0xFC200000 +#define SPEAR6XX_ICM3_CLCD_SIZE 0x00200000 + +#define SPEAR6XX_ICM3_DMA_BASE 0xFC400000 +#define SPEAR6XX_ICM3_DMA_SIZE 0x00200000 + +#define SPEAR6XX_ICM3_SDRAM_BASE 0xFC600000 +#define SPEAR6XX_ICM3_SDRAM_SIZE 0x00200000 + +#define SPEAR6XX_ICM3_TMR_BASE 0xFC800000 +#define SPEAR6XX_ICM3_TMR_SIZE 0x00080000 + +#define SPEAR6XX_ICM3_WDT_BASE 0xFC880000 +#define SPEAR6XX_ICM3_WDT_SIZE 0x00080000 + +#define SPEAR6XX_ICM3_RTC_BASE 0xFC900000 +#define SPEAR6XX_ICM3_RTC_SIZE 0x00080000 + +#define SPEAR6XX_ICM3_GPIO_BASE 0xFC980000 +#define SPEAR6XX_ICM3_GPIO_SIZE 0x00080000 + +#define SPEAR6XX_ICM3_SYS_CTRL_BASE 0xFCA00000 +#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE) +#define SPEAR6XX_ICM3_SYS_CTRL_SIZE 0x00080000 + +#define SPEAR6XX_ICM3_MISC_REG_BASE 0xFCA80000 +#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE) +#define SPEAR6XX_ICM3_MISC_REG_SIZE 0x00080000 + +/* ICM4 - High Speed Connection */ +#define SPEAR6XX_ICM4_BASE 0xE0000000 +#define SPEAR6XX_ICM4_SIZE 0x08000000 + +#define SPEAR6XX_ICM4_GMAC_BASE 0xE0800000 +#define SPEAR6XX_ICM4_GMAC_SIZE 0x00800000 + +#define SPEAR6XX_ICM4_USBD_FIFO_BASE 0xE1000000 +#define SPEAR6XX_ICM4_USBD_FIFO_SIZE 0x00100000 + +#define SPEAR6XX_ICM4__USBD_CFG_BASE 0xE1100000 +#define SPEAR6XX_ICM4_USBD_CFG_SIZE 0x00100000 + +#define SPEAR6XX_ICM4_USBD_PLUG_BASE 0xE1200000 +#define SPEAR6XX_ICM4_USBD_PLUG_SIZE 0x00100000 + +#define SPEAR6XX_ICM4_USB_EHCI0_BASE 0xE1800000 +#define SPEAR6XX_ICM4_USB_EHCI0_SIZE 0x00100000 + +#define SPEAR6XX_ICM4_USB_OHCI0_BASE 0xE1900000 +#define SPEAR6XX_ICM4_USB_OHCI0_SIZE 0x00100000 + +#define SPEAR6XX_ICM4_USB_EHCI1_BASE 0xE2000000 +#define SPEAR6XX_ICM4_USB_EHCI1_SIZE 0x00100000 + +#define SPEAR6XX_ICM4_USB_OHCI1_BASE 0xE2100000 +#define SPEAR6XX_ICM4_USB_OHCI1_SIZE 0x00100000 + +#define SPEAR6XX_ICM4_USB_ARB_CFG_BASE 0xE2800000 +#define SPEAR6XX_ICM4_USB_ARB_SIZE 0x00010000 + +#endif /* __ASM_MACH_SPEAR6XX_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/spear600.h b/arch/arm/mach-spear6xx/include/mach/spear600.h new file mode 100644 index 0000000..6b62fb7 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/spear600.h @@ -0,0 +1,21 @@ +/* + * arch/arm/mach-spear66xx/include/mach/spear600.h + * + * SPEAr600 Machine specific definition + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifdef CONFIG_MACH_SPEAR600 + +#ifndef __ASM_MACH_SPEAR600_H +#define __ASM_MACH_SPEAR600_H + +#endif /* __ASM_MACH_SPEAR600_H */ + +#endif /* CONFIG_MACH_SPEAR600 */ diff --git a/arch/arm/mach-spear6xx/include/mach/system.h b/arch/arm/mach-spear6xx/include/mach/system.h new file mode 100644 index 0000000..8a70c46 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/system.h @@ -0,0 +1,41 @@ +/* + * arch/arm/mach-spear6xx/include/mach/system.h + * + * SPEAr6xx Machine family specific architecture functions + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_SYSTEM_H +#define __ASM_MACH_SYSTEM_H + +#include <linux/io.h> +#include <linux/sysctl_sp810.h> +#include <mach/spear.h> + +static inline void arch_idle(void) +{ + /* + * This should do all the clock switching + * and wait for interrupt tricks + */ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + if (mode == 's') { + /* software reset, Jump into ROM at address 0 */ + cpu_reset(0); + } else { + /* hardware reset, Use on-chip reset capability */ + sysctl_soft_reset(SPEAR6XX_ICM3_SYS_CTRL_BASE); + } +} + +#endif /* __ASM_MACH_SYSTEM_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/timex.h b/arch/arm/mach-spear6xx/include/mach/timex.h new file mode 100644 index 0000000..f02ec47 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/timex.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear6xx/include/mach/timex.h + * + * SPEAr6XX machine family specific timex definitions + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_TIMEX_H +#define __ASM_MACH_TIMEX_H + +#define CLOCK_TICK_RATE 48000000 + +#endif /* __ASM_MACH_TIMEX_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/uncompress.h b/arch/arm/mach-spear6xx/include/mach/uncompress.h new file mode 100644 index 0000000..2ea6878 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/uncompress.h @@ -0,0 +1,43 @@ +/* + * arch/arm/mach-spear6xx/include/mach/uncompress.h + * + * Serial port stubs for kernel decompress status messages + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/io.h> +#include <linux/amba/serial.h> +#include <mach/spear.h> + +#ifndef __ASM_MACH_UNCOMPRESS_H +#define __ASM_MACH_UNCOMPRESS_H +/* +* This does not append a newline +*/ +static inline void putc(int c) +{ + void __iomem *base = (void __iomem *)SPEAR6XX_ICM1_UART0_BASE; + + while (readl(base + UART01x_FR) & UART01x_FR_TXFF) + barrier(); + + writel(c, base + UART01x_DR); +} + +static inline void flush(void) +{ +} + +/* +* nothing to do +*/ +#define arch_decomp_setup() +#define arch_decomp_wdog() + +#endif /* __ASM_MACH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-spear6xx/include/mach/vmalloc.h b/arch/arm/mach-spear6xx/include/mach/vmalloc.h new file mode 100644 index 0000000..59f3c06 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/vmalloc.h @@ -0,0 +1,22 @@ +/* + * arch/arm/mach-spear6xx/include/mach/vmalloc.h + * + * Defining Vmalloc area for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_VMALLOC_H +#define __ASM_MACH_VMALLOC_H + +#include <mach/memory.h> + +#define VMALLOC_SIZE (0x30000000) +#define VMALLOC_END (PAGE_OFFSET + VMALLOC_SIZE) + +#endif /* __ASM_MACH_VMALLOC_H */ -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform 2010-03-03 5:07 ` [PATCH 03/11] ST SPEAr: Added basic header files for SPEAr6xx " Viresh KUMAR @ 2010-03-03 5:07 ` Viresh KUMAR 2010-03-03 5:07 ` [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines Viresh KUMAR 2010-03-10 5:40 ` [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform Linus Walleij 0 siblings, 2 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-03 5:07 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Viresh Kumar <viresh.kumar@st.com> --- arch/arm/plat-spear/include/plat/gpt.h | 108 ++++++++++++++++++++++++++++++++ 1 files changed, 108 insertions(+), 0 deletions(-) create mode 100644 arch/arm/plat-spear/include/plat/gpt.h diff --git a/arch/arm/plat-spear/include/plat/gpt.h b/arch/arm/plat-spear/include/plat/gpt.h new file mode 100644 index 0000000..1ac6cf0 --- /dev/null +++ b/arch/arm/plat-spear/include/plat/gpt.h @@ -0,0 +1,108 @@ +/* + * arch/arm/plat-spear/include/plat/gpt.h + * + * SPEAr General Purpose Timers header file + * + * Copyright (C) 2010 ST Microelectronics + * shiraz hashim <shiraz.hashim@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_PLAT_GPT_H +#define __ASM_PLAT_GPT_H + +/* register offsets */ +#define GPT_CTRL_OFF 0x80 /* Control Register */ +#define GPT_INT_OFF 0x84 /* Interrupt Regiset */ +#define GPT_LOAD_OFF 0x88 /* Load Register */ +#define GPT_COUNT_OFF 0x8C /* Current Count Register */ + +/* CTRL Reg Bit Values */ +#define GPT_CTRL_MATCH_INT 0x0100 +#define GPT_CTRL_ENABLE 0x0020 +#define GPT_CTRL_MODE_AR 0x0010 + +#define GPT_CTRL_PRESCALER1 0x0 +#define GPT_CTRL_PRESCALER2 0x1 +#define GPT_CTRL_PRESCALER4 0x2 +#define GPT_CTRL_PRESCALER8 0x3 +#define GPT_CTRL_PRESCALER16 0x4 +#define GPT_CTRL_PRESCALER32 0x5 +#define GPT_CTRL_PRESCALER64 0x6 +#define GPT_CTRL_PRESCALER128 0x7 +#define GPT_CTRL_PRESCALER256 0x8 + +/* INT Reg Bit Values */ +#define GPT_STATUS_MATCH 0x0001 + +/* clock sources */ +#define SPEAR_TIMER_SRC_PLL3_CLK 0x00 +#define SPEAR_TIMER_SRC_SYS_CLK 0x01 + +/** + * struct spear_timer - spear general purpose timer representation + * @id: timer identifier 0 onwards + * @phys_base: physical base address of timer + * @irq: irq to which this gpt is attached + * @prescaler: the prescaler for input freq at which timer is working + * @fclk: gpt functional clock + * @io_base: virtual base address of timer + * @reserved: indication that gpt is reserved now + * @enabled: indication that gpt is enabled + * + * The timer structure represent the timer channel available in SPEAr. Each + * timer unit in SPEAr contains two individual timer channels with different + * set of configuration registers * and irq. But the point to remember is + * this that the fclk is common for each channels withing a timer unit. + */ + +struct spear_timer { + unsigned int id; + unsigned long phys_base; + int irq; + int prescaler; + struct clk *fclk; + void __iomem *io_base; + unsigned reserved:1; + unsigned enabled:1; +}; + +/* + * Following functions are exported by gpt.c which can be used by other + * kernel entities + */ +int spear_timer_init(struct spear_timer *, int); + +struct spear_timer *spear_timer_request(void); +struct spear_timer *spear_timer_request_specific(int id); + +int spear_timer_free(struct spear_timer *timer); +int spear_timer_enable(struct spear_timer *timer); +int spear_timer_disable(struct spear_timer *timer); + +int spear_timer_get_irq(struct spear_timer *timer); + +struct clk *spear_timer_get_fclk(struct spear_timer *timer); + +int spear_timer_start(struct spear_timer *timer); +int spear_timer_stop(struct spear_timer *timer); + +int spear_timer_set_source(struct spear_timer *timer, int source); +int spear_timer_set_load(struct spear_timer *timer, int autoreload, + u16 value); +int spear_timer_set_load_start(struct spear_timer *timer, int autoreload, + u16 value); +int spear_timer_match_irq(struct spear_timer *timer, int enable); +int spear_timer_set_prescaler(struct spear_timer *timer, int prescaler); + +int spear_timer_read_status(struct spear_timer *timer); +int spear_timer_clear_status(struct spear_timer *timer, u16 value); + +int spear_timer_read_counter(struct spear_timer *timer); + +int spear_timer_active(struct spear_timer *); + +#endif /* __ASM_PLAT_GPT_H */ -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines 2010-03-03 5:07 ` [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform Viresh KUMAR @ 2010-03-03 5:07 ` Viresh KUMAR 2010-03-03 5:07 ` [PATCH 06/11] ST SPEAr: Added source files for SPEAr platform Viresh KUMAR ` (2 more replies) 2010-03-10 5:40 ` [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform Linus Walleij 1 sibling, 3 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-03 5:07 UTC (permalink / raw) To: linux-arm-kernel Clock framework for SPEAr is based upon clkdev framework for ARM Signed-off-by: Viresh Kumar <viresh.kumar@st.com> --- arch/arm/mach-spear3xx/clock.c | 525 +++++++++++++++++++++ arch/arm/mach-spear3xx/include/mach/clkdev.h | 19 + arch/arm/mach-spear6xx/clock.c | 656 ++++++++++++++++++++++++++ arch/arm/mach-spear6xx/include/mach/clkdev.h | 19 + arch/arm/plat-spear/clock.c | 433 +++++++++++++++++ arch/arm/plat-spear/include/plat/clkdev.h | 20 + arch/arm/plat-spear/include/plat/clock.h | 130 +++++ 7 files changed, 1802 insertions(+), 0 deletions(-) create mode 100755 arch/arm/mach-spear3xx/clock.c create mode 100644 arch/arm/mach-spear3xx/include/mach/clkdev.h create mode 100755 arch/arm/mach-spear6xx/clock.c create mode 100644 arch/arm/mach-spear6xx/include/mach/clkdev.h create mode 100755 arch/arm/plat-spear/clock.c create mode 100644 arch/arm/plat-spear/include/plat/clkdev.h create mode 100755 arch/arm/plat-spear/include/plat/clock.h diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c new file mode 100755 index 0000000..005fecc --- /dev/null +++ b/arch/arm/mach-spear3xx/clock.c @@ -0,0 +1,525 @@ +/* + * arch/arm/mach-spear3xx/clock.c + * + * SPEAr3xx machines clock framework source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <mach/misc_regs.h> +#include <plat/clock.h> + +/* root clks */ +/* 32 KHz oscillator clock */ +static struct clk osc_32k_clk = { + .flags = ALWAYS_ENABLED, + .rate = 32 * KHZ, +}; + +static struct clk_lookup osc_32k_cl = { + .con_id = "osc_32k_clk", + .clk = &osc_32k_clk, +}; + +/* 24 MHz oscillator clock */ +static struct clk osc_24m_clk = { + .flags = ALWAYS_ENABLED, + .rate = 24 * MHZ, +}; + +static struct clk_lookup osc_24m_cl = { + .con_id = "osc_24m_clk", + .clk = &osc_24m_clk, +}; + +/* clock derived from 32 KHz osc clk */ +/* rtc clock */ +static struct clk rtc_clk = { + .pclk = &osc_32k_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = RTC_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup rtc_cl = { + .dev_id = "rtc", + .clk = &rtc_clk, +}; + +/* clock derived from 24 MHz osc clk */ +/* pll1 configuration structure */ +static struct pll_clk_config pll1_config = { + .mode_reg = PLL1_CTR, + .cfg_reg = PLL1_FRQ, +}; + +/* PLL1 clock */ +static struct clk pll1_clk = { + .pclk = &osc_24m_clk, + .en_reg = PLL1_CTR, + .en_reg_bit = PLL_ENABLE, + .recalc = &pll1_clk_recalc, + .private_data = &pll1_config, +}; + +static struct clk_lookup pll1_cl = { + .con_id = "pll1_clk", + .clk = &pll1_clk, +}; + +/* PLL3 48 MHz clock */ +static struct clk pll3_48m_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &osc_24m_clk, + .rate = 48 * MHZ, +}; + +static struct clk_lookup pll3_48m_cl = { + .con_id = "pll3_48m_clk", + .clk = &pll3_48m_clk, +}; + +/* watch dog timer clock */ +static struct clk wdt_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &osc_24m_clk, + .recalc = &follow_parent, +}; + +static struct clk_lookup wdt_cl = { + .dev_id = "wdt", + .clk = &wdt_clk, +}; + +/* clock derived from pll1 clk */ +/* cpu clock */ +static struct clk cpu_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .recalc = &follow_parent, +}; + +static struct clk_lookup cpu_cl = { + .con_id = "cpu_clk", + .clk = &cpu_clk, +}; + +/* ahb configuration structure */ +static struct bus_clk_config ahb_config = { + .reg = CORE_CLK_CFG, + .mask = PLL_HCLK_RATIO_MASK, + .shift = PLL_HCLK_RATIO_SHIFT, +}; + +/* ahb clock */ +static struct clk ahb_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .recalc = &bus_clk_recalc, + .private_data = &ahb_config, +}; + +static struct clk_lookup ahb_cl = { + .con_id = "ahb_clk", + .clk = &ahb_clk, +}; + +/* uart configurations */ +static struct aux_clk_config uart_config = { + .synth_reg = UART_CLK_SYNT, +}; + +/* uart parents */ +static struct pclk_info uart_pclk_info[] = { + { + .pclk = &pll1_clk, + .pclk_mask = AUX_CLK_PLL1_MASK, + .scalable = 1, + }, { + .pclk = &pll3_48m_clk, + .pclk_mask = AUX_CLK_PLL3_MASK, + .scalable = 0, + }, +}; + +/* uart parent select structure */ +static struct pclk_sel uart_pclk_sel = { + .pclk_info = uart_pclk_info, + .pclk_count = ARRAY_SIZE(uart_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = UART_CLK_MASK, +}; + +/* uart clock */ +static struct clk uart_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = UART_CLK_ENB, + .pclk_sel = &uart_pclk_sel, + .pclk_sel_shift = UART_CLK_SHIFT, + .recalc = &aux_clk_recalc, + .private_data = &uart_config, +}; + +static struct clk_lookup uart_cl = { + .dev_id = "uart", + .clk = &uart_clk, +}; + +/* firda configurations */ +static struct aux_clk_config firda_config = { + .synth_reg = FIRDA_CLK_SYNT, +}; + +/* firda parents */ +static struct pclk_info firda_pclk_info[] = { + { + .pclk = &pll1_clk, + .pclk_mask = AUX_CLK_PLL1_MASK, + .scalable = 1, + }, { + .pclk = &pll3_48m_clk, + .pclk_mask = AUX_CLK_PLL3_MASK, + .scalable = 0, + }, +}; + +/* firda parent select structure */ +static struct pclk_sel firda_pclk_sel = { + .pclk_info = firda_pclk_info, + .pclk_count = ARRAY_SIZE(firda_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = FIRDA_CLK_MASK, +}; + +/* firda clock */ +static struct clk firda_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = FIRDA_CLK_ENB, + .pclk_sel = &firda_pclk_sel, + .pclk_sel_shift = FIRDA_CLK_SHIFT, + .recalc = &aux_clk_recalc, + .private_data = &firda_config, +}; + +static struct clk_lookup firda_cl = { + .dev_id = "firda", + .clk = &firda_clk, +}; + +/* gpt parents */ +static struct pclk_info gpt_pclk_info[] = { + { + .pclk = &pll1_clk, + .pclk_mask = AUX_CLK_PLL1_MASK, + .scalable = 1, + }, { + .pclk = &pll3_48m_clk, + .pclk_mask = AUX_CLK_PLL3_MASK, + .scalable = 0, + }, +}; + +/* gpt parent select structure */ +static struct pclk_sel gpt_pclk_sel = { + .pclk_info = gpt_pclk_info, + .pclk_count = ARRAY_SIZE(gpt_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = GPT_CLK_MASK, +}; + +/* gpt0 configurations */ +static struct aux_clk_config gpt0_config = { + .synth_reg = PRSC1_CLK_CFG, +}; + +/* gpt0 timer clock */ +static struct clk gpt0_clk = { + .flags = ALWAYS_ENABLED, + .pclk_sel = &gpt_pclk_sel, + .pclk_sel_shift = GPT0_CLK_SHIFT, + .recalc = &gpt_clk_recalc, + .private_data = &gpt0_config, +}; + +static struct clk_lookup gpt0_cl = { + .dev_id = "gpt0", + .clk = &gpt0_clk, +}; + +/* gpt1 configurations */ +static struct aux_clk_config gpt1_config = { + .synth_reg = PRSC2_CLK_CFG, +}; + +/* gpt1 timer clock */ +static struct clk gpt1_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPT1_CLK_ENB, + .pclk_sel = &gpt_pclk_sel, + .pclk_sel_shift = GPT1_CLK_SHIFT, + .recalc = &gpt_clk_recalc, + .private_data = &gpt1_config, +}; + +static struct clk_lookup gpt1_cl = { + .dev_id = "gpt1", + .clk = &gpt1_clk, +}; + +/* gpt2 configurations */ +static struct aux_clk_config gpt2_config = { + .synth_reg = PRSC3_CLK_CFG, +}; + +/* gpt2 timer clock */ +static struct clk gpt2_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPT2_CLK_ENB, + .pclk_sel = &gpt_pclk_sel, + .pclk_sel_shift = GPT2_CLK_SHIFT, + .recalc = &gpt_clk_recalc, + .private_data = &gpt2_config, +}; + +static struct clk_lookup gpt2_cl = { + .dev_id = "gpt2", + .clk = &gpt2_clk, +}; + +/* clock derived from pll3 clk */ +/* usbh clock */ +static struct clk usbh_clk = { + .pclk = &pll3_48m_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = USBH_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup usbh_cl = { + .dev_id = "usbh", + .clk = &usbh_clk, +}; + +/* usbd clock */ +static struct clk usbd_clk = { + .pclk = &pll3_48m_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = USBD_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup usbd_cl = { + .dev_id = "usbd", + .clk = &usbd_clk, +}; + +/* clcd clock */ +static struct clk clcd_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll3_48m_clk, + .recalc = &follow_parent, +}; + +static struct clk_lookup clcd_cl = { + .dev_id = "clcd", + .clk = &clcd_clk, +}; + +/* clock derived from ahb clk */ +/* apb configuration structure */ +static struct bus_clk_config apb_config = { + .reg = CORE_CLK_CFG, + .mask = HCLK_PCLK_RATIO_MASK, + .shift = HCLK_PCLK_RATIO_SHIFT, +}; + +/* apb clock */ +static struct clk apb_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &ahb_clk, + .recalc = &bus_clk_recalc, + .private_data = &apb_config, +}; + +static struct clk_lookup apb_cl = { + .con_id = "apb_clk", + .clk = &apb_clk, +}; + +/* i2c clock */ +static struct clk i2c_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = I2C_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup i2c_cl = { + .dev_id = "i2c", + .clk = &i2c_clk, +}; + +/* dma clock */ +static struct clk dma_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = DMA_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup dma_cl = { + .dev_id = "dma", + .clk = &dma_clk, +}; + +/* jpeg clock */ +static struct clk jpeg_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = JPEG_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup jpeg_cl = { + .dev_id = "jpeg", + .clk = &jpeg_clk, +}; + +/* gmac clock */ +static struct clk gmac_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GMAC_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup gmac_cl = { + .dev_id = "gmac", + .clk = &gmac_clk, +}; + +/* smi clock */ +static struct clk smi_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SMI_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup smi_cl = { + .dev_id = "smi", + .clk = &smi_clk, +}; + +/* c3 clock */ +static struct clk c3_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = C3_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup c3_cl = { + .dev_id = "c3", + .clk = &c3_clk, +}; + +/* clock derived from apb clk */ +/* adc clock */ +static struct clk adc_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = ADC_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup adc_cl = { + .dev_id = "adc", + .clk = &adc_clk, +}; + +/* ssp clock */ +static struct clk ssp_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SSP_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup ssp_cl = { + .dev_id = "ssp", + .clk = &ssp_clk, +}; + +/* gpio clock */ +static struct clk gpio_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPIO_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup gpio_cl = { + .dev_id = "gpio", + .clk = &gpio_clk, +}; + +/* array of all spear 3xx clock lookups */ +static struct clk_lookup *spear_clk_lookups[] = { + /* root clks */ + &osc_32k_cl, + &osc_24m_cl, + + /* clock derived from 32 KHz osc clk */ + &rtc_cl, + + /* clock derived from 24 MHz osc clk */ + &pll1_cl, + &pll3_48m_cl, + &wdt_cl, + + /* clock derived from pll1 clk */ + &cpu_cl, + &ahb_cl, + &uart_cl, + &firda_cl, + &gpt0_cl, + &gpt1_cl, + &gpt2_cl, + + /* clock derived from pll3 clk */ + &usbh_cl, + &usbd_cl, + &clcd_cl, + + /* clock derived from ahb clk */ + &apb_cl, + &i2c_cl, + &dma_cl, + &jpeg_cl, + &gmac_cl, + &smi_cl, + &c3_cl, + + /* clock derived from apb clk */ + &adc_cl, + &ssp_cl, + &gpio_cl, +}; + +void __init clk_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) + clk_register(spear_clk_lookups[i]); + + recalc_root_clocks(); +} diff --git a/arch/arm/mach-spear3xx/include/mach/clkdev.h b/arch/arm/mach-spear3xx/include/mach/clkdev.h new file mode 100644 index 0000000..04b168b --- /dev/null +++ b/arch/arm/mach-spear3xx/include/mach/clkdev.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear3xx/include/mach/clkdev.h + * + * Clock Dev framework definitions for SPEAr3xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#include <plat/clkdev.h> + +#endif /* __ASM_MACH_CLKDEV_H */ diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c new file mode 100755 index 0000000..c33b847 --- /dev/null +++ b/arch/arm/mach-spear6xx/clock.c @@ -0,0 +1,656 @@ +/* + * arch/arm/mach-spear6xx/clock.c + * + * SPEAr6xx machines clock framework source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <mach/misc_regs.h> +#include <plat/clock.h> + +/* root clks */ +/* 32 KHz oscillator clock */ +static struct clk osc_32k_clk = { + .flags = ALWAYS_ENABLED, + .rate = 32 * KHZ, +}; + +static struct clk_lookup osc_32k_cl = { + .con_id = "osc_32k_clk", + .clk = &osc_32k_clk, +}; + +/* 30 MHz oscillator clock */ +static struct clk osc_30m_clk = { + .flags = ALWAYS_ENABLED, + .rate = 30 * MHZ, +}; + +static struct clk_lookup osc_30m_cl = { + .con_id = "osc_30m_clk", + .clk = &osc_30m_clk, +}; + +/* clock derived from 32 KHz osc clk */ +/* rtc clock */ +static struct clk rtc_clk = { + .pclk = &osc_32k_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = RTC_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup rtc_cl = { + .dev_id = "rtc", + .clk = &rtc_clk, +}; + +/* clock derived from 30 MHz osc clk */ +/* pll1 configuration structure */ +static struct pll_clk_config pll1_config = { + .mode_reg = PLL1_CTR, + .cfg_reg = PLL1_FRQ, +}; + +/* PLL1 clock */ +static struct clk pll1_clk = { + .pclk = &osc_30m_clk, + .en_reg = PLL1_CTR, + .en_reg_bit = PLL_ENABLE, + .recalc = &pll1_clk_recalc, + .private_data = &pll1_config, +}; + +static struct clk_lookup pll1_cl = { + .con_id = "pll1_clk", + .clk = &pll1_clk, +}; + +/* PLL3 48 MHz clock */ +static struct clk pll3_48m_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &osc_30m_clk, + .rate = 48 * MHZ, +}; + +static struct clk_lookup pll3_48m_cl = { + .con_id = "pll3_48m_clk", + .clk = &pll3_48m_clk, +}; + +/* watch dog timer clock */ +static struct clk wdt_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &osc_30m_clk, + .recalc = &follow_parent, +}; + +static struct clk_lookup wdt_cl = { + .dev_id = "wdt", + .clk = &wdt_clk, +}; + +/* clock derived from pll1 clk */ +/* cpu clock */ +static struct clk cpu_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .recalc = &follow_parent, +}; + +static struct clk_lookup cpu_cl = { + .con_id = "cpu_clk", + .clk = &cpu_clk, +}; + +/* ahb configuration structure */ +static struct bus_clk_config ahb_config = { + .reg = CORE_CLK_CFG, + .mask = PLL_HCLK_RATIO_MASK, + .shift = PLL_HCLK_RATIO_SHIFT, +}; + +/* ahb clock */ +static struct clk ahb_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .recalc = &bus_clk_recalc, + .private_data = &ahb_config, +}; + +static struct clk_lookup ahb_cl = { + .con_id = "ahb_clk", + .clk = &ahb_clk, +}; + +/* uart parents */ +static struct pclk_info uart_pclk_info[] = { + { + .pclk = &pll1_clk, + .pclk_mask = AUX_CLK_PLL1_MASK, + .scalable = 1, + }, { + .pclk = &pll3_48m_clk, + .pclk_mask = AUX_CLK_PLL3_MASK, + .scalable = 0, + }, +}; + +/* uart parent select structure */ +static struct pclk_sel uart_pclk_sel = { + .pclk_info = uart_pclk_info, + .pclk_count = ARRAY_SIZE(uart_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = UART_CLK_MASK, +}; + +/* uart configurations */ +static struct aux_clk_config uart_config = { + .synth_reg = UART_CLK_SYNT, +}; + +/* uart0 clock */ +static struct clk uart0_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = UART0_CLK_ENB, + .pclk_sel = &uart_pclk_sel, + .pclk_sel_shift = UART_CLK_SHIFT, + .recalc = &aux_clk_recalc, + .private_data = &uart_config, +}; + +static struct clk_lookup uart0_cl = { + .dev_id = "uart0", + .clk = &uart0_clk, +}; + +/* uart1 clock */ +static struct clk uart1_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = UART1_CLK_ENB, + .pclk_sel = &uart_pclk_sel, + .pclk_sel_shift = UART_CLK_SHIFT, + .recalc = &aux_clk_recalc, + .private_data = &uart_config, +}; + +static struct clk_lookup uart1_cl = { + .dev_id = "uart1", + .clk = &uart1_clk, +}; + +/* firda configurations */ +static struct aux_clk_config firda_config = { + .synth_reg = FIRDA_CLK_SYNT, +}; + +/* firda parents */ +static struct pclk_info firda_pclk_info[] = { + { + .pclk = &pll1_clk, + .pclk_mask = AUX_CLK_PLL1_MASK, + .scalable = 1, + }, { + .pclk = &pll3_48m_clk, + .pclk_mask = AUX_CLK_PLL3_MASK, + .scalable = 0, + }, +}; + +/* firda parent select structure */ +static struct pclk_sel firda_pclk_sel = { + .pclk_info = firda_pclk_info, + .pclk_count = ARRAY_SIZE(firda_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = FIRDA_CLK_MASK, +}; + +/* firda clock */ +static struct clk firda_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = FIRDA_CLK_ENB, + .pclk_sel = &firda_pclk_sel, + .pclk_sel_shift = FIRDA_CLK_SHIFT, + .recalc = &aux_clk_recalc, + .private_data = &firda_config, +}; + +static struct clk_lookup firda_cl = { + .dev_id = "firda", + .clk = &firda_clk, +}; + +/* clcd configurations */ +static struct aux_clk_config clcd_config = { + .synth_reg = CLCD_CLK_SYNT, +}; + +/* clcd parents */ +static struct pclk_info clcd_pclk_info[] = { + { + .pclk = &pll1_clk, + .pclk_mask = AUX_CLK_PLL1_MASK, + .scalable = 1, + }, { + .pclk = &pll3_48m_clk, + .pclk_mask = AUX_CLK_PLL3_MASK, + .scalable = 0, + }, +}; + +/* clcd parent select structure */ +static struct pclk_sel clcd_pclk_sel = { + .pclk_info = clcd_pclk_info, + .pclk_count = ARRAY_SIZE(clcd_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = CLCD_CLK_MASK, +}; + +/* clcd clock */ +static struct clk clcd_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = CLCD_CLK_ENB, + .pclk_sel = &clcd_pclk_sel, + .pclk_sel_shift = CLCD_CLK_SHIFT, + .recalc = &aux_clk_recalc, + .private_data = &clcd_config, +}; + +static struct clk_lookup clcd_cl = { + .dev_id = "clcd", + .clk = &clcd_clk, +}; + +/* gpt parents */ +static struct pclk_info gpt_pclk_info[] = { + { + .pclk = &pll1_clk, + .pclk_mask = AUX_CLK_PLL1_MASK, + .scalable = 1, + }, { + .pclk = &pll3_48m_clk, + .pclk_mask = AUX_CLK_PLL3_MASK, + .scalable = 0, + }, +}; + +/* gpt parent select structure */ +static struct pclk_sel gpt_pclk_sel = { + .pclk_info = gpt_pclk_info, + .pclk_count = ARRAY_SIZE(gpt_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = GPT_CLK_MASK, +}; + +/* gpt0_1 configurations */ +static struct aux_clk_config gpt0_1_config = { + .synth_reg = PRSC1_CLK_CFG, +}; + +/* gpt0 ARM1 subsystem timer clock */ +static struct clk gpt0_clk = { + .flags = ALWAYS_ENABLED, + .pclk_sel = &gpt_pclk_sel, + .pclk_sel_shift = GPT0_CLK_SHIFT, + .recalc = &gpt_clk_recalc, + .private_data = &gpt0_1_config, +}; + +static struct clk_lookup gpt0_cl = { + .dev_id = "gpt0", + .clk = &gpt0_clk, +}; + +/* gpt1 timer clock */ +static struct clk gpt1_clk = { + .flags = ALWAYS_ENABLED, + .pclk_sel = &gpt_pclk_sel, + .pclk_sel_shift = GPT1_CLK_SHIFT, + .recalc = &gpt_clk_recalc, + .private_data = &gpt0_1_config, +}; + +static struct clk_lookup gpt1_cl = { + .dev_id = "gpt1", + .clk = &gpt1_clk, +}; + +/* gpt2 configurations */ +static struct aux_clk_config gpt2_config = { + .synth_reg = PRSC2_CLK_CFG, +}; + +/* gpt2 timer clock */ +static struct clk gpt2_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPT2_CLK_ENB, + .pclk_sel = &gpt_pclk_sel, + .pclk_sel_shift = GPT2_CLK_SHIFT, + .recalc = &gpt_clk_recalc, + .private_data = &gpt2_config, +}; + +static struct clk_lookup gpt2_cl = { + .dev_id = "gpt2", + .clk = &gpt2_clk, +}; + +/* gpt3 configurations */ +static struct aux_clk_config gpt3_config = { + .synth_reg = PRSC3_CLK_CFG, +}; + +/* gpt3 timer clock */ +static struct clk gpt3_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPT3_CLK_ENB, + .pclk_sel = &gpt_pclk_sel, + .pclk_sel_shift = GPT3_CLK_SHIFT, + .recalc = &gpt_clk_recalc, + .private_data = &gpt3_config, +}; + +static struct clk_lookup gpt3_cl = { + .dev_id = "gpt3", + .clk = &gpt3_clk, +}; + +/* clock derived from pll3 clk */ +/* usbh0 clock */ +static struct clk usbh0_clk = { + .pclk = &pll3_48m_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = USBH0_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup usbh0_cl = { + .dev_id = "usbh0", + .clk = &usbh0_clk, +}; + +/* usbh1 clock */ +static struct clk usbh1_clk = { + .pclk = &pll3_48m_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = USBH1_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup usbh1_cl = { + .dev_id = "usbh1", + .clk = &usbh1_clk, +}; + +/* usbd clock */ +static struct clk usbd_clk = { + .pclk = &pll3_48m_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = USBD_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup usbd_cl = { + .dev_id = "usbd", + .clk = &usbd_clk, +}; + +/* clock derived from ahb clk */ +/* apb configuration structure */ +static struct bus_clk_config apb_config = { + .reg = CORE_CLK_CFG, + .mask = HCLK_PCLK_RATIO_MASK, + .shift = HCLK_PCLK_RATIO_SHIFT, +}; + +/* apb clock */ +static struct clk apb_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &ahb_clk, + .recalc = &bus_clk_recalc, + .private_data = &apb_config, +}; + +static struct clk_lookup apb_cl = { + .con_id = "apb_clk", + .clk = &apb_clk, +}; + +/* i2c clock */ +static struct clk i2c_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = I2C_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup i2c_cl = { + .dev_id = "i2c", + .clk = &i2c_clk, +}; + +/* dma clock */ +static struct clk dma_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = DMA_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup dma_cl = { + .dev_id = "dma", + .clk = &dma_clk, +}; + +/* jpeg clock */ +static struct clk jpeg_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = JPEG_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup jpeg_cl = { + .dev_id = "jpeg", + .clk = &jpeg_clk, +}; + +/* gmac clock */ +static struct clk gmac_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GMAC_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup gmac_cl = { + .dev_id = "gmac", + .clk = &gmac_clk, +}; + +/* smi clock */ +static struct clk smi_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SMI_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup smi_cl = { + .dev_id = "smi", + .clk = &smi_clk, +}; + +/* fsmc clock */ +static struct clk fsmc_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = FSMC_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup fsmc_cl = { + .dev_id = "fsmc", + .clk = &fsmc_clk, +}; + +/* clock derived from apb clk */ +/* adc clock */ +static struct clk adc_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = ADC_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup adc_cl = { + .dev_id = "adc", + .clk = &adc_clk, +}; + +/* ssp0 clock */ +static struct clk ssp0_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SSP0_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup ssp0_cl = { + .dev_id = "ssp0", + .clk = &ssp0_clk, +}; + +/* ssp1 clock */ +static struct clk ssp1_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SSP1_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup ssp1_cl = { + .dev_id = "ssp1", + .clk = &ssp1_clk, +}; + +/* ssp2 clock */ +static struct clk ssp2_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SSP2_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup ssp2_cl = { + .dev_id = "ssp2", + .clk = &ssp2_clk, +}; + +/* gpio0 ARM subsystem clock */ +static struct clk gpio0_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +static struct clk_lookup gpio0_cl = { + .dev_id = "gpio0", + .clk = &gpio0_clk, +}; + +/* gpio1 clock */ +static struct clk gpio1_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPIO1_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup gpio1_cl = { + .dev_id = "gpio1", + .clk = &gpio1_clk, +}; + +/* gpio2 clock */ +static struct clk gpio2_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPIO2_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk_lookup gpio2_cl = { + .dev_id = "gpio2", + .clk = &gpio2_clk, +}; + +/* array of all spear 6xx clock lookups */ +static struct clk_lookup *spear_clk_lookups[] = { + /* root clks */ + &osc_32k_cl, + &osc_30m_cl, + + /* clock derived from 32 KHz osc clk */ + &rtc_cl, + + /* clock derived from 30 MHz osc clk */ + &pll1_cl, + &pll3_48m_cl, + &wdt_cl, + + /* clock derived from pll1 clk */ + &cpu_cl, + &ahb_cl, + &uart0_cl, + &uart1_cl, + &firda_cl, + &clcd_cl, + &gpt0_cl, + &gpt1_cl, + &gpt2_cl, + &gpt3_cl, + + /* clock derived from pll3 clk */ + &usbh0_cl, + &usbh1_cl, + &usbd_cl, + + /* clock derived from ahb clk */ + &apb_cl, + &i2c_cl, + &dma_cl, + &jpeg_cl, + &gmac_cl, + &smi_cl, + &fsmc_cl, + + /* clock derived from apb clk */ + &adc_cl, + &ssp0_cl, + &ssp1_cl, + &ssp2_cl, + &gpio0_cl, + &gpio1_cl, + &gpio2_cl, +}; + +void __init clk_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) + clk_register(spear_clk_lookups[i]); + + recalc_root_clocks(); + + return 0; +} diff --git a/arch/arm/mach-spear6xx/include/mach/clkdev.h b/arch/arm/mach-spear6xx/include/mach/clkdev.h new file mode 100644 index 0000000..2fb7dbc --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/clkdev.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-spear6xx/include/mach/clkdev.h + * + * Clock Dev framework definitions for SPEAr6xx machine family + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#include <plat/clkdev.h> + +#endif /* __ASM_MACH_CLKDEV_H */ diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c new file mode 100755 index 0000000..bdcae0c --- /dev/null +++ b/arch/arm/plat-spear/clock.c @@ -0,0 +1,433 @@ +/* + * arch/arm/plat-spear/clock.c + * + * Clock framework for SPEAr platform + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/bug.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/spinlock.h> +#include <mach/misc_regs.h> +#include <plat/clock.h> + +static DEFINE_SPINLOCK(clocks_lock); +static LIST_HEAD(root_clks); + +static void propagate_rate(struct list_head *); + +static int generic_clk_enable(struct clk *clk) +{ + unsigned int val; + + if (!clk->en_reg) + return -EFAULT; + + val = readl(clk->en_reg); + if (unlikely(clk->flags & RESET_TO_ENABLE)) + val &= ~(1 << clk->en_reg_bit); + else + val |= 1 << clk->en_reg_bit; + + writel(val, clk->en_reg); + + return 0; +} + +static void generic_clk_disable(struct clk *clk) +{ + unsigned int val; + + if (!clk->en_reg) + return; + + val = readl(clk->en_reg); + if (unlikely(clk->flags & RESET_TO_ENABLE)) + val |= 1 << clk->en_reg_bit; + else + val &= ~(1 << clk->en_reg_bit); + + writel(val, clk->en_reg); +} + +/* generic clk ops */ +static struct clkops generic_clkops = { + .enable = generic_clk_enable, + .disable = generic_clk_disable, +}; + +/* + * clk_enable - inform the system when the clock source should be running. + * @clk: clock source + * + * If the clock can not be enabled/disabled, this should return success. + * + * Returns success (0) or negative errno. + */ +int clk_enable(struct clk *clk) +{ + unsigned long flags; + int ret = 0; + + if (!clk || IS_ERR(clk)) + return -EFAULT; + + spin_lock_irqsave(&clocks_lock, flags); + if (clk->usage_count++ == 0) { + if (clk->ops && clk->ops->enable) + ret = clk->ops->enable(clk); + } + spin_unlock_irqrestore(&clocks_lock, flags); + + return ret; +} +EXPORT_SYMBOL(clk_enable); + +/* + * clk_disable - inform the system when the clock source is no longer required. + * @clk: clock source + * + * Inform the system that a clock source is no longer required by + * a driver and may be shut down. + * + * Implementation detail: if the clock source is shared between + * multiple drivers, clk_enable() calls must be balanced by the + * same number of clk_disable() calls for the clock source to be + * disabled. + */ +void clk_disable(struct clk *clk) +{ + unsigned long flags; + + if (!clk || IS_ERR(clk)) + return; + + WARN_ON(clk->usage_count == 0); + + spin_lock_irqsave(&clocks_lock, flags); + if (--clk->usage_count == 0) { + if (clk->ops && clk->ops->disable) + clk->ops->disable(clk); + } + spin_unlock_irqrestore(&clocks_lock, flags); +} +EXPORT_SYMBOL(clk_disable); + +/** + * clk_get_rate - obtain the current clock rate (in Hz) for a clock source. + * This is only valid once the clock source has been enabled. + * @clk: clock source + */ +unsigned long clk_get_rate(struct clk *clk) +{ + unsigned long flags, rate; + + spin_lock_irqsave(&clocks_lock, flags); + rate = clk->rate; + spin_unlock_irqrestore(&clocks_lock, flags); + + return rate; +} +EXPORT_SYMBOL(clk_get_rate); + +/** + * clk_set_parent - set the parent clock source for this clock + * @clk: clock source + * @parent: parent clock source + * + * Returns success (0) or negative errno. + */ +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + int i, found = 0, val = 0; + unsigned long flags; + + if (!clk || IS_ERR(clk) || !parent || IS_ERR(parent)) + return -EFAULT; + if (clk->usage_count == 0) + return -EBUSY; + if (!clk->pclk_sel) + return -EPERM; + if (clk->pclk == parent) + return 0; + + for (i = 0; i < clk->pclk_sel->pclk_count; i++) { + if (clk->pclk_sel->pclk_info[i].pclk == parent) { + found = 1; + break; + } + } + + if (!found) + return -EPERM; + + spin_lock_irqsave(&clocks_lock, flags); + /* reflect parent change in hardware */ + val = readl(clk->pclk_sel->pclk_sel_reg); + val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift); + val |= clk->pclk_sel->pclk_info[i].pclk_mask << clk->pclk_sel_shift; + writel(val, clk->pclk_sel->pclk_sel_reg); + spin_unlock_irqrestore(&clocks_lock, flags); + + /* reflect parent change in software */ + clk->recalc(clk); + propagate_rate(&clk->children); + return 0; +} +EXPORT_SYMBOL(clk_set_parent); + +/* registers clock in platform clock framework */ +void clk_register(struct clk_lookup *cl) +{ + struct clk *clk = cl->clk; + unsigned long flags; + + if (!clk || IS_ERR(clk)) + return; + + spin_lock_irqsave(&clocks_lock, flags); + + INIT_LIST_HEAD(&clk->children); + if (clk->flags & ALWAYS_ENABLED) + clk->ops = NULL; + else if (!clk->ops) + clk->ops = &generic_clkops; + + /* root clock don't have any parents */ + if (!clk->pclk && !clk->pclk_sel) { + list_add(&clk->sibling, &root_clks); + /* add clocks with only one parent to parent's children list */ + } else if (clk->pclk && !clk->pclk_sel) { + list_add(&clk->sibling, &clk->pclk->children); + } else { + /* add clocks with > 1 parent to 1st parent's children list */ + list_add(&clk->sibling, + &clk->pclk_sel->pclk_info[0].pclk->children); + } + spin_unlock_irqrestore(&clocks_lock, flags); + + /* add clock to arm clockdev framework */ + clkdev_add(cl); +} + +/** + * propagate_rate - recalculate and propagate all clocks in list head + * + * Recalculates all root clocks in list head, which if the clock's .recalc is + * set correctly, should also propagate their rates. + */ +static void propagate_rate(struct list_head *lhead) +{ + struct clk *clkp, *_temp; + + list_for_each_entry_safe(clkp, _temp, lhead, sibling) { + if (clkp->recalc) + clkp->recalc(clkp); + propagate_rate(&clkp->children); + } +} + +/* returns current programmed clocks clock info structure */ +static struct pclk_info *pclk_info_get(struct clk *clk) +{ + unsigned int mask, i; + unsigned long flags; + struct pclk_info *info; + + spin_lock_irqsave(&clocks_lock, flags); + mask = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift) + & clk->pclk_sel->pclk_sel_mask; + + for (i = 0; i < clk->pclk_sel->pclk_count; i++) { + if (clk->pclk_sel->pclk_info[i].pclk_mask == mask) + info = &clk->pclk_sel->pclk_info[i]; + } + spin_unlock_irqrestore(&clocks_lock, flags); + + return info; +} + +/* + * Set pclk as cclk's parent and add clock sibling node to current parents + * children list + */ +static void change_parent(struct clk *cclk, struct clk *pclk) +{ + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + list_del(&cclk->sibling); + list_add(&cclk->sibling, &pclk->children); + + cclk->pclk = pclk; + spin_unlock_irqrestore(&clocks_lock, flags); +} + +/* + * calculates current programmed rate of pll1 + * + * In normal mode + * rate = (2 * M[15:8] * Fin)/(N * 2^P) + * + * In Dithered mode + * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P) + */ +void pll1_clk_recalc(struct clk *clk) +{ + struct pll_clk_config *config = clk->private_data; + unsigned int num = 2, den = 0, val, mode = 0; + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + mode = (readl(config->mode_reg) >> PLL_MODE_SHIFT) & + PLL_MODE_MASK; + + val = readl(config->cfg_reg); + /* calculate denominator */ + den = (val >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK; + den = 1 << den; + den *= (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK; + + /* calculate numerator & denominator */ + if (!mode) { + /* Normal mode */ + num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK; + } else { + /* Dithered mode */ + num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK; + den *= 256; + } + + clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000; + spin_unlock_irqrestore(&clocks_lock, flags); +} + +/* calculates current programmed rate of ahb or apb bus */ +void bus_clk_recalc(struct clk *clk) +{ + struct bus_clk_config *config = clk->private_data; + unsigned int div; + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + div = ((readl(config->reg) >> config->shift) & config->mask) + 1; + clk->rate = (unsigned long)clk->pclk->rate / div; + spin_unlock_irqrestore(&clocks_lock, flags); +} + +/* + * calculates current programmed rate of auxiliary synthesizers + * used by: UART, FIRDA + * + * Fout from synthesizer can be given from two equations: + * Fout1 = (Fin * X/Y)/2 + * Fout2 = Fin * X/Y + * + * Selection of eqn 1 or 2 is programmed in register + */ +void aux_clk_recalc(struct clk *clk) +{ + struct aux_clk_config *config = clk->private_data; + struct pclk_info *pclk_info = NULL; + unsigned int num = 1, den = 1, val, eqn; + unsigned long flags; + + /* get current programmed parent */ + pclk_info = pclk_info_get(clk); + if (!pclk_info) { + spin_lock_irqsave(&clocks_lock, flags); + clk->pclk = NULL; + clk->rate = 0; + spin_unlock_irqrestore(&clocks_lock, flags); + return; + } + + change_parent(clk, pclk_info->pclk); + + spin_lock_irqsave(&clocks_lock, flags); + if (pclk_info->scalable) { + val = readl(config->synth_reg); + + eqn = (val >> AUX_EQ_SEL_SHIFT) & AUX_EQ_SEL_MASK; + if (eqn == AUX_EQ1_SEL) + den *= 2; + + /* calculate numerator */ + num = (val >> AUX_XSCALE_SHIFT) & AUX_XSCALE_MASK; + + /* calculate denominator */ + den *= (val >> AUX_YSCALE_SHIFT) & AUX_YSCALE_MASK; + val = (((clk->pclk->rate/10000) * num) / den) * 10000; + } else + val = clk->pclk->rate; + + clk->rate = val; + spin_unlock_irqrestore(&clocks_lock, flags); +} + +/* + * calculates current programmed rate of gpt synthesizers + * Fout from synthesizer can be given from below equations: + * Fout= Fin/((2 ^ (N+1)) * (M+1)) + */ +void gpt_clk_recalc(struct clk *clk) +{ + struct aux_clk_config *config = clk->private_data; + struct pclk_info *pclk_info = NULL; + unsigned int div = 1, val; + unsigned long flags; + + pclk_info = pclk_info_get(clk); + if (!pclk_info) { + spin_lock_irqsave(&clocks_lock, flags); + clk->pclk = NULL; + clk->rate = 0; + spin_unlock_irqrestore(&clocks_lock, flags); + return; + } + + change_parent(clk, pclk_info->pclk); + + spin_lock_irqsave(&clocks_lock, flags); + if (pclk_info->scalable) { + val = readl(config->synth_reg); + div += (val >> GPT_MSCALE_SHIFT) & GPT_MSCALE_MASK; + div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1); + } + + clk->rate = (unsigned long)clk->pclk->rate / div; + spin_unlock_irqrestore(&clocks_lock, flags); +} + +/* + * Used for clocks that always have same value as the parent clock divided by a + * fixed divisor + */ +void follow_parent(struct clk *clk) +{ + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + clk->rate = clk->pclk->rate; + spin_unlock_irqrestore(&clocks_lock, flags); +} + +/** + * recalc_root_clocks - recalculate and propagate all root clocks + * + * Recalculates all root clocks (clocks with no parent), which if the + * clock's .recalc is set correctly, should also propagate their rates. + */ +void recalc_root_clocks(void) +{ + propagate_rate(&root_clks); +} diff --git a/arch/arm/plat-spear/include/plat/clkdev.h b/arch/arm/plat-spear/include/plat/clkdev.h new file mode 100644 index 0000000..9b1cd54 --- /dev/null +++ b/arch/arm/plat-spear/include/plat/clkdev.h @@ -0,0 +1,20 @@ +/* + * arch/arm/plat-spear/include/plat/clkdev.h + * + * Clock Dev framework definitions for SPEAr platform + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_PLAT_CLKDEV_H +#define __ASM_PLAT_CLKDEV_H + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +#endif /* __ASM_PLAT_CLKDEV_H */ diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h new file mode 100755 index 0000000..c220274 --- /dev/null +++ b/arch/arm/plat-spear/include/plat/clock.h @@ -0,0 +1,130 @@ +/* + * arch/arm/plat-spear/include/plat/clock.h + * + * Clock framework definitions for SPEAr platform + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_PLAT_CLOCK_H +#define __ASM_PLAT_CLOCK_H + +#include <linux/list.h> +#include <asm/clkdev.h> +#include <linux/types.h> + +/* clk values */ +#define KHZ (1000) +#define MHZ (1000000) + +/* clk structure flags */ +#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */ +#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */ + +/** + * struct clkops - clock operations + * @enable: pointer to clock enable function + * @disable: pointer to clock disable function + */ +struct clkops { + int (*enable) (struct clk *); + void (*disable) (struct clk *); +}; + +/** + * struct pclk_info - parents info + * @pclk: pointer to parent clk + * @pclk_mask: value to be written for selecting this parent + * @scalable: Is parent scalable (1 - YES, 0 - NO) + */ +struct pclk_info { + struct clk *pclk; + u8 pclk_mask; + u8 scalable; +}; + +/** + * struct pclk_sel - parents selection configuration + * @pclk_info: pointer to array of parent clock info + * @pclk_count: number of parents + * @pclk_sel_reg: register for selecting a parent + * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also) + */ +struct pclk_sel { + struct pclk_info *pclk_info; + u8 pclk_count; + unsigned int *pclk_sel_reg; + unsigned int pclk_sel_mask; +}; + +/** + * struct clk - clock structure + * @usage_count: num of users who enabled this clock + * @flags: flags for clock properties + * @rate: programmed clock rate in Hz + * @en_reg: clk enable/disable reg + * @en_reg_bit: clk enable/disable bit + * @ops: clk enable/disable ops - generic_clkops selected if NULL + * @recalc: pointer to clock rate recalculate function + * @pclk: current parent clk + * @pclk_sel: pointer to parent selection structure + * @pclk_sel_shift: register shift for selecting parent of this clock + * @children: list for childrens or this clock + * @sibling: node for list of clocks having same parents + * @private_data: clock specific private data + */ +struct clk { + unsigned int usage_count; + unsigned int flags; + unsigned long rate; + unsigned int *en_reg; + u8 en_reg_bit; + const struct clkops *ops; + void (*recalc) (struct clk *); + + struct clk *pclk; + struct pclk_sel *pclk_sel; + unsigned int pclk_sel_shift; + + struct list_head children; + struct list_head sibling; + void *private_data; +}; + +/* pll configuration structure */ +struct pll_clk_config { + unsigned int *mode_reg; + unsigned int *cfg_reg; +}; + +/* ahb and apb bus configuration structure */ +struct bus_clk_config { + unsigned int *reg; + unsigned int mask; + unsigned int shift; +}; + +/* + * Aux clk configuration structure: applicable to GPT, UART and FIRDA + */ +struct aux_clk_config { + unsigned int *synth_reg; +}; + +/* platform specific clock functions */ +void clk_register(struct clk_lookup *cl); +void recalc_root_clocks(void); + +/* clock recalc functions */ +void follow_parent(struct clk *clk); +void pll1_clk_recalc(struct clk *clk); +void bus_clk_recalc(struct clk *clk); +void gpt_clk_recalc(struct clk *clk); +void aux_clk_recalc(struct clk *clk); + +#endif /* __ASM_PLAT_CLOCK_H */ -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH 06/11] ST SPEAr: Added source files for SPEAr platform 2010-03-03 5:07 ` [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines Viresh KUMAR @ 2010-03-03 5:07 ` Viresh KUMAR 2010-03-03 5:07 ` [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family Viresh KUMAR 2010-03-11 11:22 ` [PATCH 06/11] ST SPEAr: Added source files for SPEAr platform Linus Walleij 2010-03-11 7:00 ` [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines Linus Walleij 2010-03-11 10:28 ` Russell King - ARM Linux 2 siblings, 2 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-03 5:07 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Viresh Kumar <viresh.kumar@st.com> --- arch/arm/plat-spear/Kconfig | 31 +++ arch/arm/plat-spear/Makefile | 6 + arch/arm/plat-spear/gpt.c | 537 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/plat-spear/time.c | 197 +++++++++++++++ 4 files changed, 771 insertions(+), 0 deletions(-) create mode 100644 arch/arm/plat-spear/Kconfig create mode 100644 arch/arm/plat-spear/Makefile create mode 100644 arch/arm/plat-spear/gpt.c create mode 100644 arch/arm/plat-spear/time.c diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig new file mode 100644 index 0000000..1bb3dbc --- /dev/null +++ b/arch/arm/plat-spear/Kconfig @@ -0,0 +1,31 @@ +# +# SPEAr Platform configuration file +# + +if PLAT_SPEAR + +choice + prompt "ST SPEAr Family" + default ARCH_SPEAR3XX + +config ARCH_SPEAR3XX + bool "SPEAr3XX" + select ARM_VIC + select CPU_ARM926T + help + Supports for ARM's SPEAR3XX family + +config ARCH_SPEAR6XX + bool "SPEAr6XX" + select ARM_VIC + select CPU_ARM926T + help + Supports for ARM's SPEAR6XX family + +endchoice + +# Adding SPEAr machine specific configuration files +source "arch/arm/mach-spear3xx/Kconfig" +source "arch/arm/mach-spear6xx/Kconfig" + +endif diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile new file mode 100644 index 0000000..4412f05 --- /dev/null +++ b/arch/arm/plat-spear/Makefile @@ -0,0 +1,6 @@ +# +# SPEAr Platform specific Makefile +# + +# Common support +obj-y := clock.o gpt.o time.o diff --git a/arch/arm/plat-spear/gpt.c b/arch/arm/plat-spear/gpt.c new file mode 100644 index 0000000..3b16360 --- /dev/null +++ b/arch/arm/plat-spear/gpt.c @@ -0,0 +1,537 @@ +/* + * arch/arm/plat-spear/gpt.c + * + * ST GPT Timer driver, based on omap's dmtimer.c + * + * Copyright (C) 2009 ST Microelectronics + * Shiraz Hashim<shiraz.hashim@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/clk.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/spinlock.h> +#include <mach/irqs.h> +#include <mach/spear.h> +#include <plat/gpt.h> + +static const char *src_clk_con_id[] __initdata = { + "pll3_48m_clk", + "pll1_clk", + NULL +}; + +static struct clk *spear_source_clocks[2]; +static struct spear_timer *spear_timers; +static int spear_timer_count; +static spinlock_t spear_timer_lock; + +/* + * static helper functions + */ +static inline u16 spear_timer_read_reg(struct spear_timer *timer, u32 reg) +{ + return readw(timer->io_base + (reg & 0xff)); +} + +static inline void spear_timer_write_reg(struct spear_timer *timer, u32 reg, + u16 value) +{ + writew(value, timer->io_base + (reg & 0xff)); +} + +static void spear_timer_reset(struct spear_timer *timer) +{ + + spear_timer_write_reg(timer, GPT_CTRL_OFF, 0x0); + spear_timer_write_reg(timer, GPT_LOAD_OFF, 0x0); + spear_timer_write_reg(timer, GPT_INT_OFF, GPT_STATUS_MATCH); + timer->prescaler = 0; +} + +static void spear_timer_prepare(struct spear_timer *timer) +{ + spear_timer_enable(timer); + spear_timer_reset(timer); +} + +/* functions exported for application */ + +/** + * spear_timer_enable - enable a timer + * @timer: timer + * + * This API enables the functional clock of the timer + */ +int spear_timer_enable(struct spear_timer *timer) +{ + if (!timer) + return -ENODEV; + + if (timer->enabled) + return -EINVAL; + + clk_enable(timer->fclk); + + timer->enabled = 1; + + return 0; +} + +/** + * spear_timer_disable - disables timer + * @timer: timer + * + * The API disables the functional clock of the timer + */ +int spear_timer_disable(struct spear_timer *timer) +{ + if (!timer) + return -ENODEV; + + if (!timer->enabled) + return -EINVAL; + + clk_disable(timer->fclk); + + timer->enabled = 0; + + return 0; +} + +/** + * spear_timer_request - request for a timer + * + * This API returns a timer which is available, returns NULL if none is + * available + */ +struct spear_timer *spear_timer_request(void) +{ + struct spear_timer *timer = NULL; + unsigned long flags; + int i; + + spin_lock_irqsave(&spear_timer_lock, flags); + + for (i = 0; i < spear_timer_count; i++) { + if (spear_timers[i].reserved) + continue; + + timer = &spear_timers[i]; + timer->reserved = 1; + break; + } + + spin_unlock_irqrestore(&spear_timer_lock, flags); + + if (timer != NULL) + spear_timer_prepare(timer); + + return timer; +} +EXPORT_SYMBOL(spear_timer_request); + +/** + * spear_timer_request_specific - request for a specific timer + * @id: timer id requested, 1 onwards + * + * This API returns specific timer which is requested, returns NULL if it is + * not available. + */ +struct spear_timer *spear_timer_request_specific(int id) +{ + struct spear_timer *timer; + unsigned long flags; + + spin_lock_irqsave(&spear_timer_lock, flags); + + if (id < 0 || id >= spear_timer_count || + spear_timers[id].reserved) { + spin_unlock_irqrestore(&spear_timer_lock, flags); + printk(KERN_ERR "BUG: unable to get timer %d\n", id); + dump_stack(); + return NULL; + } + + timer = &spear_timers[id]; + timer->reserved = 1; + spin_unlock_irqrestore(&spear_timer_lock, flags); + + spear_timer_prepare(timer); + + return timer; +} +EXPORT_SYMBOL(spear_timer_request_specific); + +/** + * spear_timer_free - free the timer + * @timer: timer which should be freed + * + * Applications should free the timer when not in use. The API also resets and + * disables the timer clock + */ +int spear_timer_free(struct spear_timer *timer) +{ + if (!timer) + return -ENODEV; + + WARN_ON(!timer->reserved); + + spear_timer_reset(timer); + spear_timer_disable(timer); + + timer->reserved = 0; + + return 0; +} +EXPORT_SYMBOL(spear_timer_free); + +/** + * spear_timer_get_irq - get the irq number associated + * @timer: return the irq number for this timer + * + * The application may require the irq associated with a timer to register it + * with the OS interrupt framework. + */ +int spear_timer_get_irq(struct spear_timer *timer) +{ + return (timer) ? timer->irq : -ENODEV; +} +EXPORT_SYMBOL(spear_timer_get_irq); + +/** + * spear_timer_get_fclk - return the functional clock + * @timer: timer for which fclk is required + * + * Returns the functional clock of the timer at which it is operating. + * Functional clock represents the actual clock at which the timer is + * operating. The count period depends on this clock + */ +struct clk *spear_timer_get_fclk(struct spear_timer *timer) +{ + if (!timer) + return NULL; + + return timer->fclk; +} +EXPORT_SYMBOL(spear_timer_get_fclk); + +/** + * spear_timer_start - start the timer operation + * @timer: timer to start + * + * The timer shall start operating only after calling this API + */ +int spear_timer_start(struct spear_timer *timer) +{ + u16 val; + + if (!timer) + return -ENODEV; + + val = spear_timer_read_reg(timer, GPT_CTRL_OFF); + if (!(val & GPT_CTRL_ENABLE)) { + val |= GPT_CTRL_ENABLE; + spear_timer_write_reg(timer, GPT_CTRL_OFF, val); + } + + return 0; +} +EXPORT_SYMBOL(spear_timer_start); + +/** + * spear_timer_stop - stop the timer operation + * @timer: timer to stop + * + * This API can be used to stop the timer operation + */ +int spear_timer_stop(struct spear_timer *timer) +{ + u16 val; + + if (!timer) + return -ENODEV; + + val = spear_timer_read_reg(timer, GPT_CTRL_OFF); + if (val & GPT_CTRL_ENABLE) { + val &= ~GPT_CTRL_ENABLE; + spear_timer_write_reg(timer, GPT_CTRL_OFF, val); + } + + return 0; +} +EXPORT_SYMBOL(spear_timer_stop); + +/** + * spear_timer_set_source - select the proper source clock + * @timer: timer + * @source: the clock cource + * + * source specifies the clock which has to be selected as the functional clock + * of timer. The available choice are 48 MHz (PLL3) output or AHB clock. + * + */ +int spear_timer_set_source(struct spear_timer *timer, int source) +{ + if (source < 0 || source >= 3) + return -EINVAL; + + if (!timer) + return -ENODEV; + + clk_disable(timer->fclk); + clk_set_parent(timer->fclk, spear_source_clocks[source]); + clk_enable(timer->fclk); + return 0; +} +EXPORT_SYMBOL(spear_timer_set_source); + +/** + * spear_timer_set_load - program the count value of timer + * @timer: timer + * @autoreload: boolean, whether the count will be reloaded + * @load: the actual count deciding the time period + * + * The timer will be programmed as per the value in load. The time period will + * depend on the clock and prescaler selected. + */ +int spear_timer_set_load(struct spear_timer *timer, int autoreload, + u16 load) +{ + u16 val; + + if (!timer) + return -ENODEV; + + val = spear_timer_read_reg(timer, GPT_CTRL_OFF); + if (autoreload) + val &= ~GPT_CTRL_MODE_AR; + else + val |= GPT_CTRL_MODE_AR; + + spear_timer_write_reg(timer, GPT_LOAD_OFF, load); + spear_timer_write_reg(timer, GPT_CTRL_OFF, val); + + return 0; +} +EXPORT_SYMBOL(spear_timer_set_load); + +/** + * spear_timer_set_load_start - program the count value of timer and start + * @timer: timer + * @autoreload: boolean, whether the count will be reloaded + * @load: the actual count deciding the time period + * + * The timer will be programmed as per the value in load and the operation will + * be started. + */ +int spear_timer_set_load_start(struct spear_timer *timer, int autoreload, + u16 load) +{ + u16 val; + + if (!timer) + return -ENODEV; + + val = spear_timer_read_reg(timer, GPT_CTRL_OFF); + if (autoreload) + val &= ~GPT_CTRL_MODE_AR; + else + val |= GPT_CTRL_MODE_AR; + + val |= GPT_CTRL_ENABLE; + + spear_timer_write_reg(timer, GPT_LOAD_OFF, load); + spear_timer_write_reg(timer, GPT_CTRL_OFF, val); + + return 0; +} +EXPORT_SYMBOL(spear_timer_set_load_start); + +/** + * spear_timer_match_irq - enable the match interrupt + * @timer: timer + * @enable: boolean, 1 for enable + * + * If application wants to enable the interrupt on count match then this API + * should be called + */ +int spear_timer_match_irq(struct spear_timer *timer, int enable) +{ + u16 val; + + if (!timer) + return -ENODEV; + + val = spear_timer_read_reg(timer, GPT_CTRL_OFF); + if (enable) + val |= GPT_CTRL_MATCH_INT; + else + val &= ~GPT_CTRL_MATCH_INT; + spear_timer_write_reg(timer, GPT_CTRL_OFF, val); + + return 0; +} +EXPORT_SYMBOL(spear_timer_match_irq); + +/** + * spear_timer_set_prescaler - set the prescaler for the timer + * @timer: timer + * @prescaler: the division factor to be applied on the src clk + * + * This API can be used to program the prescaler for the timer. Its value can + * be from 1 to 8 signifying division by 2^prescaler + */ +int spear_timer_set_prescaler(struct spear_timer *timer, int prescaler) +{ + u16 val; + + if (!timer) + return -ENODEV; + + val = spear_timer_read_reg(timer, GPT_CTRL_OFF); + if (prescaler >= 0x00 && prescaler <= 0x08) { + val &= 0xFFF0; + val |= prescaler; + } else { + printk(KERN_ERR "Invalid prescaler\n"); + } + + timer->prescaler = val & 0xF; + spear_timer_write_reg(timer, GPT_CTRL_OFF, val); + return 0; +} +EXPORT_SYMBOL(spear_timer_set_prescaler); + +/** + * spear_timer_read_status - read the interrupt status + * @timer: timer + * + * This API can be used to read the interrupt status of timer. Currently only + * match interrupt, at offset 0, is part of this. + */ +int spear_timer_read_status(struct spear_timer *timer) +{ + u16 val; + + if (!timer) + return -ENODEV; + + val = spear_timer_read_reg(timer, GPT_INT_OFF); + + return val; +} +EXPORT_SYMBOL(spear_timer_read_status); + +/** + * spear_timer_clear_status - write to the interrupt status reg to clear + * @timer: timer + * @value: value to be written + * + * The API can be used to clear the match interrupt status by writing a value + * 0. + */ +int spear_timer_clear_status(struct spear_timer *timer, u16 value) +{ + if (!timer) + return -ENODEV; + + spear_timer_write_reg(timer, GPT_INT_OFF, value); + return 0; +} +EXPORT_SYMBOL(spear_timer_clear_status); + +/** + * spear_timer_read_counter - get the current count value + * @timer: timer + * + * The API returns the current count value of the timer. One has to remember + * that if the timer is operating on asynchronous clock source then there is a + * probability that the application may get some junk count value. This is due + * to the fact that the count register is being accessed by two independent + * clock, one driving the timer (48MHz) and the other on which this register is + * read (system AHB clock). For more details refer GPT Application note. + */ +int spear_timer_read_counter(struct spear_timer *timer) +{ + u16 val; + + if (!timer) + return -ENODEV; + + val = spear_timer_read_reg(timer, GPT_COUNT_OFF); + + return val; +} +EXPORT_SYMBOL(spear_timer_read_counter); + +/** + * spear_timer_active - is timer active + * @timer: timer + * + * This API can be used to find whether a timer is already enabled and is + * active i.e. it is under operation + */ +int spear_timer_active(struct spear_timer *timer) +{ + if (!timer) + return 0; + + if (!timer->enabled) + return 0; + + if (spear_timer_read_reg(timer, GPT_CTRL_OFF) & GPT_CTRL_ENABLE) + return 1; + + return 0; +} +EXPORT_SYMBOL(spear_timer_active); + +/** + * spear_timer_init - initialize the set of timers + * @timer: list of timers to be intialized + * @count: number of timers supported in platform + * + * This API must not be called by user and it is called only once by the + * platform specific intialization code. + */ +int __init spear_timer_init(struct spear_timer *timers, int count) +{ + struct spear_timer *timer; + int i; + int mtu; /* timer unit */ + char dev_id[16]; + + spin_lock_init(&spear_timer_lock); + + spear_timers = timers; + spear_timer_count = count; + + for (i = 0; src_clk_con_id[i] != NULL; i++) + spear_source_clocks[i] = clk_get(NULL, src_clk_con_id[i]); + + for (i = 0; i < spear_timer_count; i++) { + timer = &spear_timers[i]; + timer->io_base = (void __iomem *)ioremap(timer->phys_base, + SZ_1K); + if (!timer->io_base) { + printk(KERN_ERR "BUG:ioremap failed for timer:%d\n", i); + continue; + } + + /* each mtu has 2 timers with same set of clocks */ + mtu = i >> 1; + + sprintf(dev_id, "gpt%d", mtu); + timer->fclk = clk_get_sys(dev_id, NULL); + } + + return 0; +} diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c new file mode 100644 index 0000000..d89ac17 --- /dev/null +++ b/arch/arm/plat-spear/time.c @@ -0,0 +1,197 @@ +/* + * arch/arm/plat-spear/time.c + * + * Copyright (C) 2009 ST Microelectronics + * Shiraz Hashim<shiraz.hashim@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/clk.h> +#include <linux/clockchips.h> +#include <linux/clocksource.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/time.h> +#include <linux/irq.h> +#include <asm/mach/time.h> +#include <mach/irqs.h> +#include <mach/hardware.h> +#include <mach/spear.h> +#include <mach/generic.h> +#include <plat/gpt.h> + +static void clockevent_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk_event_dev); +static int clockevent_next_event(unsigned long evt, + struct clock_event_device *clk_event_dev); + +/* + * Timer0 and Timer1 both belong to same mtu in cpu subbsystem. Further they + * share same functional clock. Any change in one's functional clock will also + * affect other timer. + */ +static struct spear_timer *spear_timer_clkevt; +static struct spear_timer *spear_timer_clksrc; + +/* + * Clock Source + */ +static cycle_t clocksource_read_cycles(struct clocksource *cs) +{ + return (cycle_t) spear_timer_read_counter(spear_timer_clksrc); +} + +static struct clocksource clksrc = { + .name = "clock source", + .rating = 200, /* its a pretty decent clock */ + .read = clocksource_read_cycles, + .mask = 0xFFFF, /* 16 bits */ + .mult = 0, /* to be computed */ + .shift = 10, + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void spear_clocksource_init(void) +{ + static struct spear_timer *timer; + u32 tick_rate; + + timer = spear_timer_request_specific(1); + BUG_ON(timer == NULL); + spear_timer_clksrc = timer; + + spear_timer_set_source(timer, SPEAR_TIMER_SRC_PLL3_CLK); + spear_timer_set_prescaler(timer, GPT_CTRL_PRESCALER256); + + /* find out actual clock driving Timer */ + tick_rate = clk_get_rate(spear_timer_get_fclk(timer)); + tick_rate >>= timer->prescaler; + + spear_timer_set_load_start(timer, 1, 0xFFFF); /* 16 bit maximum */ + + clksrc.mult = + clocksource_khz2mult((tick_rate / 1000), clksrc.shift); + + /* register the clocksource */ + clocksource_register(&clksrc); +} + +/* +* Clock Event +*/ +static struct clock_event_device clkevt = { + .name = "clock_event", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .set_mode = clockevent_set_mode, + .set_next_event = clockevent_next_event, + .shift = 20, +}; + +static void clockevent_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk_event_dev) +{ + u32 period; + struct spear_timer *timer = spear_timer_clkevt; + + if (timer) + return; + + spear_timer_stop(timer); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + period = clk_get_rate(spear_timer_get_fclk(timer)) / HZ; + period >>= timer->prescaler; + + spear_timer_match_irq(timer, 1); + spear_timer_set_load_start(timer, 1, period); + break; + + case CLOCK_EVT_MODE_ONESHOT: + spear_timer_match_irq(timer, 1); + break; + + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_RESUME: + break; + + default: + printk(KERN_ERR "BUG: Invalid mode requested\n"); + break; + } +} + +static int clockevent_next_event(unsigned long cycles, + struct clock_event_device *clk_event_dev) +{ + spear_timer_set_load_start(spear_timer_clkevt, 0, (u16) cycles); + + return 0; +} + +static irqreturn_t spear_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = &clkevt; + struct spear_timer *timer = (struct spear_timer *)dev_id; + + spear_timer_clear_status(timer, GPT_STATUS_MATCH); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction spear_timer_irq = { + .name = "gp_timer", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = spear_timer_interrupt +}; + +static void __init spear_clockevent_init(void) +{ + struct spear_timer *timer; + u32 tick_rate; + + timer = spear_timer_request_specific(0); + BUG_ON(timer == NULL); + spear_timer_clkevt = timer; + + spear_timer_set_source(timer, SPEAR_TIMER_SRC_PLL3_CLK); + spear_timer_set_prescaler(timer, GPT_CTRL_PRESCALER16); + + tick_rate = clk_get_rate(spear_timer_get_fclk(timer)); + tick_rate >>= timer->prescaler; + + clkevt.mult = div_sc(tick_rate, NSEC_PER_SEC, + clkevt.shift); + clkevt.max_delta_ns = clockevent_delta2ns(0xfff0, + &clkevt); + clkevt.min_delta_ns = clockevent_delta2ns(3, &clkevt); + + clkevt.cpumask = cpumask_of(0); + clockevents_register_device(&clkevt); + + spear_timer_irq.dev_id = (void *)timer; + + setup_irq(spear_timer_get_irq(timer), &spear_timer_irq); + spear_timer_match_irq(timer, 1); +} + +void __init spear_setup_timer(void) +{ + /* Initialize all General Purpose Timers */ + spear_gpt_init(); + + spear_clockevent_init(); + spear_clocksource_init(); +} + +struct sys_timer spear_sys_timer = { + .init = spear_setup_timer, +}; -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family 2010-03-03 5:07 ` [PATCH 06/11] ST SPEAr: Added source files for SPEAr platform Viresh KUMAR @ 2010-03-03 5:07 ` Viresh KUMAR 2010-03-03 5:07 ` [PATCH 08/11] ST SPEAr: Added source files for SPEAr6xx " Viresh KUMAR 2010-03-09 6:46 ` [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family Linus Walleij 2010-03-11 11:22 ` [PATCH 06/11] ST SPEAr: Added source files for SPEAr platform Linus Walleij 1 sibling, 2 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-03 5:07 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Viresh Kumar <viresh.kumar@st.com> --- arch/arm/mach-spear3xx/Kconfig | 33 +++++++++ arch/arm/mach-spear3xx/Kconfig300 | 17 +++++ arch/arm/mach-spear3xx/Kconfig310 | 17 +++++ arch/arm/mach-spear3xx/Kconfig320 | 17 +++++ arch/arm/mach-spear3xx/Makefile | 26 +++++++ arch/arm/mach-spear3xx/Makefile.boot | 3 + arch/arm/mach-spear3xx/spear300.c | 23 +++++++ arch/arm/mach-spear3xx/spear300_evb.c | 47 +++++++++++++ arch/arm/mach-spear3xx/spear310.c | 23 +++++++ arch/arm/mach-spear3xx/spear310_evb.c | 47 +++++++++++++ arch/arm/mach-spear3xx/spear320.c | 23 +++++++ arch/arm/mach-spear3xx/spear320_evb.c | 47 +++++++++++++ arch/arm/mach-spear3xx/spear3xx.c | 118 +++++++++++++++++++++++++++++++++ 13 files changed, 441 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-spear3xx/Kconfig create mode 100644 arch/arm/mach-spear3xx/Kconfig300 create mode 100644 arch/arm/mach-spear3xx/Kconfig310 create mode 100644 arch/arm/mach-spear3xx/Kconfig320 create mode 100644 arch/arm/mach-spear3xx/Makefile create mode 100644 arch/arm/mach-spear3xx/Makefile.boot create mode 100644 arch/arm/mach-spear3xx/spear300.c create mode 100644 arch/arm/mach-spear3xx/spear300_evb.c create mode 100644 arch/arm/mach-spear3xx/spear310.c create mode 100644 arch/arm/mach-spear3xx/spear310_evb.c create mode 100644 arch/arm/mach-spear3xx/spear320.c create mode 100644 arch/arm/mach-spear3xx/spear320_evb.c create mode 100644 arch/arm/mach-spear3xx/spear3xx.c diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig new file mode 100644 index 0000000..20d1317 --- /dev/null +++ b/arch/arm/mach-spear3xx/Kconfig @@ -0,0 +1,33 @@ +# +# SPEAr3XX Machine configuration file +# + +if ARCH_SPEAR3XX + +choice + prompt "SPEAr3XX Family" + default MACH_SPEAR300 + +config MACH_SPEAR300 + bool "SPEAr300" + help + Supports ST SPEAr300 Machine + +config MACH_SPEAR310 + bool "SPEAr310" + help + Supports ST SPEAr310 Machine + +config MACH_SPEAR320 + bool "SPEAr320" + help + Supports ST SPEAr320 Machine + +endchoice + +# Adding SPEAr3XX machine specific configuration files +source "arch/arm/mach-spear3xx/Kconfig300" +source "arch/arm/mach-spear3xx/Kconfig310" +source "arch/arm/mach-spear3xx/Kconfig320" + +endif #ARCH_SPEAR3XX diff --git a/arch/arm/mach-spear3xx/Kconfig300 b/arch/arm/mach-spear3xx/Kconfig300 new file mode 100644 index 0000000..c519a05 --- /dev/null +++ b/arch/arm/mach-spear3xx/Kconfig300 @@ -0,0 +1,17 @@ +# +# SPEAr300 machine configuration file +# + +if MACH_SPEAR300 + +choice + prompt "SPEAr300 Boards" + default BOARD_SPEAR300_EVB + +config BOARD_SPEAR300_EVB + bool "SPEAr300 Evaluation Board" + help + Supports ST SPEAr300 Evaluation Board +endchoice + +endif #MACH_SPEAR300 diff --git a/arch/arm/mach-spear3xx/Kconfig310 b/arch/arm/mach-spear3xx/Kconfig310 new file mode 100644 index 0000000..60e7442 --- /dev/null +++ b/arch/arm/mach-spear3xx/Kconfig310 @@ -0,0 +1,17 @@ +# +# SPEAr310 machine configuration file +# + +if MACH_SPEAR310 + +choice + prompt "SPEAr310 Boards" + default BOARD_SPEAR310_EVB + +config BOARD_SPEAR310_EVB + bool "SPEAr310 Evaluation Board" + help + Supports ST SPEAr310 Evaluation Board +endchoice + +endif #MACH_SPEAR310 diff --git a/arch/arm/mach-spear3xx/Kconfig320 b/arch/arm/mach-spear3xx/Kconfig320 new file mode 100644 index 0000000..1c1d438 --- /dev/null +++ b/arch/arm/mach-spear3xx/Kconfig320 @@ -0,0 +1,17 @@ +# +# SPEAr320 machine configuration file +# + +if MACH_SPEAR320 + +choice + prompt "SPEAr320 Boards" + default BOARD_SPEAR320_EVB + +config BOARD_SPEAR320_EVB + bool "SPEAr320 Evaluation Board" + help + Supports ST SPEAr320 Evaluation Board +endchoice + +endif #MACH_SPEAR320 diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile new file mode 100644 index 0000000..b248624 --- /dev/null +++ b/arch/arm/mach-spear3xx/Makefile @@ -0,0 +1,26 @@ +# +# Makefile for SPEAr3XX machine series +# + +# common files +obj-y += spear3xx.o clock.o + +# spear300 specific files +obj-$(CONFIG_MACH_SPEAR300) += spear300.o + +# spear300 boards files +obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o + + +# spear310 specific files +obj-$(CONFIG_MACH_SPEAR310) += spear310.o + +# spear310 boards files +obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o + + +# spear320 specific files +obj-$(CONFIG_MACH_SPEAR320) += spear320.o + +# spear320 boards files +obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot new file mode 100644 index 0000000..7a1f3c0 --- /dev/null +++ b/arch/arm/mach-spear3xx/Makefile.boot @@ -0,0 +1,3 @@ +zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c new file mode 100644 index 0000000..6a95948 --- /dev/null +++ b/arch/arm/mach-spear3xx/spear300.c @@ -0,0 +1,23 @@ +/* + * arch/arm/mach-spear3xx/spear300.c + * + * SPEAr300 machine source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <mach/generic.h> +#include <mach/spear.h> + +/* Add spear300 specific devices here */ + +void __init spear300_init(void) +{ + /* call spear3xx family common init function */ + spear3xx_init(); +} diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c new file mode 100644 index 0000000..ed926ba --- /dev/null +++ b/arch/arm/mach-spear3xx/spear300_evb.c @@ -0,0 +1,47 @@ +/* + * arch/arm/mach-spear3xx/spear300_evb.c + * + * SPEAr300 evaluation board source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> +#include <mach/generic.h> +#include <mach/spear.h> + +static struct amba_device *amba_devs[] __initdata = { + &uart_device, +}; + +static struct platform_device *plat_devs[] __initdata = { +}; + +static void __init spear300_evb_init(void) +{ + unsigned int i; + + /* call spear300 machine init function */ + spear300_init(); + + /* Add Platform Devices */ + platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); + + /* Add Amba Devices */ + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) + amba_device_register(amba_devs[i], &iomem_resource); +} + +MACHINE_START(SPEAR300, "ST-SPEAR300-EVB") + .boot_params = 0x00000100, + .map_io = spear3xx_map_io, + .init_irq = spear3xx_init_irq, + .timer = &spear_sys_timer, + .init_machine = spear300_evb_init, +MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c new file mode 100644 index 0000000..35d61e4 --- /dev/null +++ b/arch/arm/mach-spear3xx/spear310.c @@ -0,0 +1,23 @@ +/* + * arch/arm/mach-spear3xx/spear310.c + * + * SPEAr310 machine source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <mach/generic.h> +#include <mach/spear.h> + +/* Add spear310 specific devices here */ + +void __init spear310_init(void) +{ + /* call spear3xx family common init function */ + spear3xx_init(); +} diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c new file mode 100644 index 0000000..6bc1488 --- /dev/null +++ b/arch/arm/mach-spear3xx/spear310_evb.c @@ -0,0 +1,47 @@ +/* + * arch/arm/mach-spear3xx/spear310_evb.c + * + * SPEAr310 evaluation board source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> +#include <mach/generic.h> +#include <mach/spear.h> + +static struct amba_device *amba_devs[] __initdata = { + &uart_device, +}; + +static struct platform_device *plat_devs[] __initdata = { +}; + +static void __init spear310_evb_init(void) +{ + unsigned int i; + + /* call spear310 machine init function */ + spear310_init(); + + /* Add Platform Devices */ + platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); + + /* Add Amba Devices */ + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) + amba_device_register(amba_devs[i], &iomem_resource); +} + +MACHINE_START(SPEAR310, "ST-SPEAR310-EVB") + .boot_params = 0x00000100, + .map_io = spear3xx_map_io, + .init_irq = spear3xx_init_irq, + .timer = &spear_sys_timer, + .init_machine = spear310_evb_init, +MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c new file mode 100644 index 0000000..0fb2f4b --- /dev/null +++ b/arch/arm/mach-spear3xx/spear320.c @@ -0,0 +1,23 @@ +/* + * arch/arm/mach-spear3xx/spear320.c + * + * SPEAr320 machine source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <mach/generic.h> +#include <mach/spear.h> + +/* Add spear320 specific devices here */ + +void __init spear320_init(void) +{ + /* call spear3xx family common init function */ + spear3xx_init(); +} diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c new file mode 100644 index 0000000..e61599c --- /dev/null +++ b/arch/arm/mach-spear3xx/spear320_evb.c @@ -0,0 +1,47 @@ +/* + * arch/arm/mach-spear3xx/spear320_evb.c + * + * SPEAr320 evaluation board source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> +#include <mach/generic.h> +#include <mach/spear.h> + +static struct amba_device *amba_devs[] __initdata = { + &uart_device, +}; + +static struct platform_device *plat_devs[] __initdata = { +}; + +static void __init spear320_evb_init(void) +{ + unsigned int i; + + /* call spear320 machine init function */ + spear320_init(); + + /* Add Platform Devices */ + platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); + + /* Add Amba Devices */ + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) + amba_device_register(amba_devs[i], &iomem_resource); +} + +MACHINE_START(SPEAR320, "ST-SPEAR320-EVB") + .boot_params = 0x00000100, + .map_io = spear3xx_map_io, + .init_irq = spear3xx_init_irq, + .timer = &spear_sys_timer, + .init_machine = spear320_evb_init, +MACHINE_END diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c new file mode 100644 index 0000000..f529d74 --- /dev/null +++ b/arch/arm/mach-spear3xx/spear3xx.c @@ -0,0 +1,118 @@ +/* + * arch/arm/mach-spear3xx/spear3xx.c + * + * SPEAr3XX machines common source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/types.h> +#include <linux/ptrace.h> +#include <linux/io.h> +#include <asm/hardware/vic.h> +#include <asm/irq.h> +#include <asm/mach/arch.h> +#include <mach/irqs.h> +#include <mach/generic.h> +#include <mach/spear.h> +#include <plat/gpt.h> + +/* Add spear3xx machines common devices here */ +/* uart device registeration */ +struct amba_device uart_device = { + .dev = { + .init_name = "uart", + }, + .res = { + .start = SPEAR3XX_ICM1_UART_BASE, + .end = SPEAR3XX_ICM1_UART_BASE + SPEAR3XX_ICM1_UART_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_UART, NO_IRQ}, + .periphid = 0x00041011, +}; + +/* Following section enumerates all available GPTs */ +struct spear_timer spear3xx_timers[] = { + { + .id = 1, + .phys_base = SPEAR3XX_ML1_TMR_BASE, + .irq = IRQ_CPU_GPT1_1 + }, { + .id = 2, + .phys_base = (SPEAR3XX_ML1_TMR_BASE + 0x80), + .irq = IRQ_CPU_GPT1_2 + }, { + .id = 3, + .phys_base = (SPEAR3XX_ICM3_TMR0_BASE), + .irq = IRQ_BASIC_GPT1_1 + }, { + .id = 4, + .phys_base = (SPEAR3XX_ICM3_TMR0_BASE + 0x80), + .irq = IRQ_BASIC_GPT1_2 + }, { + .id = 5, + .phys_base = (SPEAR3XX_ICM3_TMR1_BASE), + .irq = IRQ_BASIC_GPT2_1 + }, { + .id = 6, + .phys_base = (SPEAR3XX_ICM3_TMR1_BASE + 0x80), + .irq = IRQ_BASIC_GPT2_2 + }, +}; + +void __init spear_gpt_init() +{ + spear_timer_init(spear3xx_timers, ARRAY_SIZE(spear3xx_timers)); +} + +/* Do spear3xx familiy common initialization part here */ +void __init spear3xx_init(void) +{ + /* nothing to do for now */ +} + +/* This will initialize vic */ +void __init spear3xx_init_irq(void) +{ + vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0); +} + +/* Following will create static virtual/physical mappings */ +struct map_desc spear3xx_io_desc[] __initdata = { + { + .virtual = VA_SPEAR3XX_ICM1_UART_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE), + .length = SPEAR3XX_ICM1_UART_SIZE, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR3XX_ML1_VIC_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE), + .length = SPEAR3XX_ML1_VIC_SIZE, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE), + .length = SPEAR3XX_ICM3_SYS_CTRL_SIZE, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE, + .pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE), + .length = SPEAR3XX_ICM3_MISC_REG_SIZE, + .type = MT_DEVICE + }, +}; + +/* This will create static memory mapping for selected devices */ +void __init spear3xx_map_io(void) +{ + iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); + + /* This will initialize clock framework */ + clk_init(); +} -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH 08/11] ST SPEAr: Added source files for SPEAr6xx machine family 2010-03-03 5:07 ` [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family Viresh KUMAR @ 2010-03-03 5:07 ` Viresh KUMAR 2010-03-03 5:07 ` [PATCH 09/11] ST SPEAr: Added support for SPEAr platform and machines in arch/arm/ Viresh KUMAR 2010-03-09 6:46 ` [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family Linus Walleij 1 sibling, 1 reply; 51+ messages in thread From: Viresh KUMAR @ 2010-03-03 5:07 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Viresh Kumar <viresh.kumar@st.com> --- arch/arm/mach-spear6xx/Kconfig | 20 +++++ arch/arm/mach-spear6xx/Kconfig600 | 17 ++++ arch/arm/mach-spear6xx/Makefile | 12 +++ arch/arm/mach-spear6xx/Makefile.boot | 3 + arch/arm/mach-spear6xx/spear600.c | 23 +++++ arch/arm/mach-spear6xx/spear600_evb.c | 48 +++++++++++ arch/arm/mach-spear6xx/spear6xx.c | 149 +++++++++++++++++++++++++++++++++ 7 files changed, 272 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-spear6xx/Kconfig create mode 100644 arch/arm/mach-spear6xx/Kconfig600 create mode 100644 arch/arm/mach-spear6xx/Makefile create mode 100644 arch/arm/mach-spear6xx/Makefile.boot create mode 100644 arch/arm/mach-spear6xx/spear600.c create mode 100644 arch/arm/mach-spear6xx/spear600_evb.c create mode 100644 arch/arm/mach-spear6xx/spear6xx.c diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig new file mode 100644 index 0000000..bddba03 --- /dev/null +++ b/arch/arm/mach-spear6xx/Kconfig @@ -0,0 +1,20 @@ +# +# SPEAr6XX Machine configuration file +# + +if ARCH_SPEAR6XX + +choice + prompt "SPEAr6XX Family" + default MACH_SPEAR600 + +config MACH_SPEAR600 + bool "SPEAr600" + help + Supports ST SPEAr600 Machine +endchoice + +# Adding SPEAr6XX machine specific configuration files +source "arch/arm/mach-spear6xx/Kconfig600" + +endif #ARCH_SPEAR6XX diff --git a/arch/arm/mach-spear6xx/Kconfig600 b/arch/arm/mach-spear6xx/Kconfig600 new file mode 100644 index 0000000..9e19f65 --- /dev/null +++ b/arch/arm/mach-spear6xx/Kconfig600 @@ -0,0 +1,17 @@ +# +# SPEAr600 machine configuration file +# + +if MACH_SPEAR600 + +choice + prompt "SPEAr600 Boards" + default BOARD_SPEAR600_EVB + +config BOARD_SPEAR600_EVB + bool "SPEAr600 Evaluation Board" + help + Supports ST SPEAr600 Evaluation Board +endchoice + +endif #MACH_SPEAR600 diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile new file mode 100644 index 0000000..cc1a4d8 --- /dev/null +++ b/arch/arm/mach-spear6xx/Makefile @@ -0,0 +1,12 @@ +# +# Makefile for SPEAr6XX machine series +# + +# common files +obj-y += clock.o spear6xx.o + +# spear600 specific files +obj-$(CONFIG_MACH_SPEAR600) += spear600.o + +# spear600 boards files +obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot new file mode 100644 index 0000000..7a1f3c0 --- /dev/null +++ b/arch/arm/mach-spear6xx/Makefile.boot @@ -0,0 +1,3 @@ +zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-spear6xx/spear600.c b/arch/arm/mach-spear6xx/spear600.c new file mode 100644 index 0000000..2a08ee9 --- /dev/null +++ b/arch/arm/mach-spear6xx/spear600.c @@ -0,0 +1,23 @@ +/* + * arch/arm/mach-spear6xx/spear600.c + * + * SPEAr600 machine source file + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <mach/generic.h> +#include <mach/spear.h> + +/* Add spear600 specific devices here */ + +void __init spear600_init(void) +{ + /* call spear6xx family common init function */ + spear6xx_init(); +} diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c new file mode 100644 index 0000000..0ee2ce6 --- /dev/null +++ b/arch/arm/mach-spear6xx/spear600_evb.c @@ -0,0 +1,48 @@ +/* + * arch/arm/mach-spear6xx/spear600_evb.c + * + * SPEAr600 evaluation board source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar<viresh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> +#include <mach/generic.h> +#include <mach/spear.h> + +static struct amba_device *amba_devs[] __initdata = { + &uart_device[0], + &uart_device[1], +}; + +static struct platform_device *plat_devs[] __initdata = { +}; + +static void __init spear600_evb_init(void) +{ + unsigned int i; + + /* call spear600 machine init function */ + spear600_init(); + + /* Add Platform Devices */ + platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); + + /* Add Amba Devices */ + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) + amba_device_register(amba_devs[i], &iomem_resource); +} + +MACHINE_START(SPEAR600, "ST-SPEAR600-EVB") + .boot_params = 0x00000100, + .map_io = spear6xx_map_io, + .init_irq = spear6xx_init_irq, + .timer = &spear_sys_timer, + .init_machine = spear600_evb_init, +MACHINE_END diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c new file mode 100644 index 0000000..dafa067 --- /dev/null +++ b/arch/arm/mach-spear6xx/spear6xx.c @@ -0,0 +1,149 @@ +/* + * arch/arm/mach-spear6xx/spear6xx.c + * + * SPEAr6XX machines common source file + * + * Copyright (C) 2009 ST Microelectronics + * Rajeev Kumar<rajeev-dlh.kumar@st.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/types.h> +#include <linux/ptrace.h> +#include <linux/io.h> +#include <asm/hardware/vic.h> +#include <asm/irq.h> +#include <asm/mach/arch.h> +#include <mach/irqs.h> +#include <mach/generic.h> +#include <mach/spear.h> +#include <plat/gpt.h> + +/* Add spear6xx machines common devices here */ +/* uart device registeration */ +struct amba_device uart_device[] = { + { + .dev = { + .init_name = "uart0", + }, + .res = { + .start = SPEAR6XX_ICM1_UART0_BASE, + .end = SPEAR6XX_ICM1_UART0_BASE + + SPEAR6XX_ICM1_UART0_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_UART_0, NO_IRQ}, + .periphid = 0x00041011, + }, + { + .dev = { + .init_name = "uart1", + }, + .res = { + .start = SPEAR6XX_ICM1_UART1_BASE, + .end = SPEAR6XX_ICM1_UART1_BASE + + SPEAR6XX_ICM1_UART1_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + .irq = {IRQ_UART_1, NO_IRQ}, + .periphid = 0x00041011, + } +}; + +/* Following enumerates all GPTs available in the system */ +struct spear_timer spear6xx_timers[] = { + { + .id = 1, + .phys_base = SPEAR6XX_CPU_TMR_BASE, + .irq = IRQ_CPU_GPT1_1 + }, { + .id = 2, + .phys_base = (SPEAR6XX_CPU_TMR_BASE + 0x80), + .irq = IRQ_CPU_GPT1_2 + }, { + .id = 3, + .phys_base = (SPEAR6XX_ICM3_TMR_BASE), + .irq = IRQ_BASIC_GPT1_1 + }, { + .id = 4, + .phys_base = (SPEAR6XX_ICM3_TMR_BASE + 0x80), + .irq = IRQ_BASIC_GPT1_2 + + }, { + .id = 5, + .phys_base = SPEAR6XX_ICM2_TMR0_BASE, + .irq = IRQ_APPL_GPT1_1 + }, { + .id = 6, + .phys_base = (SPEAR6XX_ICM2_TMR0_BASE + 0x80), + .irq = IRQ_APPL_GPT1_2 + }, { + .id = 7, + .phys_base = SPEAR6XX_ICM2_TMR1_BASE, + .irq = IRQ_APPL_GPT2_1 + }, { + .id = 8, + .phys_base = (SPEAR6XX_ICM2_TMR1_BASE + 0x80), + .irq = IRQ_APPL_GPT2_2 + }, +}; + +void __init spear_gpt_init(void) +{ + spear_timer_init(spear6xx_timers, ARRAY_SIZE(spear6xx_timers)); +} + +/* This will add devices, and do machine specific tasks */ +void __init spear6xx_init(void) +{ + /* nothing to do for now */ +} + +/* This will initialize vic */ +void __init spear6xx_init_irq(void) +{ + vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_PRI_BASE, 0, ~0, 0); + vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_SEC_BASE, 32, ~0, 0); +} + +/* Following will create static virtual/physical mappings */ +static struct map_desc spear6xx_io_desc[] __initdata = { + { + .virtual = VA_SPEAR6XX_ICM1_UART0_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE), + .length = SPEAR6XX_ICM1_UART0_SIZE, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE), + .length = SPEAR6XX_CPU_VIC_PRI_SIZE, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE), + .length = SPEAR6XX_CPU_VIC_SEC_SIZE, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE), + .length = SPEAR6XX_ICM3_MISC_REG_BASE, + .type = MT_DEVICE + }, { + .virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE), + .length = SPEAR6XX_ICM3_MISC_REG_SIZE, + .type = MT_DEVICE + }, +}; + +/* This will create static memory mapping for selected devices */ +void __init spear6xx_map_io(void) +{ + iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); + + /* This will initialize clock framework */ + clk_init(); +} -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH 09/11] ST SPEAr: Added support for SPEAr platform and machines in arch/arm/ 2010-03-03 5:07 ` [PATCH 08/11] ST SPEAr: Added source files for SPEAr6xx " Viresh KUMAR @ 2010-03-03 5:07 ` Viresh KUMAR 2010-03-03 5:07 ` [PATCH 10/11] ST SPEAr: Added default configuration files for SPEAr machines Viresh KUMAR 0 siblings, 1 reply; 51+ messages in thread From: Viresh KUMAR @ 2010-03-03 5:07 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Viresh Kumar <viresh.kumar@st.com> --- arch/arm/Kconfig | 11 +++++++++++ arch/arm/Makefile | 5 +++++ 2 files changed, 16 insertions(+), 0 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 184a6bd..9b7398a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -728,6 +728,16 @@ config ARCH_U8500 help Support for ST-Ericsson's Ux500 architecture +config PLAT_SPEAR + bool "ST SPEAr" + select ARM_AMBA + select COMMON_CLKDEV + select GENERIC_CLOCKEVENTS + select GENERIC_TIME + select HAVE_CLK + help + Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). + endchoice source "arch/arm/mach-aaec2000/Kconfig" @@ -807,6 +817,7 @@ source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/plat-s3c64xx/Kconfig" source "arch/arm/plat-s3c/Kconfig" source "arch/arm/plat-s5pc1xx/Kconfig" +source "arch/arm/plat-spear/Kconfig" if ARCH_S3C2410 source "arch/arm/mach-s3c2400/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 356d702..95a3bfc 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -172,6 +172,10 @@ machine-$(CONFIG_ARCH_U8500) := ux500 machine-$(CONFIG_ARCH_VERSATILE) := versatile machine-$(CONFIG_ARCH_W90X900) := w90x900 machine-$(CONFIG_FOOTBRIDGE) := footbridge +machine-$(CONFIG_MACH_SPEAR300) := spear3xx +machine-$(CONFIG_MACH_SPEAR310) := spear3xx +machine-$(CONFIG_MACH_SPEAR320) := spear3xx +machine-$(CONFIG_MACH_SPEAR600) := spear6xx # Platform directory name. This list is sorted alphanumerically # by CONFIG_* macro name. @@ -185,6 +189,7 @@ plat-$(CONFIG_PLAT_PXA) := pxa plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c samsung plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c samsung plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c samsung +plat-$(CONFIG_PLAT_SPEAR) := spear ifeq ($(CONFIG_ARCH_EBSA110),y) # This is what happens if you forget the IOCS16 line. -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH 10/11] ST SPEAr: Added default configuration files for SPEAr machines 2010-03-03 5:07 ` [PATCH 09/11] ST SPEAr: Added support for SPEAr platform and machines in arch/arm/ Viresh KUMAR @ 2010-03-03 5:07 ` Viresh KUMAR 2010-03-03 5:07 ` [PATCH 11/11] ST SPEAr: Updated Maintainers and added Documentation/arm/SPEAr Viresh KUMAR 2010-03-11 20:18 ` [PATCH 10/11] ST SPEAr: Added default configuration files for SPEAr machines Linus Walleij 0 siblings, 2 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-03 5:07 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Viresh Kumar <viresh.kumar@st.com> --- arch/arm/configs/spear300_defconfig | 1409 ++++++++++++++++++++++++++++++++++ arch/arm/configs/spear310_defconfig | 1410 ++++++++++++++++++++++++++++++++++ arch/arm/configs/spear320_defconfig | 1410 ++++++++++++++++++++++++++++++++++ arch/arm/configs/spear600_defconfig | 1451 +++++++++++++++++++++++++++++++++++ 4 files changed, 5680 insertions(+), 0 deletions(-) create mode 100644 arch/arm/configs/spear300_defconfig create mode 100644 arch/arm/configs/spear310_defconfig create mode 100644 arch/arm/configs/spear320_defconfig create mode 100644 arch/arm/configs/spear600_defconfig diff --git a/arch/arm/configs/spear300_defconfig b/arch/arm/configs/spear300_defconfig new file mode 100644 index 0000000..596bad5 --- /dev/null +++ b/arch/arm/configs/spear300_defconfig @@ -0,0 +1,1409 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33 +# Fri Feb 26 19:17:02 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +CONFIG_AUDIT=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +CONFIG_OPROFILE=m +CONFIG_HAVE_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_KRETPROBES=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_SLOW_WORK=y +# CONFIG_SLOW_WORK_DEBUG is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_PLAT_SPEAR=y +CONFIG_ARCH_SPEAR3XX=y +# CONFIG_ARCH_SPEAR6XX is not set +CONFIG_MACH_SPEAR300=y +# CONFIG_MACH_SPEAR310 is not set +# CONFIG_MACH_SPEAR320 is not set +CONFIG_BOARD_SPEAR300_EVB=y + +# +# Processor Type +# +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_VIC=y +CONFIG_ARM_VIC_NR=2 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y +# CONFIG_ARTHUR is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETLABEL is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_TPROXY is not set +CONFIG_NETFILTER_XTABLES=m +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +CONFIG_NETFILTER_XT_MATCH_HL=m +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +CONFIG_NETFILTER_XT_MATCH_SCTP=m +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +CONFIG_IP_VS=m +# CONFIG_IP_VS_IPV6 is not set +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +# CONFIG_IP_NF_MATCH_AH is not set +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +# CONFIG_IP_NF_TARGET_TTL is not set +CONFIG_IP_NF_RAW=m +# CONFIG_IP_NF_SECURITY is not set +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +CONFIG_IP6_NF_IPTABLES=m +# CONFIG_IP6_NF_MATCH_AH is not set +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +# CONFIG_IP6_NF_MATCH_MH is not set +CONFIG_IP6_NF_MATCH_RT=m +# CONFIG_IP6_NF_TARGET_HL is not set +CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m +# CONFIG_IP6_NF_TARGET_REJECT is not set +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +# CONFIG_IP6_NF_SECURITY is not set +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +# CONFIG_BRIDGE_EBT_IP6 is not set +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +# CONFIG_BRIDGE_EBT_ULOG is not set +# CONFIG_BRIDGE_EBT_NFLOG is not set +# CONFIG_IP_DCCP is not set +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +# CONFIG_ATM_MPOA is not set +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_STP=m +CONFIG_BRIDGE=m +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_MULTIQ is not set +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +# CONFIG_CLS_U32_MARK is not set +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_CLS_IND=y +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_TCPPROBE is not set +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=m +CONFIG_BT_L2CAP=m +CONFIG_BT_SCO=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +# CONFIG_BT_HCIUART_LL is not set +CONFIG_BT_HCIVHCI=m +# CONFIG_BT_MRVL is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_CRYPTOLOOP=m + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=m +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_VSXXXAA=m +CONFIG_INPUT_JOYSTICK=y +# CONFIG_JOYSTICK_ANALOG is not set +# CONFIG_JOYSTICK_A3D is not set +# CONFIG_JOYSTICK_ADI is not set +# CONFIG_JOYSTICK_COBRA is not set +# CONFIG_JOYSTICK_GF2K is not set +# CONFIG_JOYSTICK_GRIP is not set +# CONFIG_JOYSTICK_GRIP_MP is not set +# CONFIG_JOYSTICK_GUILLEMOT is not set +# CONFIG_JOYSTICK_INTERACT is not set +# CONFIG_JOYSTICK_SIDEWINDER is not set +# CONFIG_JOYSTICK_TMDC is not set +# CONFIG_JOYSTICK_IFORCE is not set +# CONFIG_JOYSTICK_WARRIOR is not set +# CONFIG_JOYSTICK_MAGELLAN is not set +# CONFIG_JOYSTICK_SPACEORB is not set +# CONFIG_JOYSTICK_SPACEBALL is not set +# CONFIG_JOYSTICK_STINGER is not set +# CONFIG_JOYSTICK_TWIDJOY is not set +# CONFIG_JOYSTICK_ZHENHUA is not set +# CONFIG_JOYSTICK_JOYDUMP is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +CONFIG_TOUCHSCREEN_GUNZE=m +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=m + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=y +CONFIG_MAX_RAW_DEVS=8192 +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=m +# CONFIG_SSB_DEBUG is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_HID=m +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=m +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=m +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +# CONFIG_INOTIFY is not set +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=m +# CONFIG_SQUASHFS is not set +CONFIG_VXFS_FS=m +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_SPKM3=m +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_EXPERIMENTAL is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_OSF_PARTITION=y +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_LDM_PARTITION is not set +CONFIG_SGI_PARTITION=y +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +# CONFIG_KPROBES_SANITY_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +# CONFIG_SECURITY_PATH is not set +CONFIG_LSM_MMAP_MIN_ADDR=65536 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1 +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_DEFAULT_SECURITY="selinux" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_HW=y +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/spear310_defconfig b/arch/arm/configs/spear310_defconfig new file mode 100644 index 0000000..26898b8 --- /dev/null +++ b/arch/arm/configs/spear310_defconfig @@ -0,0 +1,1410 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33 +# Sat Feb 27 09:20:40 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +CONFIG_AUDIT=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +CONFIG_OPROFILE=m +CONFIG_HAVE_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_KRETPROBES=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_SLOW_WORK=y +# CONFIG_SLOW_WORK_DEBUG is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_PLAT_SPEAR=y +CONFIG_ARCH_SPEAR3XX=y +# CONFIG_ARCH_SPEAR6XX is not set +# CONFIG_MACH_SPEAR300 is not set +CONFIG_MACH_SPEAR310=y +# CONFIG_MACH_SPEAR320 is not set +# CONFIG_BOARD_SPEAR300_EVB is not set +CONFIG_BOARD_SPEAR310_EVB=y + +# +# Processor Type +# +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_VIC=y +CONFIG_ARM_VIC_NR=2 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y +# CONFIG_ARTHUR is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETLABEL is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_TPROXY is not set +CONFIG_NETFILTER_XTABLES=m +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +CONFIG_NETFILTER_XT_MATCH_HL=m +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +CONFIG_NETFILTER_XT_MATCH_SCTP=m +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +CONFIG_IP_VS=m +# CONFIG_IP_VS_IPV6 is not set +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +# CONFIG_IP_NF_MATCH_AH is not set +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +# CONFIG_IP_NF_TARGET_TTL is not set +CONFIG_IP_NF_RAW=m +# CONFIG_IP_NF_SECURITY is not set +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +CONFIG_IP6_NF_IPTABLES=m +# CONFIG_IP6_NF_MATCH_AH is not set +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +# CONFIG_IP6_NF_MATCH_MH is not set +CONFIG_IP6_NF_MATCH_RT=m +# CONFIG_IP6_NF_TARGET_HL is not set +CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m +# CONFIG_IP6_NF_TARGET_REJECT is not set +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +# CONFIG_IP6_NF_SECURITY is not set +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +# CONFIG_BRIDGE_EBT_IP6 is not set +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +# CONFIG_BRIDGE_EBT_ULOG is not set +# CONFIG_BRIDGE_EBT_NFLOG is not set +# CONFIG_IP_DCCP is not set +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +# CONFIG_ATM_MPOA is not set +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_STP=m +CONFIG_BRIDGE=m +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_MULTIQ is not set +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +# CONFIG_CLS_U32_MARK is not set +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_CLS_IND=y +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_TCPPROBE is not set +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=m +CONFIG_BT_L2CAP=m +CONFIG_BT_SCO=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +# CONFIG_BT_HCIUART_LL is not set +CONFIG_BT_HCIVHCI=m +# CONFIG_BT_MRVL is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_CRYPTOLOOP=m + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=m +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_VSXXXAA=m +CONFIG_INPUT_JOYSTICK=y +# CONFIG_JOYSTICK_ANALOG is not set +# CONFIG_JOYSTICK_A3D is not set +# CONFIG_JOYSTICK_ADI is not set +# CONFIG_JOYSTICK_COBRA is not set +# CONFIG_JOYSTICK_GF2K is not set +# CONFIG_JOYSTICK_GRIP is not set +# CONFIG_JOYSTICK_GRIP_MP is not set +# CONFIG_JOYSTICK_GUILLEMOT is not set +# CONFIG_JOYSTICK_INTERACT is not set +# CONFIG_JOYSTICK_SIDEWINDER is not set +# CONFIG_JOYSTICK_TMDC is not set +# CONFIG_JOYSTICK_IFORCE is not set +# CONFIG_JOYSTICK_WARRIOR is not set +# CONFIG_JOYSTICK_MAGELLAN is not set +# CONFIG_JOYSTICK_SPACEORB is not set +# CONFIG_JOYSTICK_SPACEBALL is not set +# CONFIG_JOYSTICK_STINGER is not set +# CONFIG_JOYSTICK_TWIDJOY is not set +# CONFIG_JOYSTICK_ZHENHUA is not set +# CONFIG_JOYSTICK_JOYDUMP is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +CONFIG_TOUCHSCREEN_GUNZE=m +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=m + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=y +CONFIG_MAX_RAW_DEVS=8192 +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=m +# CONFIG_SSB_DEBUG is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_HID=m +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=m +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=m +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +# CONFIG_INOTIFY is not set +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=m +# CONFIG_SQUASHFS is not set +CONFIG_VXFS_FS=m +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_SPKM3=m +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_EXPERIMENTAL is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_OSF_PARTITION=y +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_LDM_PARTITION is not set +CONFIG_SGI_PARTITION=y +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +# CONFIG_KPROBES_SANITY_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +# CONFIG_SECURITY_PATH is not set +CONFIG_LSM_MMAP_MIN_ADDR=65536 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1 +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_DEFAULT_SECURITY="selinux" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_HW=y +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/spear320_defconfig b/arch/arm/configs/spear320_defconfig new file mode 100644 index 0000000..ea6731c --- /dev/null +++ b/arch/arm/configs/spear320_defconfig @@ -0,0 +1,1410 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33 +# Sat Feb 27 09:20:48 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +CONFIG_AUDIT=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +CONFIG_OPROFILE=m +CONFIG_HAVE_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_KRETPROBES=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_SLOW_WORK=y +# CONFIG_SLOW_WORK_DEBUG is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_PLAT_SPEAR=y +CONFIG_ARCH_SPEAR3XX=y +# CONFIG_ARCH_SPEAR6XX is not set +# CONFIG_MACH_SPEAR300 is not set +# CONFIG_MACH_SPEAR310 is not set +CONFIG_MACH_SPEAR320=y +# CONFIG_BOARD_SPEAR300_EVB is not set +CONFIG_BOARD_SPEAR320_EVB=y + +# +# Processor Type +# +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_VIC=y +CONFIG_ARM_VIC_NR=2 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y +# CONFIG_ARTHUR is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETLABEL is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_TPROXY is not set +CONFIG_NETFILTER_XTABLES=m +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +CONFIG_NETFILTER_XT_MATCH_HL=m +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +CONFIG_NETFILTER_XT_MATCH_SCTP=m +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +CONFIG_IP_VS=m +# CONFIG_IP_VS_IPV6 is not set +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +# CONFIG_IP_NF_MATCH_AH is not set +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +# CONFIG_IP_NF_TARGET_TTL is not set +CONFIG_IP_NF_RAW=m +# CONFIG_IP_NF_SECURITY is not set +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +CONFIG_IP6_NF_IPTABLES=m +# CONFIG_IP6_NF_MATCH_AH is not set +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +# CONFIG_IP6_NF_MATCH_MH is not set +CONFIG_IP6_NF_MATCH_RT=m +# CONFIG_IP6_NF_TARGET_HL is not set +CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m +# CONFIG_IP6_NF_TARGET_REJECT is not set +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +# CONFIG_IP6_NF_SECURITY is not set +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +# CONFIG_BRIDGE_EBT_IP6 is not set +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +# CONFIG_BRIDGE_EBT_ULOG is not set +# CONFIG_BRIDGE_EBT_NFLOG is not set +# CONFIG_IP_DCCP is not set +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +# CONFIG_ATM_MPOA is not set +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_STP=m +CONFIG_BRIDGE=m +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_MULTIQ is not set +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +# CONFIG_CLS_U32_MARK is not set +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_CLS_IND=y +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_TCPPROBE is not set +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=m +CONFIG_BT_L2CAP=m +CONFIG_BT_SCO=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +# CONFIG_BT_HCIUART_LL is not set +CONFIG_BT_HCIVHCI=m +# CONFIG_BT_MRVL is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_CRYPTOLOOP=m + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=m +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_VSXXXAA=m +CONFIG_INPUT_JOYSTICK=y +# CONFIG_JOYSTICK_ANALOG is not set +# CONFIG_JOYSTICK_A3D is not set +# CONFIG_JOYSTICK_ADI is not set +# CONFIG_JOYSTICK_COBRA is not set +# CONFIG_JOYSTICK_GF2K is not set +# CONFIG_JOYSTICK_GRIP is not set +# CONFIG_JOYSTICK_GRIP_MP is not set +# CONFIG_JOYSTICK_GUILLEMOT is not set +# CONFIG_JOYSTICK_INTERACT is not set +# CONFIG_JOYSTICK_SIDEWINDER is not set +# CONFIG_JOYSTICK_TMDC is not set +# CONFIG_JOYSTICK_IFORCE is not set +# CONFIG_JOYSTICK_WARRIOR is not set +# CONFIG_JOYSTICK_MAGELLAN is not set +# CONFIG_JOYSTICK_SPACEORB is not set +# CONFIG_JOYSTICK_SPACEBALL is not set +# CONFIG_JOYSTICK_STINGER is not set +# CONFIG_JOYSTICK_TWIDJOY is not set +# CONFIG_JOYSTICK_ZHENHUA is not set +# CONFIG_JOYSTICK_JOYDUMP is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +CONFIG_TOUCHSCREEN_GUNZE=m +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=m + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=y +CONFIG_MAX_RAW_DEVS=8192 +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=m +# CONFIG_SSB_DEBUG is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_HID=m +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=m +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=m +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +# CONFIG_INOTIFY is not set +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=m +# CONFIG_SQUASHFS is not set +CONFIG_VXFS_FS=m +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_SPKM3=m +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_EXPERIMENTAL is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_OSF_PARTITION=y +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_LDM_PARTITION is not set +CONFIG_SGI_PARTITION=y +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +# CONFIG_KPROBES_SANITY_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +# CONFIG_SECURITY_PATH is not set +CONFIG_LSM_MMAP_MIN_ADDR=65536 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1 +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_DEFAULT_SECURITY="selinux" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_HW=y +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/spear600_defconfig b/arch/arm/configs/spear600_defconfig new file mode 100644 index 0000000..041139d --- /dev/null +++ b/arch/arm/configs/spear600_defconfig @@ -0,0 +1,1451 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33 +# Fri Feb 26 19:18:12 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +CONFIG_AUDIT=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +CONFIG_OPROFILE=m +CONFIG_HAVE_OPROFILE=y +CONFIG_KPROBES=y +CONFIG_KRETPROBES=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_SLOW_WORK=y +# CONFIG_SLOW_WORK_DEBUG is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_PLAT_SPEAR=y +# CONFIG_ARCH_SPEAR3XX is not set +CONFIG_ARCH_SPEAR6XX=y +CONFIG_MACH_SPEAR600=y +CONFIG_BOARD_SPEAR600_EVB=y + +# +# Processor Type +# +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_VIC=y +CONFIG_ARM_VIC_NR=2 +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_AEABI is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y +# CONFIG_ARTHUR is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETLABEL is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_TPROXY is not set +CONFIG_NETFILTER_XTABLES=m +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +CONFIG_NETFILTER_XT_MATCH_HL=m +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +CONFIG_NETFILTER_XT_MATCH_SCTP=m +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +CONFIG_IP_VS=m +# CONFIG_IP_VS_IPV6 is not set +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +# CONFIG_IP_NF_MATCH_AH is not set +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +# CONFIG_IP_NF_TARGET_TTL is not set +CONFIG_IP_NF_RAW=m +# CONFIG_IP_NF_SECURITY is not set +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +CONFIG_IP6_NF_IPTABLES=m +# CONFIG_IP6_NF_MATCH_AH is not set +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +# CONFIG_IP6_NF_MATCH_MH is not set +CONFIG_IP6_NF_MATCH_RT=m +# CONFIG_IP6_NF_TARGET_HL is not set +CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m +# CONFIG_IP6_NF_TARGET_REJECT is not set +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +# CONFIG_IP6_NF_SECURITY is not set +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +# CONFIG_BRIDGE_EBT_IP6 is not set +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +# CONFIG_BRIDGE_EBT_ULOG is not set +# CONFIG_BRIDGE_EBT_NFLOG is not set +# CONFIG_IP_DCCP is not set +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +# CONFIG_ATM_MPOA is not set +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_STP=m +CONFIG_BRIDGE=m +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +# CONFIG_NET_SCH_MULTIQ is not set +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +# CONFIG_CLS_U32_MARK is not set +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_CLS_IND=y +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_TCPPROBE is not set +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=m +CONFIG_BT_L2CAP=m +CONFIG_BT_SCO=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +# CONFIG_BT_HCIUART_LL is not set +CONFIG_BT_HCIVHCI=m +# CONFIG_BT_MRVL is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_CRYPTOLOOP=m + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=m +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_NETDEVICES is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_VSXXXAA=m +CONFIG_INPUT_JOYSTICK=y +# CONFIG_JOYSTICK_ANALOG is not set +# CONFIG_JOYSTICK_A3D is not set +# CONFIG_JOYSTICK_ADI is not set +# CONFIG_JOYSTICK_COBRA is not set +# CONFIG_JOYSTICK_GF2K is not set +# CONFIG_JOYSTICK_GRIP is not set +# CONFIG_JOYSTICK_GRIP_MP is not set +# CONFIG_JOYSTICK_GUILLEMOT is not set +# CONFIG_JOYSTICK_INTERACT is not set +# CONFIG_JOYSTICK_SIDEWINDER is not set +# CONFIG_JOYSTICK_TMDC is not set +# CONFIG_JOYSTICK_IFORCE is not set +# CONFIG_JOYSTICK_WARRIOR is not set +# CONFIG_JOYSTICK_MAGELLAN is not set +# CONFIG_JOYSTICK_SPACEORB is not set +# CONFIG_JOYSTICK_SPACEBALL is not set +# CONFIG_JOYSTICK_STINGER is not set +# CONFIG_JOYSTICK_TWIDJOY is not set +# CONFIG_JOYSTICK_ZHENHUA is not set +# CONFIG_JOYSTICK_JOYDUMP is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +CONFIG_TOUCHSCREEN_GUNZE=m +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=m + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_N_HDLC=m +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +CONFIG_STALDRV=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_IPMI_HANDLER=m +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=y +CONFIG_MAX_RAW_DEVS=8192 +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=m +# CONFIG_SSB_DEBUG is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_RAWMIDI_SEQ=m +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_MPU401_UART=m +CONFIG_SND_DRIVERS=y +CONFIG_SND_DUMMY=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +# CONFIG_SND_SERIAL_U16550 is not set +CONFIG_SND_MPU401=m +CONFIG_SND_ARM=y +# CONFIG_SND_ARMAACI is not set +# CONFIG_SND_SOC is not set +# CONFIG_SOUND_PRIME is not set +# CONFIG_HID_SUPPORT is not set +CONFIG_HID=m +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=m +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=m +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +# CONFIG_INOTIFY is not set +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=m +# CONFIG_SQUASHFS is not set +CONFIG_VXFS_FS=m +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_SPKM3=m +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_EXPERIMENTAL is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +CONFIG_OSF_PARTITION=y +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +# CONFIG_LDM_PARTITION is not set +CONFIG_SGI_PARTITION=y +# CONFIG_ULTRIX_PARTITION is not set +CONFIG_SUN_PARTITION=y +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_DETECTOR=y +# CONFIG_KPROBES_SANITY_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +# CONFIG_SECURITY_PATH is not set +CONFIG_LSM_MMAP_MIN_ADDR=65536 +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1 +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_DEFAULT_SECURITY="selinux" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_HW=y +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_DECOMPRESS=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH 11/11] ST SPEAr: Updated Maintainers and added Documentation/arm/SPEAr 2010-03-03 5:07 ` [PATCH 10/11] ST SPEAr: Added default configuration files for SPEAr machines Viresh KUMAR @ 2010-03-03 5:07 ` Viresh KUMAR 2010-03-11 20:18 ` [PATCH 10/11] ST SPEAr: Added default configuration files for SPEAr machines Linus Walleij 1 sibling, 0 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-03 5:07 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Viresh Kumar <viresh.kumar@st.com> --- Documentation/arm/SPEAr/overview.txt | 60 ++++++++++++++++++++++++++++++++++ MAINTAINERS | 27 +++++++++++++++ 2 files changed, 87 insertions(+), 0 deletions(-) create mode 100644 Documentation/arm/SPEAr/overview.txt diff --git a/Documentation/arm/SPEAr/overview.txt b/Documentation/arm/SPEAr/overview.txt new file mode 100644 index 0000000..253a35c --- /dev/null +++ b/Documentation/arm/SPEAr/overview.txt @@ -0,0 +1,60 @@ + SPEAr ARM Linux Overview + ========================== + +Introduction +------------ + + SPEAr (Structured Processor Enhanced Architecture). + weblink : http://www.st.com/spear + + The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are + supported by the 'spear' platform of ARM Linux. Currently SPEAr300, + SPEAr310, SPEAr320 and SPEAr600 SOCs are supported. Support for the SPEAr13XX + series is in progress. + + Hierarchy in SPEAr is as follows: + + SPEAr (Platform) + - SPEAr3XX (3XX SOC series, based on ARM9) + - SPEAr300 (SOC) + - SPEAr300_EVB (Evaluation Board) + - SPEAr310 (SOC) + - SPEAr310_EVB (Evaluation Board) + - SPEAr320 (SOC) + - SPEAr320_EVB (Evaluation Board) + - SPEAr6XX (6XX SOC series, based on ARM9) + - SPEAr600 (SOC) + - SPEAr600_EVB (Evaluation Board) + - SPEAr13XX (13XX SOC series, based on ARM CORTEXA9) + - SPEAr1300 (SOC) + + Configuration + ------------- + + A generic configuration is provided for each machine, and can be used as the + default by + make spear600_defconfig + make spear300_defconfig + make spear310_defconfig + make spear320_defconfig + + Layout + ------ + + The common files for multiple machine families (SPEAr3XX, SPEAr6XX and + SPEAr13XX) are located in the platform code contained in arch/arm/plat-spear + with headers in plat/. + + Each machine series have a directory with name arch/arm/mach-spear followed by + series name. Like mach-spear3xx, mach-spear6xx and mach-spear13xx. + + Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for + spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine + specific files, like spear300.c, spear310.c, spear320.c and spear600.c. + mach-spear* also contains board specific files for each machine type. + + + Document Author + --------------- + + Viresh Kumar, (c) 2010 ST Microelectronics diff --git a/MAINTAINERS b/MAINTAINERS index 2533fc4..8f11d92 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5078,6 +5078,33 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-next-2.6.git S: Maintained F: arch/sparc/ +SPEAR PLATFORM SUPPORT +M: Viresh Kumar <viresh.kumar@st.com> +W: http://www.st.com/spear +S: Maintained +F: arch/arm/plat-spear/ + +SPEAR3XX MACHINE SUPPORT +M: Viresh Kumar <viresh.kumar@st.com> +W: http://www.st.com/spear +S: Maintained +F: arch/arm/mach-spear3xx/ + +SPEAR6XX MACHINE SUPPORT +M: Rajeev Kumar <rajeev-dlh.kumar@st.com> +W: http://www.st.com/spear +S: Maintained +F: arch/arm/mach-spear6xx/ + +SPEAR CLOCK FRAMEWORK SUPPORT +M: Viresh Kumar <viresh.kumar@st.com> +W: http://www.st.com/spear +S: Maintained +F: arch/arm/mach-spear*/clock.c +F: arch/arm/mach-spear*/include/mach/clkdev.h +F: arch/arm/plat-spear/clock.c +F: arch/arm/plat-spear/include/plat/clock.h and clkdev.h + SPECIALIX IO8+ MULTIPORT SERIAL CARD DRIVER M: Roger Wolff <R.E.Wolff@BitWizard.nl> S: Supported -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH 10/11] ST SPEAr: Added default configuration files for SPEAr machines 2010-03-03 5:07 ` [PATCH 10/11] ST SPEAr: Added default configuration files for SPEAr machines Viresh KUMAR 2010-03-03 5:07 ` [PATCH 11/11] ST SPEAr: Updated Maintainers and added Documentation/arm/SPEAr Viresh KUMAR @ 2010-03-11 20:18 ` Linus Walleij 2010-03-11 20:26 ` Russell King - ARM Linux 2010-03-12 4:12 ` Viresh KUMAR 1 sibling, 2 replies; 51+ messages in thread From: Linus Walleij @ 2010-03-11 20:18 UTC (permalink / raw) To: linux-arm-kernel 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: > (...) > +CONFIG_HAVE_GENERIC_DMA_COHERENT=y Not specifically related to this defconfig because hundreds of defconfigs use this, but HAVE_GENERIC_DMA_COHERENT is not used in anything but a few Kconfig files, all just defining it. No single Makefile, #ifdef or anything else seems to be using this, so what is it for?? I can't find any use even if I go back to kernel 2.6.11 on LXR. > (...) > +# > +# Networking options > +# > +CONFIG_PACKET=y > +CONFIG_PACKET_MMAP=y > (...) You're obviously doing a lot of networking in this system, but the machine has no network interfaces defined... yet, I suppose, so if it's coming, keep it. (Or are you running PPP over your UART?) > +# > +# Bluetooth device drivers > +# > +CONFIG_BT_HCIUART=m > +CONFIG_BT_HCIUART_H4=y > +CONFIG_BT_HCIUART_BCSP=y > (...) Same here, make sure you're really going to have Bluetooth on this device. > +# > +# SCSI device support > +# > +# CONFIG_RAID_ATTRS is not set > +CONFIG_SCSI=m > +CONFIG_SCSI_DMA=y Same issue here. > +# > +# Userland interfaces > +# > +CONFIG_INPUT_MOUSEDEV=y > +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set > +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 > +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 > +CONFIG_INPUT_JOYDEV=m > +CONFIG_INPUT_EVDEV=y > +# CONFIG_INPUT_EVBUG is not set ...and here > +CONFIG_INPUT_TOUCHSCREEN=y > +# CONFIG_TOUCHSCREEN_AD7879 is not set > +# CONFIG_TOUCHSCREEN_DYNAPRO is not set > +# CONFIG_TOUCHSCREEN_FUJITSU is not set > +CONFIG_TOUCHSCREEN_GUNZE=m Aha OK where is that connected? > +CONFIG_EXT3_FS=m Good choice, nowadays I think you should even consider EXT4. But you have no block device for it in the platform... Again I guess it's a runner-up, just checking. > +CONFIG_FS_POSIX_ACL=y This is rarely used in embedded. > +CONFIG_QUOTA=y This is also rare in embedded. > +# > +# CD-ROM/DVD Filesystems > +# > (...) > +# > +# DOS/FAT/NT Filesystems > +# Again there is no corresponding block device for this. (Just checkin.) > +CONFIG_CRAMFS=m Is cramfs really useful as a module? Enlighten me. > +CONFIG_NETWORK_FILESYSTEMS=y > +CONFIG_NFS_FS=m > +CONFIG_NFS_V3=y > (...) On what network interface? > +# > +# Partition Types > +# > +CONFIG_PARTITION_ADVANCED=y > +# CONFIG_ACORN_PARTITION is not set > +CONFIG_OSF_PARTITION=y > +# CONFIG_AMIGA_PARTITION is not set > +# CONFIG_ATARI_PARTITION is not set > +CONFIG_MAC_PARTITION=y I doubt that you need these weird partition types. > +CONFIG_NLS=y > +CONFIG_NLS_DEFAULT="utf8" > +CONFIG_NLS_CODEPAGE_437=y I usually only keep 437 but if you need the others, sure. > +CONFIG_SECURITY_SELINUX=y This is some serious stuff to compile into an embedded system, make sure you really need it. > +# > +# Random Number Generation > +# > +CONFIG_CRYPTO_ANSI_CPRNG=m > +CONFIG_CRYPTO_HW=y Do you have crypto HW? It's not in the machine right now atleast. Comments repeat for the other configs, I just wanna make sure you're really gonna use all of this so that your kernel is not too big for no good reason. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 10/11] ST SPEAr: Added default configuration files for SPEAr machines 2010-03-11 20:18 ` [PATCH 10/11] ST SPEAr: Added default configuration files for SPEAr machines Linus Walleij @ 2010-03-11 20:26 ` Russell King - ARM Linux 2010-03-12 4:12 ` Viresh KUMAR 1 sibling, 0 replies; 51+ messages in thread From: Russell King - ARM Linux @ 2010-03-11 20:26 UTC (permalink / raw) To: linux-arm-kernel On Thu, Mar 11, 2010 at 09:18:40PM +0100, Linus Walleij wrote: > 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: > > (...) > > +CONFIG_HAVE_GENERIC_DMA_COHERENT=y > > Not specifically related to this defconfig because hundreds of defconfigs > use this, but HAVE_GENERIC_DMA_COHERENT is not used in anything but > a few Kconfig files, all just defining it. No single Makefile, #ifdef > or anything > else seems to be using this, so what is it for?? I can't find any use even if I > go back to kernel 2.6.11 on LXR. Err... drivers/base/Makefile:obj-$(CONFIG_HAVE_GENERIC_DMA_COHERENT) += dma-coherent.o include/asm-generic/dma-coherent.h:#ifdef CONFIG_HAVE_GENERIC_DMA_COHERENT ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 10/11] ST SPEAr: Added default configuration files for SPEAr machines 2010-03-11 20:18 ` [PATCH 10/11] ST SPEAr: Added default configuration files for SPEAr machines Linus Walleij 2010-03-11 20:26 ` Russell King - ARM Linux @ 2010-03-12 4:12 ` Viresh KUMAR 1 sibling, 0 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-12 4:12 UTC (permalink / raw) To: linux-arm-kernel On 3/12/2010 1:48 AM, Linus Walleij wrote: > 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: >> (...) >> +CONFIG_HAVE_GENERIC_DMA_COHERENT=y > > Not specifically related to this defconfig because hundreds of defconfigs > use this, but HAVE_GENERIC_DMA_COHERENT is not used in anything but > a few Kconfig files, all just defining it. No single Makefile, #ifdef > or anything > else seems to be using this, so what is it for?? I can't find any use even if I > go back to kernel 2.6.11 on LXR. > >> (...) >> +# >> +# Networking options >> +# >> +CONFIG_PACKET=y >> +CONFIG_PACKET_MMAP=y >> (...) > > You're obviously doing a lot of networking in this system, but the machine > has no network interfaces defined... yet, I suppose, so if it's coming, > keep it. (Or are you running PPP over your UART?) > >> +# >> +# Bluetooth device drivers >> +# >> +CONFIG_BT_HCIUART=m >> +CONFIG_BT_HCIUART_H4=y >> +CONFIG_BT_HCIUART_BCSP=y >> (...) > > Same here, make sure you're really going to > have Bluetooth on this device. > >> +# >> +# SCSI device support >> +# >> +# CONFIG_RAID_ATTRS is not set >> +CONFIG_SCSI=m >> +CONFIG_SCSI_DMA=y > > Same issue here. > >> +# >> +# Userland interfaces >> +# >> +CONFIG_INPUT_MOUSEDEV=y >> +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set >> +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 >> +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 >> +CONFIG_INPUT_JOYDEV=m >> +CONFIG_INPUT_EVDEV=y >> +# CONFIG_INPUT_EVBUG is not set > > ...and here > >> +CONFIG_INPUT_TOUCHSCREEN=y >> +# CONFIG_TOUCHSCREEN_AD7879 is not set >> +# CONFIG_TOUCHSCREEN_DYNAPRO is not set >> +# CONFIG_TOUCHSCREEN_FUJITSU is not set >> +CONFIG_TOUCHSCREEN_GUNZE=m > > Aha OK where is that connected? > >> +CONFIG_EXT3_FS=m > > Good choice, nowadays I think you should even consider EXT4. > But you have no block device for it in the platform... > Again I guess it's a runner-up, just checking. > >> +CONFIG_FS_POSIX_ACL=y > > This is rarely used in embedded. > >> +CONFIG_QUOTA=y > > This is also rare in embedded. > >> +# >> +# CD-ROM/DVD Filesystems >> +# >> (...) >> +# >> +# DOS/FAT/NT Filesystems >> +# > > Again there is no corresponding block device for this. > (Just checkin.) > >> +CONFIG_CRAMFS=m > > Is cramfs really useful as a module? > Enlighten me. > >> +CONFIG_NETWORK_FILESYSTEMS=y >> +CONFIG_NFS_FS=m >> +CONFIG_NFS_V3=y >> (...) > > On what network interface? > >> +# >> +# Partition Types >> +# >> +CONFIG_PARTITION_ADVANCED=y >> +# CONFIG_ACORN_PARTITION is not set >> +CONFIG_OSF_PARTITION=y >> +# CONFIG_AMIGA_PARTITION is not set >> +# CONFIG_ATARI_PARTITION is not set >> +CONFIG_MAC_PARTITION=y > > I doubt that you need these weird partition types. > >> +CONFIG_NLS=y >> +CONFIG_NLS_DEFAULT="utf8" >> +CONFIG_NLS_CODEPAGE_437=y > > I usually only keep 437 but if you need the others, sure. > >> +CONFIG_SECURITY_SELINUX=y > > This is some serious stuff to compile into an embedded system, > make sure you really need it. > >> +# >> +# Random Number Generation >> +# >> +CONFIG_CRYPTO_ANSI_CPRNG=m >> +CONFIG_CRYPTO_HW=y > > Do you have crypto HW? It's not in the machine right now atleast. > > Comments repeat for the other configs, I just wanna make sure you're > really gonna use all of this so that your kernel is not too big for no good > reason. > Linus, I will remove all unwanted parts from defconfigs. viresh. ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family 2010-03-03 5:07 ` [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family Viresh KUMAR 2010-03-03 5:07 ` [PATCH 08/11] ST SPEAr: Added source files for SPEAr6xx " Viresh KUMAR @ 2010-03-09 6:46 ` Linus Walleij 2010-03-09 7:05 ` Viresh KUMAR 2010-03-11 10:41 ` Russell King - ARM Linux 1 sibling, 2 replies; 51+ messages in thread From: Linus Walleij @ 2010-03-09 6:46 UTC (permalink / raw) To: linux-arm-kernel Hi Viresh, some smallish comments... 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: > (skip some stuff that looks OK...) > diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c > new file mode 100644 > index 0000000..f529d74 > --- /dev/null > +++ b/arch/arm/mach-spear3xx/spear3xx.c > @@ -0,0 +1,118 @@ > +/* > + * arch/arm/mach-spear3xx/spear3xx.c > + * > + * SPEAr3XX machines common source file > + * > + * Copyright (C) 2009 ST Microelectronics > + * Viresh Kumar<viresh.kumar@st.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#include <linux/types.h> > +#include <linux/ptrace.h> > +#include <linux/io.h> > +#include <asm/hardware/vic.h> > +#include <asm/irq.h> > +#include <asm/mach/arch.h> > +#include <mach/irqs.h> > +#include <mach/generic.h> > +#include <mach/spear.h> > +#include <plat/gpt.h> > + > +/* Add spear3xx machines common devices here */ > +/* uart device registeration */ > +struct amba_device uart_device = { > + ? ? ? .dev = { > + ? ? ? ? ? ? ? .init_name = "uart", > + ? ? ? ? ? ? ? }, > + ? ? ? .res = { > + ? ? ? ? ? ? ? .start = SPEAR3XX_ICM1_UART_BASE, > + ? ? ? ? ? ? ? .end = SPEAR3XX_ICM1_UART_BASE + SPEAR3XX_ICM1_UART_SIZE - 1, > + ? ? ? ? ? ? ? .flags = IORESOURCE_MEM, > + ? ? ? ? ? ? ? }, > + ? ? ? .irq = {IRQ_UART, NO_IRQ}, > + ? ? ? .periphid = 0x00041011, > +}; You're hardcoding the PrimeCell ID to the ARM version, but I suspect you have an ST derivate with some additional features. If you look in the PL011 driver in drivers/serial/amba-pl011.c you will probably recognize the modified PrimeCell IDs for vendor 0x80 (VENDOR_ST) and I think you might rather need to patch this file with your new periphid and possibly even implement some new extensions (if there are any). What value is actually in the ID registers of your cell? (Just check in some debugger or simply printk() it...) Apart from this the patch looks OK to me. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family 2010-03-09 6:46 ` [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family Linus Walleij @ 2010-03-09 7:05 ` Viresh KUMAR 2010-03-10 5:15 ` Linus Walleij 2010-03-11 10:41 ` Russell King - ARM Linux 1 sibling, 1 reply; 51+ messages in thread From: Viresh KUMAR @ 2010-03-09 7:05 UTC (permalink / raw) To: linux-arm-kernel Hi Linus, On 3/9/2010 12:16 PM, Linus Walleij wrote: > Hi Viresh, > some smallish comments... > > 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: > >> (skip some stuff that looks OK...) >> diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c >> new file mode 100644 >> index 0000000..f529d74 >> --- /dev/null >> + .res = { >> + .start = SPEAR3XX_ICM1_UART_BASE, >> + .end = SPEAR3XX_ICM1_UART_BASE + SPEAR3XX_ICM1_UART_SIZE - 1, >> + .flags = IORESOURCE_MEM, >> + }, >> + .irq = {IRQ_UART, NO_IRQ}, >> + .periphid = 0x00041011, >> +}; > > You're hardcoding the PrimeCell ID to the ARM version, but I suspect > you have an ST derivate with some additional features. If you look in > the PL011 driver in drivers/serial/amba-pl011.c you will probably recognize > the modified PrimeCell IDs for vendor 0x80 (VENDOR_ST) and I think > you might rather need to patch this file with your new periphid and > possibly even implement some new extensions (if there are any). > > What value is actually in the ID registers of your cell? (Just > check in some debugger or simply printk() it...) > > Apart from this the patch looks OK to me. > Actually PL011 is customized by ST's nomadik platform. And hence above is true for nomadik only. We are using ARM's version of PL011 without any customization over it and so id for our case is still 0x00041011. regards, viresh kumar. ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family 2010-03-09 7:05 ` Viresh KUMAR @ 2010-03-10 5:15 ` Linus Walleij 2010-03-10 6:10 ` viresh kumar 0 siblings, 1 reply; 51+ messages in thread From: Linus Walleij @ 2010-03-10 5:15 UTC (permalink / raw) To: linux-arm-kernel 2010/3/9 Viresh KUMAR <viresh.kumar@st.com>: > On 3/9/2010 12:16 PM, Linus Walleij wrote: >> Hi Viresh, >>> (...) >>> + ? ? ? .irq = {IRQ_UART, NO_IRQ}, >>> + ? ? ? .periphid = 0x00041011, >>> +}; >> >> You're hardcoding the PrimeCell ID to the ARM version, (...) > > Actually PL011 is customized by ST's nomadik platform. And hence above > is true for nomadik only. We are using ARM's version of PL011 without > any customization over it and so id for our case is still 0x00041011. OK then you can probably just delete the .periphid line, the only thing that will do is to override the number found in the ID registers with the same number. If this doesn't work you certainly have a modified version anyway. Linus ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family 2010-03-10 5:15 ` Linus Walleij @ 2010-03-10 6:10 ` viresh kumar 0 siblings, 0 replies; 51+ messages in thread From: viresh kumar @ 2010-03-10 6:10 UTC (permalink / raw) To: linux-arm-kernel Linus, On Wed, Mar 10, 2010 at 10:45 AM, Linus Walleij <linus.ml.walleij@gmail.com> wrote: > 2010/3/9 Viresh KUMAR <viresh.kumar@st.com>: > >> On 3/9/2010 12:16 PM, Linus Walleij wrote: >>> Hi Viresh, >>>> (...) >>>> + ? ? ? .irq = {IRQ_UART, NO_IRQ}, >>>> + ? ? ? .periphid = 0x00041011, >>>> +}; >>> >>> You're hardcoding the PrimeCell ID to the ARM version, (...) >> >> Actually PL011 is customized by ST's nomadik platform. And hence above >> is true for nomadik only. We are using ARM's version of PL011 without >> any customization over it and so id for our case is still 0x00041011. > > OK then you can probably just delete the .periphid line, the only thing that > will do is to override the number found in the ID registers with the same > number. If this doesn't work you certainly have a modified version anyway. > OK. viresh. ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family 2010-03-09 6:46 ` [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family Linus Walleij 2010-03-09 7:05 ` Viresh KUMAR @ 2010-03-11 10:41 ` Russell King - ARM Linux 2010-03-12 5:19 ` Viresh KUMAR 1 sibling, 1 reply; 51+ messages in thread From: Russell King - ARM Linux @ 2010-03-11 10:41 UTC (permalink / raw) To: linux-arm-kernel On Tue, Mar 09, 2010 at 07:46:10AM +0100, Linus Walleij wrote: > > +struct amba_device uart_device = { > > + ? ? ? .dev = { > > + ? ? ? ? ? ? ? .init_name = "uart", > > + ? ? ? ? ? ? ? }, > > + ? ? ? .res = { > > + ? ? ? ? ? ? ? .start = SPEAR3XX_ICM1_UART_BASE, > > + ? ? ? ? ? ? ? .end = SPEAR3XX_ICM1_UART_BASE + SPEAR3XX_ICM1_UART_SIZE - 1, > > + ? ? ? ? ? ? ? .flags = IORESOURCE_MEM, > > + ? ? ? ? ? ? ? }, > > + ? ? ? .irq = {IRQ_UART, NO_IRQ}, > > + ? ? ? .periphid = 0x00041011, > > +}; > > You're hardcoding the PrimeCell ID to the ARM version, but I suspect > you have an ST derivate with some additional features. If you look in > the PL011 driver in drivers/serial/amba-pl011.c you will probably recognize > the modified PrimeCell IDs for vendor 0x80 (VENDOR_ST) and I think > you might rather need to patch this file with your new periphid and > possibly even implement some new extensions (if there are any). > > What value is actually in the ID registers of your cell? (Just > check in some debugger or simply printk() it...) There is no need to specify the ID when the device provides it - in fact the code will override you by reading the ID from the device if it finds it. The only reason to explicitly provide one is for the very early Primecell devices which didn't implement the ID scheme - such as PL010. ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family 2010-03-11 10:41 ` Russell King - ARM Linux @ 2010-03-12 5:19 ` Viresh KUMAR 0 siblings, 0 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-12 5:19 UTC (permalink / raw) To: linux-arm-kernel On 3/11/2010 4:11 PM, Russell King - ARM Linux wrote: > On Tue, Mar 09, 2010 at 07:46:10AM +0100, Linus Walleij wrote: >>> +struct amba_device uart_device = { >>> + .dev = { >>> + .init_name = "uart", >>> + }, >>> + .res = { >>> + .start = SPEAR3XX_ICM1_UART_BASE, >>> + .end = SPEAR3XX_ICM1_UART_BASE + SPEAR3XX_ICM1_UART_SIZE - 1, >>> + .flags = IORESOURCE_MEM, >>> + }, >>> + .irq = {IRQ_UART, NO_IRQ}, >>> + .periphid = 0x00041011, >>> +}; >> >> You're hardcoding the PrimeCell ID to the ARM version, but I suspect >> you have an ST derivate with some additional features. If you look in >> the PL011 driver in drivers/serial/amba-pl011.c you will probably recognize >> the modified PrimeCell IDs for vendor 0x80 (VENDOR_ST) and I think >> you might rather need to patch this file with your new periphid and >> possibly even implement some new extensions (if there are any). >> >> What value is actually in the ID registers of your cell? (Just >> check in some debugger or simply printk() it...) > > There is no need to specify the ID when the device provides it - in fact > the code will override you by reading the ID from the device if it finds > it. The only reason to explicitly provide one is for the very early > Primecell devices which didn't implement the ID scheme - such as PL010. > It is Removed. ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 06/11] ST SPEAr: Added source files for SPEAr platform 2010-03-03 5:07 ` [PATCH 06/11] ST SPEAr: Added source files for SPEAr platform Viresh KUMAR 2010-03-03 5:07 ` [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family Viresh KUMAR @ 2010-03-11 11:22 ` Linus Walleij 1 sibling, 0 replies; 51+ messages in thread From: Linus Walleij @ 2010-03-11 11:22 UTC (permalink / raw) To: linux-arm-kernel Hi Viresh, I'm working my way through the patch set, be patient :) 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: > (...) > diff --git a/arch/arm/plat-spear/gpt.c b/arch/arm/plat-spear/gpt.c > new file mode 100644 > index 0000000..3b16360 > --- /dev/null > +++ b/arch/arm/plat-spear/gpt.c > @@ -0,0 +1,537 @@ > +/* > + * arch/arm/plat-spear/gpt.c As mentioned I prefer that you merge this file into the timer.c file and remove the extra .h interface totally. Also of course refactor to take into account that it's one file only. > + * > + * ST GPT Timer driver, based on omap's dmtimer.c > + * > + * Copyright (C) 2009 ST Microelectronics > + * Shiraz Hashim<shiraz.hashim@st.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#include <linux/clk.h> > +#include <linux/errno.h> > +#include <linux/init.h> > +#include <linux/io.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/spinlock.h> > +#include <mach/irqs.h> > +#include <mach/spear.h> > +#include <plat/gpt.h> > + > +static const char *src_clk_con_id[] __initdata = { > + ? ? ? "pll3_48m_clk", > + ? ? ? "pll1_clk", > + ? ? ? NULL > +}; > + > +static struct clk *spear_source_clocks[2]; > +static struct spear_timer *spear_timers; > +static int spear_timer_count; > +static spinlock_t spear_timer_lock; > + > +/* > + * static helper functions > + */ > +static inline u16 spear_timer_read_reg(struct spear_timer *timer, u32 reg) > +{ > + ? ? ? return readw(timer->io_base + (reg & 0xff)); > +} > + > +static inline void spear_timer_write_reg(struct spear_timer *timer, u32 reg, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? u16 value) > +{ > + ? ? ? writew(value, timer->io_base + (reg & 0xff)); > +} I usually just have raw writew() and skip all this extra abstraction in my code, but it's a matter of taste so if you like it, keep it. > + > +static void spear_timer_reset(struct spear_timer *timer) > +{ > + > + ? ? ? spear_timer_write_reg(timer, GPT_CTRL_OFF, 0x0); > + ? ? ? spear_timer_write_reg(timer, GPT_LOAD_OFF, 0x0); > + ? ? ? spear_timer_write_reg(timer, GPT_INT_OFF, GPT_STATUS_MATCH); > + ? ? ? timer->prescaler = 0; > +} > + > +static void spear_timer_prepare(struct spear_timer *timer) > +{ > + ? ? ? spear_timer_enable(timer); > + ? ? ? spear_timer_reset(timer); > +} > + > +/* functions exported for application */ > + > +/** > + * spear_timer_enable - enable a timer > + * @timer: timer > + * > + * This API enables the functional clock of the timer > + */ > +int spear_timer_enable(struct spear_timer *timer) > +{ > + ? ? ? if (!timer) > + ? ? ? ? ? ? ? return -ENODEV; > + > + ? ? ? if (timer->enabled) > + ? ? ? ? ? ? ? return -EINVAL; > + > + ? ? ? clk_enable(timer->fclk); > + > + ? ? ? timer->enabled = 1; > + > + ? ? ? return 0; > +} > + > +/** > + * spear_timer_disable - disables timer > + * @timer: timer > + * > + * The API disables the functional clock of the timer > + */ > +int spear_timer_disable(struct spear_timer *timer) > +{ > + ? ? ? if (!timer) > + ? ? ? ? ? ? ? return -ENODEV; > + > + ? ? ? if (!timer->enabled) > + ? ? ? ? ? ? ? return -EINVAL; > + > + ? ? ? clk_disable(timer->fclk); > + > + ? ? ? timer->enabled = 0; > + > + ? ? ? return 0; > +} > + > +/** > + * spear_timer_request - request for a timer > + * > + * This API returns a timer which is available, returns NULL if none is > + * available > + */ > +struct spear_timer *spear_timer_request(void) > +{ > + ? ? ? struct spear_timer *timer = NULL; > + ? ? ? unsigned long flags; > + ? ? ? int i; > + > + ? ? ? spin_lock_irqsave(&spear_timer_lock, flags); > + > + ? ? ? for (i = 0; i < spear_timer_count; i++) { > + ? ? ? ? ? ? ? if (spear_timers[i].reserved) > + ? ? ? ? ? ? ? ? ? ? ? continue; > + > + ? ? ? ? ? ? ? timer = &spear_timers[i]; > + ? ? ? ? ? ? ? timer->reserved = 1; I forgot to mention that if .reserved can only have the values 0 and 1, the chances are big that you should turn that member of struct spear_timer into a bool instead and use false/true as values. > + ? ? ? ? ? ? ? break; > + ? ? ? } > + > + ? ? ? spin_unlock_irqrestore(&spear_timer_lock, flags); > + > + ? ? ? if (timer != NULL) > + ? ? ? ? ? ? ? spear_timer_prepare(timer); > + > + ? ? ? return timer; > +} > +EXPORT_SYMBOL(spear_timer_request); > + > +/** > + * spear_timer_request_specific - request for a specific timer > + * @id: timer id requested, 1 onwards > + * > + * This API returns specific timer which is requested, returns NULL if it is > + * not available. > + */ > +struct spear_timer *spear_timer_request_specific(int id) I don't see the need for this functions. Are not all timers the same? If the timers are hardwired for specific purposes, as in they have some extra hardware routing of their output,, this should rather show up in the API. Again I think moving this into timer.c will solve the problem. > +{ > + ? ? ? struct spear_timer *timer; > + ? ? ? unsigned long flags; > + > + ? ? ? spin_lock_irqsave(&spear_timer_lock, flags); > + > + ? ? ? if (id < 0 || id >= spear_timer_count || > + ? ? ? ? ? ? ? ? ? ? ? spear_timers[id].reserved) { > + ? ? ? ? ? ? ? spin_unlock_irqrestore(&spear_timer_lock, flags); > + ? ? ? ? ? ? ? printk(KERN_ERR "BUG: unable to get timer %d\n", id); > + dump_stack(); Is this really a bug...? You can easily see that say timer 2 can have been taken by the generic spear_timer_request() function. In that case, the raise of a BUG message is subject to calling order and implicit semantics, e.g. you require that all clients that require a certain timer issue their spear_timer_request_specific() before any calls to spear_request_timer() is issued. That's getting messy, at least it needs to documented. Again merging into timer.c will solve this (it will just go away). > + ? ? ? ? ? ? ? return NULL; > + ? ? ? } > + > + ? ? ? timer = &spear_timers[id]; > + ? ? ? timer->reserved = 1; > + ? ? ? spin_unlock_irqrestore(&spear_timer_lock, flags); > + > + ? ? ? spear_timer_prepare(timer); > + > + ? ? ? return timer; > +} > +EXPORT_SYMBOL(spear_timer_request_specific); > + > +/** > + * spear_timer_free - free the timer > + * @timer: timer which should be freed > + * > + * Applications should free the timer when not in use. The API also resets and > + * disables the timer clock > + */ > +int spear_timer_free(struct spear_timer *timer) > +{ > + ? ? ? if (!timer) > + ? ? ? ? ? ? ? return -ENODEV; > + > + ? ? ? WARN_ON(!timer->reserved); This is a bug. If spear_request_timer[_specific]() and spear_timer_free() are supposed to be called in pairs this warning message will always be printed. Or are you suggesting that clients should never ever release their clocks? > + > + ? ? ? spear_timer_reset(timer); > + ? ? ? spear_timer_disable(timer); > + > + ? ? ? timer->reserved = 0; > + > + ? ? ? return 0; > +} > +EXPORT_SYMBOL(spear_timer_free); > + > +/** > + * spear_timer_get_irq - get the irq number associated > + * @timer: return the irq number for this timer > + * > + * The application may require the irq associated with a timer to register it > + * with the OS interrupt framework. > + */ > +int spear_timer_get_irq(struct spear_timer *timer) > +{ > + ? ? ? return (timer) ? timer->irq : -ENODEV; > +} > +EXPORT_SYMBOL(spear_timer_get_irq); This is messy IMHO. If you really want to route interrupts from the timers away from the actual timer driver (which *should* be in this file only!) you need to register a new struct irq_chip for the timer array and register a callback along with the spear_request_timer[_specific]() function. If you look for the uses of struct irq_chip in the kernel you can find a lot of this hierarchical irq_chip:s, notice that they are used as abstract entities, an irq_chip does NOT have to map 1-to-1 to e.g. a PL190 VIC, they can be subrouters. > + > +/** > + * spear_timer_get_fclk - return the functional clock > + * @timer: timer for which fclk is required > + * > + * Returns the functional clock of the timer at which it is operating. > + * Functional clock represents the actual clock at which the timer is > + * operating. The count period depends on this clock > + */ > +struct clk *spear_timer_get_fclk(struct spear_timer *timer) > +{ > + ? ? ? if (!timer) > + ? ? ? ? ? ? ? return NULL; > + > + ? ? ? return timer->fclk; > +} > +EXPORT_SYMBOL(spear_timer_get_fclk); > + > +/** > + * spear_timer_start - start the timer operation > + * @timer: timer to start > + * > + * The timer shall start operating only after calling this API > + */ > +int spear_timer_start(struct spear_timer *timer) > +{ > + ? ? ? u16 val; > + > + ? ? ? if (!timer) > + ? ? ? ? ? ? ? return -ENODEV; > + > + ? ? ? val = spear_timer_read_reg(timer, GPT_CTRL_OFF); > + ? ? ? if (!(val & GPT_CTRL_ENABLE)) { > + ? ? ? ? ? ? ? val |= GPT_CTRL_ENABLE; > + ? ? ? ? ? ? ? spear_timer_write_reg(timer, GPT_CTRL_OFF, val); > + ? ? ? } > + > + ? ? ? return 0; > +} > +EXPORT_SYMBOL(spear_timer_start); > + > +/** > + * spear_timer_stop - stop the timer operation > + * @timer: timer to stop > + * > + * This API can be used to stop the timer operation > + */ > +int spear_timer_stop(struct spear_timer *timer) > +{ > + ? ? ? u16 val; > + > + ? ? ? if (!timer) > + ? ? ? ? ? ? ? return -ENODEV; > + > + ? ? ? val = spear_timer_read_reg(timer, GPT_CTRL_OFF); > + ? ? ? if (val & GPT_CTRL_ENABLE) { > + ? ? ? ? ? ? ? val &= ~GPT_CTRL_ENABLE; > + ? ? ? ? ? ? ? spear_timer_write_reg(timer, GPT_CTRL_OFF, val); > + ? ? ? } > + > + ? ? ? return 0; > +} > +EXPORT_SYMBOL(spear_timer_stop); > + > +/** > + * spear_timer_set_source - select the proper source clock > + * @timer: timer > + * @source: the clock cource > + * > + * source specifies the clock which has to be selected as the functional clock > + * of timer. The available choice are 48 MHz (PLL3) output or AHB clock. > + * > + */ > +int spear_timer_set_source(struct spear_timer *timer, int source) > +{ > + ? ? ? if (source < 0 || source >= 3) > + ? ? ? ? ? ? ? return -EINVAL; > + > + ? ? ? if (!timer) > + ? ? ? ? ? ? ? return -ENODEV; > + > + ? ? ? clk_disable(timer->fclk); > + ? ? ? clk_set_parent(timer->fclk, spear_source_clocks[source]); > + ? ? ? clk_enable(timer->fclk); > + ? ? ? return 0; > +} > +EXPORT_SYMBOL(spear_timer_set_source); So depending on what you want each timer can be clocked at two different frequencies. This is actually an argument *against* merging it into the timer.c file, because the run frequency of clock event drivers are expected to be fixed and static. But again, this depends on whether you use it or not. When you use it as clocksource / clock event, you should just set it to the highest possible frequency. However when power management comes into the picture, this becomes a more complicated question. So, are lower frequencies really used for anything? > + > +/** > + * spear_timer_set_load - program the count value of timer > + * @timer: timer > + * @autoreload: boolean, whether the count will be reloaded > + * @load: the actual count deciding the time period Append a comment satting that the value to reload will depend on the frequency of the parent PLL, because it does, right? > + * > + * The timer will be programmed as per the value in load. The time period will > + * depend on the clock and prescaler selected. > + */ > +int spear_timer_set_load(struct spear_timer *timer, int autoreload, > + ? ? ? ? ? ? ? u16 load) > +{ > + ? ? ? u16 val; > + > + ? ? ? if (!timer) > + ? ? ? ? ? ? ? return -ENODEV; > + > + ? ? ? val = spear_timer_read_reg(timer, GPT_CTRL_OFF); > + ? ? ? if (autoreload) > + ? ? ? ? ? ? ? val &= ~GPT_CTRL_MODE_AR; > + ? ? ? else > + ? ? ? ? ? ? ? val |= GPT_CTRL_MODE_AR; > + > + ? ? ? spear_timer_write_reg(timer, GPT_LOAD_OFF, load); > + ? ? ? spear_timer_write_reg(timer, GPT_CTRL_OFF, val); > + > + ? ? ? return 0; > +} > +EXPORT_SYMBOL(spear_timer_set_load); > + > +/** > + * spear_timer_set_load_start - program the count value of timer and start > + * @timer: timer > + * @autoreload: boolean, whether the count will be reloaded > + * @load: the actual count deciding the time period > + * > + * The timer will be programmed as per the value in load and the operation will > + * be started. > + */ > +int spear_timer_set_load_start(struct spear_timer *timer, int autoreload, > + ? ? ? ? ? ? ? u16 load) > +{ > + ? ? ? u16 val; > + > + ? ? ? if (!timer) > + ? ? ? ? ? ? ? return -ENODEV; > + > + ? ? ? val = spear_timer_read_reg(timer, GPT_CTRL_OFF); > + ? ? ? if (autoreload) > + ? ? ? ? ? ? ? val &= ~GPT_CTRL_MODE_AR; > + ? ? ? else > + ? ? ? ? ? ? ? val |= GPT_CTRL_MODE_AR; > + > + ? ? ? val |= GPT_CTRL_ENABLE; > + > + ? ? ? spear_timer_write_reg(timer, GPT_LOAD_OFF, load); > + ? ? ? spear_timer_write_reg(timer, GPT_CTRL_OFF, val); > + > + ? ? ? return 0; > +} > +EXPORT_SYMBOL(spear_timer_set_load_start); If you merge this into timer.c it becomes obvious that autoreload will be used for the MODE_PERIODIC and non-autoreload for the oneshot timer, and the abstraction goes away, so the timer driver will be a lot simpler to read. > + > +/** > + * spear_timer_match_irq - enable the match interrupt > + * @timer: timer > + * @enable: boolean, 1 for enable > + * > + * If application wants to enable the interrupt on count match then this API > + * should be called > + */ > +int spear_timer_match_irq(struct spear_timer *timer, int enable) > +{ > + ? ? ? u16 val; > + > + ? ? ? if (!timer) > + ? ? ? ? ? ? ? return -ENODEV; > + > + ? ? ? val = spear_timer_read_reg(timer, GPT_CTRL_OFF); > + ? ? ? if (enable) > + ? ? ? ? ? ? ? val |= GPT_CTRL_MATCH_INT; > + ? ? ? else > + ? ? ? ? ? ? ? val &= ~GPT_CTRL_MATCH_INT; > + ? ? ? spear_timer_write_reg(timer, GPT_CTRL_OFF, val); > + > + ? ? ? return 0; > +} > +EXPORT_SYMBOL(spear_timer_match_irq); Again, use an abstract struct irq_chip instead and you won't need all these kludges. > + > +/** > + * spear_timer_set_prescaler - set the prescaler for the timer > + * @timer: timer > + * @prescaler: the division factor to be applied on the src clk > + * > + * This API can be used to program the prescaler for the timer. Its value can > + * be from 1 to 8 signifying division by 2^prescaler > + */ > +int spear_timer_set_prescaler(struct spear_timer *timer, int prescaler) > +{ > + ? ? ? u16 val; > + > + ? ? ? if (!timer) > + ? ? ? ? ? ? ? return -ENODEV; > + > + ? ? ? val = spear_timer_read_reg(timer, GPT_CTRL_OFF); > + ? ? ? if (prescaler >= 0x00 && prescaler <= 0x08) { > + ? ? ? ? ? ? ? val &= 0xFFF0; > + ? ? ? ? ? ? ? val |= prescaler; > + ? ? ? } else { > + ? ? ? ? ? ? ? printk(KERN_ERR "Invalid prescaler\n"); > + ? ? ? } > + > + ? ? ? timer->prescaler = val & 0xF; > + ? ? ? spear_timer_write_reg(timer, GPT_CTRL_OFF, val); > + ? ? ? return 0; > +} > +EXPORT_SYMBOL(spear_timer_set_prescaler); Same comment here as for set_source(). > + > +/** > + * spear_timer_read_status - read the interrupt status > + * @timer: timer > + * > + * This API can be used to read the interrupt status of timer. Currently only > + * match interrupt, at offset 0, is part of this. > + */ > +int spear_timer_read_status(struct spear_timer *timer) > +{ > + ? ? ? u16 val; > + > + ? ? ? if (!timer) > + ? ? ? ? ? ? ? return -ENODEV; > + > + ? ? ? val = spear_timer_read_reg(timer, GPT_INT_OFF); > + > + ? ? ? return val; > +} > +EXPORT_SYMBOL(spear_timer_read_status); Goes away with struct irq_chip again. > + > +/** > + * spear_timer_clear_status - write to the interrupt status reg to clear > + * @timer: timer > + * @value: value to be written > + * > + * The API can be used to clear the match interrupt status by writing a value > + * 0. > + */ > +int spear_timer_clear_status(struct spear_timer *timer, u16 value) > +{ > + ? ? ? if (!timer) > + ? ? ? ? ? ? ? return -ENODEV; > + > + ? ? ? spear_timer_write_reg(timer, GPT_INT_OFF, value); > + ? ? ? return 0; > +} > +EXPORT_SYMBOL(spear_timer_clear_status); Goes away with struct irq_chip again. > + > +/** > + * spear_timer_read_counter - get the current count value > + * @timer: timer > + * > + * The API returns the current count value of the timer. One has to remember > + * that if the timer is operating on asynchronous clock source then there is a > + * probability that the application may get some junk count value. This is due > + * to the fact that the count register is being accessed by two independent > + * clock, one driving the timer (48MHz) and the other on which this register is > + * read (system AHB clock). For more details refer GPT Application note. > + */ > +int spear_timer_read_counter(struct spear_timer *timer) > +{ > + ? ? ? u16 val; > + > + ? ? ? if (!timer) > + ? ? ? ? ? ? ? return -ENODEV; > + > + ? ? ? val = spear_timer_read_reg(timer, GPT_COUNT_OFF); > + > + ? ? ? return val; > +} > +EXPORT_SYMBOL(spear_timer_read_counter); Used for the clocksource right? No other in-kernel user would be interested in this function. If you fold the driver into timer.c it goes away naturally, the driver for the clocksource just read and use this register. > + > +/** > + * spear_timer_active - is timer active > + * @timer: timer > + * > + * This API can be used to find whether a timer is already enabled and is > + * active i.e. it is under operation > + */ > +int spear_timer_active(struct spear_timer *timer) > +{ > + ? ? ? if (!timer) > + ? ? ? ? ? ? ? return 0; return -EINVAL, no? > + > + ? ? ? if (!timer->enabled) > + ? ? ? ? ? ? ? return 0; > + > + ? ? ? if (spear_timer_read_reg(timer, GPT_CTRL_OFF) & GPT_CTRL_ENABLE) > + ? ? ? ? ? ? ? return 1; These two if:s are counterintuitive, can't you just remove the .enabled field in the struct spear_timer and *only* rely on the GPT_CTRL_ENABLE bit in the GPT_CTRL register? This way there are two bits that are supposed to be either both 00 or both 11 and any 10 or 01 is a BUG() really. The only reason of having a shadow variable is if it takes a long time to read the register, which appears to not be the case. > + > + ? ? ? return 0; > +} > +EXPORT_SYMBOL(spear_timer_active); > + > +/** > + * spear_timer_init - initialize the set of timers > + * @timer: list of timers to be intialized > + * @count: number of timers supported in platform > + * > + * This API must not be called by user and it is called only once by the > + * platform specific intialization code. > + */ > +int __init spear_timer_init(struct spear_timer *timers, int count) > +{ > + ? ? ? struct spear_timer *timer; > + ? ? ? int i; > + ? ? ? int mtu; /* timer unit */ > + ? ? ? char dev_id[16]; > + > + ? ? ? spin_lock_init(&spear_timer_lock); > + > + ? ? ? spear_timers = timers; > + ? ? ? spear_timer_count = count; > + > + ? ? ? for (i = 0; src_clk_con_id[i] != NULL; i++) > + ? ? ? ? ? ? ? spear_source_clocks[i] = clk_get(NULL, src_clk_con_id[i]); > + > + ? ? ? for (i = 0; i < spear_timer_count; i++) { > + ? ? ? ? ? ? ? timer = &spear_timers[i]; Here, before ioremap you should request_mem_region(timer->phys_base, timer->phys_base + SZ_1K - 1); Make sure that call doesn't return NULL. > + ? ? ? ? ? ? ? timer->io_base = (void __iomem *)ioremap(timer->phys_base, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SZ_1K); > + ? ? ? ? ? ? ? if (!timer->io_base) { > + ? ? ? ? ? ? ? ? ? ? ? printk(KERN_ERR "BUG:ioremap failed for timer:%d\n", i); > + ? ? ? ? ? ? ? ? ? ? ? continue; Um... Make a proper error path. What about goto err_ioremap; ? > + ? ? ? ? ? ? ? } > + > + ? ? ? ? ? ? ? /* each mtu has 2 timers with same set of clocks */ > + ? ? ? ? ? ? ? mtu = i >> 1; > + > + ? ? ? ? ? ? ? sprintf(dev_id, "gpt%d", mtu); > + ? ? ? ? ? ? ? timer->fclk = clk_get_sys(dev_id, NULL); > + ? ? ? } > + > + ? ? ? return 0; > +} > diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c > new file mode 100644 > index 0000000..d89ac17 > --- /dev/null > +++ b/arch/arm/plat-spear/time.c > @@ -0,0 +1,197 @@ > +/* > + * arch/arm/plat-spear/time.c > + * > + * Copyright (C) 2009 ST Microelectronics > + * Shiraz Hashim<shiraz.hashim@st.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#include <linux/clk.h> > +#include <linux/clockchips.h> > +#include <linux/clocksource.h> > +#include <linux/err.h> > +#include <linux/init.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/time.h> > +#include <linux/irq.h> > +#include <asm/mach/time.h> > +#include <mach/irqs.h> > +#include <mach/hardware.h> > +#include <mach/spear.h> > +#include <mach/generic.h> > +#include <plat/gpt.h> > + > +static void clockevent_set_mode(enum clock_event_mode mode, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct clock_event_device *clk_event_dev); > +static int clockevent_next_event(unsigned long evt, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct clock_event_device *clk_event_dev); > + > +/* > + * Timer0 and Timer1 both belong to same mtu in cpu subbsystem. Further they > + * share same functional clock. Any change in one's functional clock will also > + * affect other timer. > + */ > +static struct spear_timer *spear_timer_clkevt; > +static struct spear_timer *spear_timer_clksrc; > + > +/* > + * Clock Source > + */ > +static cycle_t clocksource_read_cycles(struct clocksource *cs) > +{ > + ? ? ? return (cycle_t) spear_timer_read_counter(spear_timer_clksrc); > +} > + > +static struct clocksource clksrc = { > + ? ? ? .name = "clock source", > + ? ? ? .rating = 200, ? ? ? ? ?/* its a pretty decent clock */ > + ? ? ? .read = clocksource_read_cycles, > + ? ? ? .mask = 0xFFFF, ? ? ? ? /* 16 bits */ > + ? ? ? .mult = 0, ? ? ? ? ? ? ?/* to be computed */ > + ? ? ? .shift = 10, How is this number (10) decided? I ask because many people just copy something from some other platform. One algorithm you could consider is the clocksource_calc_mult_shift() function. > + ? ? ? .flags = CLOCK_SOURCE_IS_CONTINUOUS, > +}; > + > +static void spear_clocksource_init(void) > +{ > + ? ? ? static struct spear_timer *timer; > + ? ? ? u32 tick_rate; > + > + ? ? ? timer = spear_timer_request_specific(1); Why does this need exactly timer 1? Atleast the argument could be an enum GPT_TIMER_1, GPT_TIMER_2 etc. If this is some way to force the clocksource on a certain timer this also shows that gpt should be merged in here so we don't need strange interfaces or numbers like this. > + ? ? ? BUG_ON(timer == NULL); > + ? ? ? spear_timer_clksrc = timer; > + > + ? ? ? spear_timer_set_source(timer, SPEAR_TIMER_SRC_PLL3_CLK); > + ? ? ? spear_timer_set_prescaler(timer, GPT_CTRL_PRESCALER256); > + > + ? ? ? /* find out actual clock driving Timer */ > + ? ? ? tick_rate = clk_get_rate(spear_timer_get_fclk(timer)); > + ? ? ? tick_rate >>= timer->prescaler; > + > + ? ? ? spear_timer_set_load_start(timer, 1, 0xFFFF); /* 16 bit maximum */ > + > + ? ? ? clksrc.mult = > + ? ? ? ? ? ? ? clocksource_khz2mult((tick_rate / 1000), clksrc.shift); > + > + ? ? ? /* register the clocksource */ > + ? ? ? clocksource_register(&clksrc); > +} > + > +/* > +* Clock Event > +*/ > +static struct clock_event_device clkevt = { > + ? ? ? .name = "clock_event", > + ? ? ? .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, > + ? ? ? .set_mode = clockevent_set_mode, > + ? ? ? .set_next_event = clockevent_next_event, > + ? ? ? .shift = 20, Elaborate on why you choose 20. Comtemplate using clockevents_calc_mult_shift(). > +}; > + > +static void clockevent_set_mode(enum clock_event_mode mode, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct clock_event_device *clk_event_dev) > +{ > + ? ? ? u32 period; > + ? ? ? struct spear_timer *timer = spear_timer_clkevt; > + > + ? ? ? if (timer) > + ? ? ? ? ? ? ? return; > + > + ? ? ? spear_timer_stop(timer); > + > + ? ? ? switch (mode) { > + ? ? ? case CLOCK_EVT_MODE_PERIODIC: > + ? ? ? ? ? ? ? period = clk_get_rate(spear_timer_get_fclk(timer)) / HZ; > + ? ? ? ? ? ? ? period >>= timer->prescaler; > + > + ? ? ? ? ? ? ? spear_timer_match_irq(timer, 1); > + ? ? ? ? ? ? ? spear_timer_set_load_start(timer, 1, period); > + ? ? ? ? ? ? ? break; > + > + ? ? ? case CLOCK_EVT_MODE_ONESHOT: > + ? ? ? ? ? ? ? spear_timer_match_irq(timer, 1); > + ? ? ? ? ? ? ? break; > + > + ? ? ? case CLOCK_EVT_MODE_UNUSED: > + ? ? ? case CLOCK_EVT_MODE_SHUTDOWN: > + ? ? ? case CLOCK_EVT_MODE_RESUME: > + ? ? ? ? ? ? ? break; > + > + ? ? ? default: > + ? ? ? ? ? ? ? printk(KERN_ERR "BUG: Invalid mode requested\n"); What about using pr_err() and also BUG()? > + ? ? ? ? ? ? ? break; > + ? ? ? } > +} > + > +static int clockevent_next_event(unsigned long cycles, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct clock_event_device *clk_event_dev) > +{ > + ? ? ? spear_timer_set_load_start(spear_timer_clkevt, 0, (u16) cycles); > + > + ? ? ? return 0; > +} > + > +static irqreturn_t spear_timer_interrupt(int irq, void *dev_id) > +{ > + ? ? ? struct clock_event_device *evt = &clkevt; > + ? ? ? struct spear_timer *timer = (struct spear_timer *)dev_id; > + > + ? ? ? spear_timer_clear_status(timer, GPT_STATUS_MATCH); > + > + ? ? ? evt->event_handler(evt); > + > + ? ? ? return IRQ_HANDLED; > +} > + > +static struct irqaction spear_timer_irq = { > + ? ? ? .name = "gp_timer", > + ? ? ? .flags = IRQF_DISABLED | IRQF_TIMER, > + ? ? ? .handler = spear_timer_interrupt > +}; > + > +static void __init spear_clockevent_init(void) > +{ > + ? ? ? struct spear_timer *timer; > + ? ? ? u32 tick_rate; > + > + ? ? ? timer = spear_timer_request_specific(0); > + ? ? ? BUG_ON(timer == NULL); > + ? ? ? spear_timer_clkevt = timer; > + > + ? ? ? spear_timer_set_source(timer, SPEAR_TIMER_SRC_PLL3_CLK); > + ? ? ? spear_timer_set_prescaler(timer, GPT_CTRL_PRESCALER16); > + > + ? ? ? tick_rate = clk_get_rate(spear_timer_get_fclk(timer)); > + ? ? ? tick_rate >>= timer->prescaler; > + > + ? ? ? clkevt.mult = div_sc(tick_rate, NSEC_PER_SEC, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? clkevt.shift); > + ? ? ? clkevt.max_delta_ns = clockevent_delta2ns(0xfff0, > + ? ? ? ? ? ? ? ? ? ? ? &clkevt); > + ? ? ? clkevt.min_delta_ns = clockevent_delta2ns(3, &clkevt); > + > + ? ? ? clkevt.cpumask = cpumask_of(0); > + ? ? ? clockevents_register_device(&clkevt); > + > + ? ? ? spear_timer_irq.dev_id = (void *)timer; > + > + ? ? ? setup_irq(spear_timer_get_irq(timer), &spear_timer_irq); > + ? ? ? spear_timer_match_irq(timer, 1); > +} > + > +void __init spear_setup_timer(void) > +{ > + ? ? ? /* Initialize all General Purpose Timers */ > + ? ? ? spear_gpt_init(); > + > + ? ? ? spear_clockevent_init(); > + ? ? ? spear_clocksource_init(); > +} > + > +struct sys_timer spear_sys_timer = { > + ? ? ? .init = spear_setup_timer, > +}; Consider also adding a simple sched_clock() implementation or your scheduling and hrtimers will have tick granularity only, (not very highres...) look at examples in other archs like plat-omap. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines 2010-03-03 5:07 ` [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines Viresh KUMAR 2010-03-03 5:07 ` [PATCH 06/11] ST SPEAr: Added source files for SPEAr platform Viresh KUMAR @ 2010-03-11 7:00 ` Linus Walleij 2010-03-11 10:18 ` Shiraz HASHIM 2010-03-12 4:19 ` Viresh KUMAR 2010-03-11 10:28 ` Russell King - ARM Linux 2 siblings, 2 replies; 51+ messages in thread From: Linus Walleij @ 2010-03-11 7:00 UTC (permalink / raw) To: linux-arm-kernel 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: > Clock framework for SPEAr is based upon clkdev framework for ARM > (... clock tree definition looks OK to me ...) > diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c > new file mode 100755 > index 0000000..bdcae0c > --- /dev/null > +++ b/arch/arm/plat-spear/clock.c > @@ -0,0 +1,433 @@ > +/* > + * arch/arm/plat-spear/clock.c > + * > + * Clock framework for SPEAr platform > + * > + * Copyright (C) 2009 ST Microelectronics > + * Viresh Kumar<viresh.kumar@st.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#include <linux/bug.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/list.h> > +#include <linux/module.h> > +#include <linux/spinlock.h> > +#include <mach/misc_regs.h> > +#include <plat/clock.h> > + > +static DEFINE_SPINLOCK(clocks_lock); > +static LIST_HEAD(root_clks); > + > +static void propagate_rate(struct list_head *); > + > +static int generic_clk_enable(struct clk *clk) > +{ > + ? ? ? unsigned int val; > + > + ? ? ? if (!clk->en_reg) > + ? ? ? ? ? ? ? return -EFAULT; > + > + ? ? ? val = readl(clk->en_reg); > + ? ? ? if (unlikely(clk->flags & RESET_TO_ENABLE)) > + ? ? ? ? ? ? ? val &= ~(1 << clk->en_reg_bit); > + ? ? ? else > + ? ? ? ? ? ? ? val |= 1 << clk->en_reg_bit; > + ? ? ? writel(val, clk->en_reg); I don't understand one bit of this. What happens if the RESET_TO_ENABLE flag is set for the clock? The exact same bit is &-masked and then immediately |:ed to 1 again. Then it is written to the register. Practical effect: absolutely none. Is there a writel(val, clk->en_reg); missing from the unlikely() execution path? > + > + ? ? ? return 0; > +} > + > +static void generic_clk_disable(struct clk *clk) > +{ > + ? ? ? unsigned int val; > + > + ? ? ? if (!clk->en_reg) > + ? ? ? ? ? ? ? return; > + > + ? ? ? val = readl(clk->en_reg); > + ? ? ? if (unlikely(clk->flags & RESET_TO_ENABLE)) > + ? ? ? ? ? ? ? val |= 1 << clk->en_reg_bit; > + ? ? ? else > + ? ? ? ? ? ? ? val &= ~(1 << clk->en_reg_bit); Same issue here... > + > + ? ? ? writel(val, clk->en_reg); > +} > + > +/* generic clk ops */ > +static struct clkops generic_clkops = { > + ? ? ? .enable = generic_clk_enable, > + ? ? ? .disable = generic_clk_disable, > +}; > + > +/* > + * clk_enable - inform the system when the clock source should be running. > + * @clk: clock source > + * > + * If the clock can not be enabled/disabled, this should return success. > + * > + * Returns success (0) or negative errno. > + */ > +int clk_enable(struct clk *clk) > +{ > + ? ? ? unsigned long flags; > + ? ? ? int ret = 0; > + > + ? ? ? if (!clk || IS_ERR(clk)) > + ? ? ? ? ? ? ? return -EFAULT; > + > + ? ? ? spin_lock_irqsave(&clocks_lock, flags); > + ? ? ? if (clk->usage_count++ == 0) { Isnt if (++clk.>usage_count == 1) easier to understand, or is it just me? BTW doing this: clk->usage_count++; if (clk->usage_count == 1) will not use more memory, the compiler optimize this, so choose the version you think is most readable. If you think this is very readable, by all means keep it. > + ? ? ? ? ? ? ? if (clk->ops && clk->ops->enable) > + ? ? ? ? ? ? ? ? ? ? ? ret = clk->ops->enable(clk); > + ? ? ? } > + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags); > + > + ? ? ? return ret; > +} > +EXPORT_SYMBOL(clk_enable); > + > +/* > + * clk_disable - inform the system when the clock source is no longer required. > + * @clk: clock source > + * > + * Inform the system that a clock source is no longer required by > + * a driver and may be shut down. > + * > + * Implementation detail: if the clock source is shared between > + * multiple drivers, clk_enable() calls must be balanced by the > + * same number of clk_disable() calls for the clock source to be > + * disabled. > + */ > +void clk_disable(struct clk *clk) > +{ > + ? ? ? unsigned long flags; > + > + ? ? ? if (!clk || IS_ERR(clk)) > + ? ? ? ? ? ? ? return; > + > + ? ? ? WARN_ON(clk->usage_count == 0); > + > + ? ? ? spin_lock_irqsave(&clocks_lock, flags); > + ? ? ? if (--clk->usage_count == 0) { Same readability issue here. > + ? ? ? ? ? ? ? if (clk->ops && clk->ops->disable) > + ? ? ? ? ? ? ? ? ? ? ? clk->ops->disable(clk); > + ? ? ? } > + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags); > +} > +EXPORT_SYMBOL(clk_disable); > + > +/** > + * clk_get_rate - obtain the current clock rate (in Hz) for a clock source. > + * ? ? ? ? ? ? ?This is only valid once the clock source has been enabled. > + * @clk: clock source > + */ > +unsigned long clk_get_rate(struct clk *clk) > +{ > + ? ? ? unsigned long flags, rate; > + > + ? ? ? spin_lock_irqsave(&clocks_lock, flags); > + ? ? ? rate = clk->rate; > + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags); > + > + ? ? ? return rate; > +} > +EXPORT_SYMBOL(clk_get_rate); > + > +/** > + * clk_set_parent - set the parent clock source for this clock > + * @clk: clock source > + * @parent: parent clock source > + * > + * Returns success (0) or negative errno. > + */ > +int clk_set_parent(struct clk *clk, struct clk *parent) > +{ > + ? ? ? int i, found = 0, val = 0; > + ? ? ? unsigned long flags; > + > + ? ? ? if (!clk || IS_ERR(clk) || !parent || IS_ERR(parent)) > + ? ? ? ? ? ? ? return -EFAULT; > + ? ? ? if (clk->usage_count == 0) > + ? ? ? ? ? ? ? return -EBUSY; Why will the clk_set_parent() call fail if there are *no* users of the clock? Should it not be the other way around? Or what am I misunderstanding here? > + ? ? ? if (!clk->pclk_sel) > + ? ? ? ? ? ? ? return -EPERM; > + ? ? ? if (clk->pclk == parent) > + ? ? ? ? ? ? ? return 0; > + > + ? ? ? for (i = 0; i < clk->pclk_sel->pclk_count; i++) { > + ? ? ? ? ? ? ? if (clk->pclk_sel->pclk_info[i].pclk == parent) { > + ? ? ? ? ? ? ? ? ? ? ? found = 1; > + ? ? ? ? ? ? ? ? ? ? ? break; > + ? ? ? ? ? ? ? } > + ? ? ? } > + > + ? ? ? if (!found) > + ? ? ? ? ? ? ? return -EPERM; What about -ENODEV or so? (I don't know what people typically use for clocks that don't exist.) > + > + ? ? ? spin_lock_irqsave(&clocks_lock, flags); > + ? ? ? /* reflect parent change in hardware */ > + ? ? ? val = readl(clk->pclk_sel->pclk_sel_reg); > + ? ? ? val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift); > + ? ? ? val |= clk->pclk_sel->pclk_info[i].pclk_mask << clk->pclk_sel_shift; > + ? ? ? writel(val, clk->pclk_sel->pclk_sel_reg); > + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags); > + > + ? ? ? /* reflect parent change in software */ > + ? ? ? clk->recalc(clk); > + ? ? ? propagate_rate(&clk->children); > + ? ? ? return 0; > +} > +EXPORT_SYMBOL(clk_set_parent); > + > +/* registers clock in platform clock framework */ > +void clk_register(struct clk_lookup *cl) > +{ > + ? ? ? struct clk *clk = cl->clk; > + ? ? ? unsigned long flags; > + > + ? ? ? if (!clk || IS_ERR(clk)) > + ? ? ? ? ? ? ? return; > + > + ? ? ? spin_lock_irqsave(&clocks_lock, flags); > + > + ? ? ? INIT_LIST_HEAD(&clk->children); > + ? ? ? if (clk->flags & ALWAYS_ENABLED) > + ? ? ? ? ? ? ? clk->ops = NULL; > + ? ? ? else if (!clk->ops) > + ? ? ? ? ? ? ? clk->ops = &generic_clkops; > + > + ? ? ? /* root clock don't have any parents */ > + ? ? ? if (!clk->pclk && !clk->pclk_sel) { > + ? ? ? ? ? ? ? list_add(&clk->sibling, &root_clks); > + ? ? ? ? ? ? ? /* add clocks with only one parent to parent's children list */ > + ? ? ? } else if (clk->pclk && !clk->pclk_sel) { > + ? ? ? ? ? ? ? list_add(&clk->sibling, &clk->pclk->children); > + ? ? ? } else { > + ? ? ? ? ? ? ? /* add clocks with > 1 parent to 1st parent's children list */ > + ? ? ? ? ? ? ? list_add(&clk->sibling, > + ? ? ? ? ? ? ? ? ? ? ? ?&clk->pclk_sel->pclk_info[0].pclk->children); > + ? ? ? } > + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags); > + > + ? ? ? /* add clock to arm clockdev framework */ > + ? ? ? clkdev_add(cl); > +} > + > +/** > + * propagate_rate - recalculate and propagate all clocks in list head > + * > + * Recalculates all root clocks in list head, which if the clock's .recalc is > + * set correctly, should also propagate their rates. > + */ > +static void propagate_rate(struct list_head *lhead) > +{ > + ? ? ? struct clk *clkp, *_temp; > + > + ? ? ? list_for_each_entry_safe(clkp, _temp, lhead, sibling) { > + ? ? ? ? ? ? ? if (clkp->recalc) > + ? ? ? ? ? ? ? ? ? ? ? clkp->recalc(clkp); > + ? ? ? ? ? ? ? propagate_rate(&clkp->children); > + ? ? ? } > +} > + > +/* returns current programmed clocks clock info structure */ > +static struct pclk_info *pclk_info_get(struct clk *clk) > +{ > + ? ? ? unsigned int mask, i; > + ? ? ? unsigned long flags; > + ? ? ? struct pclk_info *info; > + > + ? ? ? spin_lock_irqsave(&clocks_lock, flags); > + ? ? ? mask = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift) > + ? ? ? ? ? ? ? ? ? ? ? & clk->pclk_sel->pclk_sel_mask; > + > + ? ? ? for (i = 0; i < clk->pclk_sel->pclk_count; i++) { > + ? ? ? ? ? ? ? if (clk->pclk_sel->pclk_info[i].pclk_mask == mask) > + ? ? ? ? ? ? ? ? ? ? ? info = &clk->pclk_sel->pclk_info[i]; > + ? ? ? } > + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags); > + > + ? ? ? return info; > +} > + > +/* > + * Set pclk as cclk's parent and add clock sibling node to current parents > + * children list > + */ > +static void change_parent(struct clk *cclk, struct clk *pclk) > +{ > + ? ? ? unsigned long flags; > + > + ? ? ? spin_lock_irqsave(&clocks_lock, flags); > + ? ? ? list_del(&cclk->sibling); > + ? ? ? list_add(&cclk->sibling, &pclk->children); > + > + ? ? ? cclk->pclk = pclk; > + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags); > +} > + > +/* > + * calculates current programmed rate of pll1 > + * > + * In normal mode > + * rate = (2 * M[15:8] * Fin)/(N * 2^P) > + * > + * In Dithered mode > + * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P) > + */ > +void pll1_clk_recalc(struct clk *clk) > +{ > + ? ? ? struct pll_clk_config *config = clk->private_data; > + ? ? ? unsigned int num = 2, den = 0, val, mode = 0; > + ? ? ? unsigned long flags; > + > + ? ? ? spin_lock_irqsave(&clocks_lock, flags); > + ? ? ? mode = (readl(config->mode_reg) >> PLL_MODE_SHIFT) & > + ? ? ? ? ? ? ? PLL_MODE_MASK; > + > + ? ? ? val = readl(config->cfg_reg); > + ? ? ? /* calculate denominator */ > + ? ? ? den = (val >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK; > + ? ? ? den = 1 << den; > + ? ? ? den *= (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK; > + > + ? ? ? /* calculate numerator & denominator */ > + ? ? ? if (!mode) { > + ? ? ? ? ? ? ? /* Normal mode */ > + ? ? ? ? ? ? ? num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK; > + ? ? ? } else { > + ? ? ? ? ? ? ? /* Dithered mode */ > + ? ? ? ? ? ? ? num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK; > + ? ? ? ? ? ? ? den *= 256; > + ? ? ? } > + > + ? ? ? clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000; > + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags); > +} > + > +/* calculates current programmed rate of ahb or apb bus */ > +void bus_clk_recalc(struct clk *clk) > +{ > + ? ? ? struct bus_clk_config *config = clk->private_data; > + ? ? ? unsigned int div; > + ? ? ? unsigned long flags; > + > + ? ? ? spin_lock_irqsave(&clocks_lock, flags); > + ? ? ? div = ((readl(config->reg) >> config->shift) & config->mask) + 1; > + ? ? ? clk->rate = (unsigned long)clk->pclk->rate / div; > + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags); > +} > + > +/* > + * calculates current programmed rate of auxiliary synthesizers > + * used by: UART, FIRDA > + * > + * Fout from synthesizer can be given from two equations: > + * Fout1 = (Fin * X/Y)/2 > + * Fout2 = Fin * X/Y > + * > + * Selection of eqn 1 or 2 is programmed in register > + */ > +void aux_clk_recalc(struct clk *clk) > +{ > + ? ? ? struct aux_clk_config *config = clk->private_data; > + ? ? ? struct pclk_info *pclk_info = NULL; > + ? ? ? unsigned int num = 1, den = 1, val, eqn; > + ? ? ? unsigned long flags; > + > + ? ? ? /* get current programmed parent */ > + ? ? ? pclk_info = pclk_info_get(clk); > + ? ? ? if (!pclk_info) { > + ? ? ? ? ? ? ? spin_lock_irqsave(&clocks_lock, flags); > + ? ? ? ? ? ? ? clk->pclk = NULL; > + ? ? ? ? ? ? ? clk->rate = 0; > + ? ? ? ? ? ? ? spin_unlock_irqrestore(&clocks_lock, flags); > + ? ? ? ? ? ? ? return; > + ? ? ? } > + > + ? ? ? change_parent(clk, pclk_info->pclk); > + > + ? ? ? spin_lock_irqsave(&clocks_lock, flags); > + ? ? ? if (pclk_info->scalable) { > + ? ? ? ? ? ? ? val = readl(config->synth_reg); > + > + ? ? ? ? ? ? ? eqn = (val >> AUX_EQ_SEL_SHIFT) & AUX_EQ_SEL_MASK; > + ? ? ? ? ? ? ? if (eqn == AUX_EQ1_SEL) > + ? ? ? ? ? ? ? ? ? ? ? den *= 2; > + > + ? ? ? ? ? ? ? /* calculate numerator */ > + ? ? ? ? ? ? ? num = (val >> AUX_XSCALE_SHIFT) & AUX_XSCALE_MASK; > + > + ? ? ? ? ? ? ? /* calculate denominator */ > + ? ? ? ? ? ? ? den *= (val >> AUX_YSCALE_SHIFT) & AUX_YSCALE_MASK; > + ? ? ? ? ? ? ? val = (((clk->pclk->rate/10000) * num) / den) * 10000; > + ? ? ? } else > + ? ? ? ? ? ? ? val = clk->pclk->rate; > + > + ? ? ? clk->rate = val; > + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags); > +} > + > +/* > + * calculates current programmed rate of gpt synthesizers > + * Fout from synthesizer can be given from below equations: > + * Fout= Fin/((2 ^ (N+1)) * (M+1)) > + */ > +void gpt_clk_recalc(struct clk *clk) > +{ > + ? ? ? struct aux_clk_config *config = clk->private_data; > + ? ? ? struct pclk_info *pclk_info = NULL; > + ? ? ? unsigned int div = 1, val; > + ? ? ? unsigned long flags; > + > + ? ? ? pclk_info = pclk_info_get(clk); > + ? ? ? if (!pclk_info) { > + ? ? ? ? ? ? ? spin_lock_irqsave(&clocks_lock, flags); > + ? ? ? ? ? ? ? clk->pclk = NULL; > + ? ? ? ? ? ? ? clk->rate = 0; > + ? ? ? ? ? ? ? spin_unlock_irqrestore(&clocks_lock, flags); > + ? ? ? ? ? ? ? return; > + ? ? ? } > + > + ? ? ? change_parent(clk, pclk_info->pclk); > + > + ? ? ? spin_lock_irqsave(&clocks_lock, flags); > + ? ? ? if (pclk_info->scalable) { > + ? ? ? ? ? ? ? val = readl(config->synth_reg); > + ? ? ? ? ? ? ? div += (val >> GPT_MSCALE_SHIFT) & GPT_MSCALE_MASK; > + ? ? ? ? ? ? ? div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1); > + ? ? ? } > + > + ? ? ? clk->rate = (unsigned long)clk->pclk->rate / div; > + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags); > +} > + > +/* > + * Used for clocks that always have same value as the parent clock divided by a > + * fixed divisor > + */ > +void follow_parent(struct clk *clk) > +{ > + ? ? ? unsigned long flags; > + > + ? ? ? spin_lock_irqsave(&clocks_lock, flags); > + ? ? ? clk->rate = clk->pclk->rate; > + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags); > +} > + > +/** > + * recalc_root_clocks - recalculate and propagate all root clocks > + * > + * Recalculates all root clocks (clocks with no parent), which if the > + * clock's .recalc is set correctly, should also propagate their rates. > + */ > +void recalc_root_clocks(void) > +{ > + ? ? ? propagate_rate(&root_clks); > +} I understand (I think) how speed change can propagate through the clocks. However I think it will be hard to notify users that the clock rate has changed, because there is nothing in the clk framework that supports that. If you have drivers with dynamic clocks, do you have any plans on how you will notify drivers? OMAP uses CPUfreq but that is really about the CPU. As it happens, all their clk:s always change frequency at the same operating points as the CPU. So they can have pre/post calls from CPUfreq in their code, but this will not work with things like PrimeCells where other users of the cell may not have operating points correlated with CPU operating points. (I'm not requesting you to solve this problem, more to be aware of it.) > diff --git a/arch/arm/plat-spear/include/plat/clkdev.h b/arch/arm/plat-spear/include/plat/clkdev.h > new file mode 100644 > index 0000000..9b1cd54 > --- /dev/null > +++ b/arch/arm/plat-spear/include/plat/clkdev.h > @@ -0,0 +1,20 @@ > +/* > + * arch/arm/plat-spear/include/plat/clkdev.h > + * > + * Clock Dev framework definitions for SPEAr platform > + * > + * Copyright (C) 2009 ST Microelectronics > + * Viresh Kumar<viresh.kumar@st.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#ifndef __ASM_PLAT_CLKDEV_H > +#define __ASM_PLAT_CLKDEV_H > + > +#define __clk_get(clk) ({ 1; }) > +#define __clk_put(clk) do { } while (0) > + > +#endif /* __ASM_PLAT_CLKDEV_H */ > diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h > new file mode 100755 > index 0000000..c220274 > --- /dev/null > +++ b/arch/arm/plat-spear/include/plat/clock.h > @@ -0,0 +1,130 @@ > +/* > + * arch/arm/plat-spear/include/plat/clock.h > + * > + * Clock framework definitions for SPEAr platform > + * > + * Copyright (C) 2009 ST Microelectronics > + * Viresh Kumar<viresh.kumar@st.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#ifndef __ASM_PLAT_CLOCK_H > +#define __ASM_PLAT_CLOCK_H > + > +#include <linux/list.h> > +#include <asm/clkdev.h> > +#include <linux/types.h> > + > +/* clk values */ > +#define KHZ ? ? ? ? ? ? ? ? ? ?(1000) > +#define MHZ ? ? ? ? ? ? ? ? ? ?(1000000) This looks far to generic to be hidden in some weird special architecture. And I *think* the preferred way to encode frequencies in the kernel is raw Hertz measure with all the extra zeroes. Doing .foo = MHZ *48; Is a bit awkward, don't you think it's better to do: #define MHZ(f) f * 1000000 .foo = MHZ(48); If you absolutely want to do this, I would suggest to add the KHZ and MHZ macros to some global kernel file but I honestly cannot say which one. Perhaps inlcude/linux/clk.h? > + > +/* clk structure flags */ > +#define ? ? ? ?ALWAYS_ENABLED ? ? ? ? ?(1 << 0) /* clock always enabled */ > +#define ? ? ? ?RESET_TO_ENABLE ? ? ? ? (1 << 1) /* reset register bit to enable clk */ > + > +/** > + * struct clkops - clock operations > + * @enable: pointer to clock enable function > + * @disable: pointer to clock disable function > + */ > +struct clkops { > + ? ? ? int (*enable) (struct clk *); > + ? ? ? void (*disable) (struct clk *); > +}; > + > +/** > + * struct pclk_info - parents info > + * @pclk: pointer to parent clk > + * @pclk_mask: value to be written for selecting this parent > + * @scalable: Is parent scalable (1 - YES, 0 - NO) > + */ > +struct pclk_info { > + ? ? ? struct clk *pclk; > + ? ? ? u8 pclk_mask; > + ? ? ? u8 scalable; > +}; > + > +/** > + * struct pclk_sel - parents selection configuration > + * @pclk_info: pointer to array of parent clock info > + * @pclk_count: number of parents > + * @pclk_sel_reg: register for selecting a parent > + * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also) > + */ > +struct pclk_sel { > + ? ? ? struct pclk_info *pclk_info; > + ? ? ? u8 pclk_count; > + ? ? ? unsigned int *pclk_sel_reg; > + ? ? ? unsigned int pclk_sel_mask; > +}; > + > +/** > + * struct clk - clock structure > + * @usage_count: num of users who enabled this clock > + * @flags: flags for clock properties > + * @rate: programmed clock rate in Hz > + * @en_reg: clk enable/disable reg > + * @en_reg_bit: clk enable/disable bit > + * @ops: clk enable/disable ops - generic_clkops selected if NULL > + * @recalc: pointer to clock rate recalculate function > + * @pclk: current parent clk > + * @pclk_sel: pointer to parent selection structure > + * @pclk_sel_shift: register shift for selecting parent of this clock > + * @children: list for childrens or this clock > + * @sibling: node for list of clocks having same parents > + * @private_data: clock specific private data > + */ > +struct clk { > + ? ? ? unsigned int usage_count; > + ? ? ? unsigned int flags; > + ? ? ? unsigned long rate; > + ? ? ? unsigned int *en_reg; > + ? ? ? u8 en_reg_bit; > + ? ? ? const struct clkops *ops; > + ? ? ? void (*recalc) (struct clk *); > + > + ? ? ? struct clk *pclk; > + ? ? ? struct pclk_sel *pclk_sel; > + ? ? ? unsigned int pclk_sel_shift; > + > + ? ? ? struct list_head children; > + ? ? ? struct list_head sibling; > + ? ? ? void *private_data; > +}; > + > +/* pll configuration structure */ > +struct pll_clk_config { > + ? ? ? unsigned int *mode_reg; > + ? ? ? unsigned int *cfg_reg; > +}; > + > +/* ahb and apb bus configuration structure */ > +struct bus_clk_config { > + ? ? ? unsigned int *reg; > + ? ? ? unsigned int mask; > + ? ? ? unsigned int shift; > +}; > + > +/* > + * Aux clk configuration structure: applicable to GPT, UART and FIRDA > + */ > +struct aux_clk_config { > + ? ? ? unsigned int *synth_reg; > +}; > + > +/* platform specific clock functions */ > +void clk_register(struct clk_lookup *cl); > +void recalc_root_clocks(void); > + > +/* clock recalc functions */ > +void follow_parent(struct clk *clk); > +void pll1_clk_recalc(struct clk *clk); > +void bus_clk_recalc(struct clk *clk); > +void gpt_clk_recalc(struct clk *clk); > +void aux_clk_recalc(struct clk *clk); > + > +#endif /* __ASM_PLAT_CLOCK_H */ > -- > 1.6.0.2 Yours, Linus Walleij ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines 2010-03-11 7:00 ` [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines Linus Walleij @ 2010-03-11 10:18 ` Shiraz HASHIM 2010-03-12 8:46 ` Linus Walleij 2010-03-12 4:19 ` Viresh KUMAR 1 sibling, 1 reply; 51+ messages in thread From: Shiraz HASHIM @ 2010-03-11 10:18 UTC (permalink / raw) To: linux-arm-kernel Hello Linus, Thanks for your comments. Replying on some of these. For the rest Viresh would reply tomorrow. On 3/11/2010 12:30 PM, Linus Walleij wrote: > 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: > >> Clock framework for SPEAr is based upon clkdev framework for ARM >> (... clock tree definition looks OK to me ...) > >> diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c >> new file mode 100755 >> index 0000000..bdcae0c >> --- /dev/null >> +++ b/arch/arm/plat-spear/clock.c >> @@ -0,0 +1,433 @@ >> +/* >> + * arch/arm/plat-spear/clock.c >> + * >> + * Clock framework for SPEAr platform >> + * >> + * Copyright (C) 2009 ST Microelectronics >> + * Viresh Kumar<viresh.kumar@st.com> >> + * >> + * This file is licensed under the terms of the GNU General Public >> + * License version 2. This program is licensed "as is" without any >> + * warranty of any kind, whether express or implied. >> + */ >> + >> +#include <linux/bug.h> >> +#include <linux/err.h> >> +#include <linux/io.h> >> +#include <linux/list.h> >> +#include <linux/module.h> >> +#include <linux/spinlock.h> >> +#include <mach/misc_regs.h> >> +#include <plat/clock.h> >> + >> +static DEFINE_SPINLOCK(clocks_lock); >> +static LIST_HEAD(root_clks); >> + >> +static void propagate_rate(struct list_head *); >> + >> +static int generic_clk_enable(struct clk *clk) >> +{ >> + unsigned int val; >> + >> + if (!clk->en_reg) >> + return -EFAULT; >> + >> + val = readl(clk->en_reg); >> + if (unlikely(clk->flags & RESET_TO_ENABLE)) >> + val &= ~(1 << clk->en_reg_bit); >> + else >> + val |= 1 << clk->en_reg_bit; >> + writel(val, clk->en_reg); > > I don't understand one bit of this. What happens if the RESET_TO_ENABLE > flag is set for the clock? The exact same bit is &-masked and then > immediately |:ed to 1 again. Then it is written to the register. Practical > effect: absolutely none. > > Is there a writel(val, clk->en_reg); missing from the unlikely() execution > path? The intention to use RESET_TO_ENABLE flag is to generalize clock enable/disable across platforms. To enable particular clock, we may require to set/reset some particular bit in system register. If RESET_TO_ENABLE is set in the flags, this means we need to reset the corresponding bit (clk->en_reg_bit) to enable the clock else we need to set it. >> + >> + return 0; >> +} >> + >> +static void generic_clk_disable(struct clk *clk) >> +{ >> + unsigned int val; >> + >> + if (!clk->en_reg) >> + return; >> + >> + val = readl(clk->en_reg); >> + if (unlikely(clk->flags & RESET_TO_ENABLE)) >> + val |= 1 << clk->en_reg_bit; >> + else >> + val &= ~(1 << clk->en_reg_bit); > > Same issue here... > The purpose of RESET_TO_ENABLE is explained above. So in this case if this flag is present we need to set the bit to disable the clock. >> + >> + writel(val, clk->en_reg); >> +} >> + >> +/* generic clk ops */ >> +static struct clkops generic_clkops = { >> + .enable = generic_clk_enable, >> + .disable = generic_clk_disable, >> +}; >> + >> +/* >> + * clk_enable - inform the system when the clock source should be running. >> + * @clk: clock source >> + * >> + * If the clock can not be enabled/disabled, this should return success. >> + * >> + * Returns success (0) or negative errno. >> + */ >> +int clk_enable(struct clk *clk) >> +{ >> + unsigned long flags; >> + int ret = 0; >> + >> + if (!clk || IS_ERR(clk)) >> + return -EFAULT; >> + >> + spin_lock_irqsave(&clocks_lock, flags); >> + if (clk->usage_count++ == 0) { > > Isnt if (++clk.>usage_count == 1) easier to understand, or is it just me? > BTW doing this: > clk->usage_count++; > if (clk->usage_count == 1) > will not use more memory, the compiler optimize this, so choose the > version you think is most readable. If you think this is very readable, by > all means keep it. I think you are right. I would let Viresh reply on this. >> + if (clk->ops && clk->ops->enable) >> + ret = clk->ops->enable(clk); >> + } >> + spin_unlock_irqrestore(&clocks_lock, flags); >> + >> + return ret; >> +} >> +EXPORT_SYMBOL(clk_enable); >> + >> +/* >> + * clk_disable - inform the system when the clock source is no longer required. >> + * @clk: clock source >> + * >> + * Inform the system that a clock source is no longer required by >> + * a driver and may be shut down. >> + * >> + * Implementation detail: if the clock source is shared between >> + * multiple drivers, clk_enable() calls must be balanced by the >> + * same number of clk_disable() calls for the clock source to be >> + * disabled. >> + */ >> +void clk_disable(struct clk *clk) >> +{ >> + unsigned long flags; >> + >> + if (!clk || IS_ERR(clk)) >> + return; >> + >> + WARN_ON(clk->usage_count == 0); >> + >> + spin_lock_irqsave(&clocks_lock, flags); >> + if (--clk->usage_count == 0) { > > Same readability issue here. >> + if (clk->ops && clk->ops->disable) >> + clk->ops->disable(clk); >> + } >> + spin_unlock_irqrestore(&clocks_lock, flags); >> +} >> +EXPORT_SYMBOL(clk_disable); >> + >> +/** >> + * clk_get_rate - obtain the current clock rate (in Hz) for a clock source. >> + * This is only valid once the clock source has been enabled. >> + * @clk: clock source >> + */ >> +unsigned long clk_get_rate(struct clk *clk) >> +{ >> + unsigned long flags, rate; >> + >> + spin_lock_irqsave(&clocks_lock, flags); >> + rate = clk->rate; >> + spin_unlock_irqrestore(&clocks_lock, flags); >> + >> + return rate; >> +} >> +EXPORT_SYMBOL(clk_get_rate); >> + >> +/** >> + * clk_set_parent - set the parent clock source for this clock >> + * @clk: clock source >> + * @parent: parent clock source >> + * >> + * Returns success (0) or negative errno. >> + */ >> +int clk_set_parent(struct clk *clk, struct clk *parent) >> +{ >> + int i, found = 0, val = 0; >> + unsigned long flags; >> + >> + if (!clk || IS_ERR(clk) || !parent || IS_ERR(parent)) >> + return -EFAULT; >> + if (clk->usage_count == 0) >> + return -EBUSY; > > Why will the clk_set_parent() call fail if there are *no* users of the clock? > Should it not be the other way around? Or what am I misunderstanding here? I think you are right. The parent can be selected even if clock is disabled. I would let Viresh answer on this. >> + if (!clk->pclk_sel) >> + return -EPERM; >> + if (clk->pclk == parent) >> + return 0; >> + >> + for (i = 0; i < clk->pclk_sel->pclk_count; i++) { >> + if (clk->pclk_sel->pclk_info[i].pclk == parent) { >> + found = 1; >> + break; >> + } >> + } >> + >> + if (!found) >> + return -EPERM; > > What about -ENODEV or so? (I don't know what people typically > use for clocks that don't exist.) > yes, atleast -EPERM doesn't seem suitable here. May be -EINVAL or -ENOENT? >> + >> + spin_lock_irqsave(&clocks_lock, flags); >> + /* reflect parent change in hardware */ >> + val = readl(clk->pclk_sel->pclk_sel_reg); >> + val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift); >> + val |= clk->pclk_sel->pclk_info[i].pclk_mask << clk->pclk_sel_shift; >> + writel(val, clk->pclk_sel->pclk_sel_reg); >> + spin_unlock_irqrestore(&clocks_lock, flags); >> + >> + /* reflect parent change in software */ >> + clk->recalc(clk); >> + propagate_rate(&clk->children); >> + return 0; >> +} >> +EXPORT_SYMBOL(clk_set_parent); >> + >> +/* registers clock in platform clock framework */ >> +void clk_register(struct clk_lookup *cl) >> +{ >> + struct clk *clk = cl->clk; >> + unsigned long flags; >> + >> + if (!clk || IS_ERR(clk)) >> + return; >> + >> + spin_lock_irqsave(&clocks_lock, flags); >> + >> + INIT_LIST_HEAD(&clk->children); >> + if (clk->flags & ALWAYS_ENABLED) >> + clk->ops = NULL; >> + else if (!clk->ops) >> + clk->ops = &generic_clkops; >> + >> + /* root clock don't have any parents */ >> + if (!clk->pclk && !clk->pclk_sel) { >> + list_add(&clk->sibling, &root_clks); >> + /* add clocks with only one parent to parent's children list */ >> + } else if (clk->pclk && !clk->pclk_sel) { >> + list_add(&clk->sibling, &clk->pclk->children); >> + } else { >> + /* add clocks with > 1 parent to 1st parent's children list */ >> + list_add(&clk->sibling, >> + &clk->pclk_sel->pclk_info[0].pclk->children); >> + } >> + spin_unlock_irqrestore(&clocks_lock, flags); >> + >> + /* add clock to arm clockdev framework */ >> + clkdev_add(cl); >> +} >> + >> +/** >> + * propagate_rate - recalculate and propagate all clocks in list head >> + * >> + * Recalculates all root clocks in list head, which if the clock's .recalc is >> + * set correctly, should also propagate their rates. >> + */ >> +static void propagate_rate(struct list_head *lhead) >> +{ >> + struct clk *clkp, *_temp; >> + >> + list_for_each_entry_safe(clkp, _temp, lhead, sibling) { >> + if (clkp->recalc) >> + clkp->recalc(clkp); >> + propagate_rate(&clkp->children); >> + } >> +} >> + >> +/* returns current programmed clocks clock info structure */ >> +static struct pclk_info *pclk_info_get(struct clk *clk) >> +{ >> + unsigned int mask, i; >> + unsigned long flags; >> + struct pclk_info *info; >> + >> + spin_lock_irqsave(&clocks_lock, flags); >> + mask = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift) >> + & clk->pclk_sel->pclk_sel_mask; >> + >> + for (i = 0; i < clk->pclk_sel->pclk_count; i++) { >> + if (clk->pclk_sel->pclk_info[i].pclk_mask == mask) >> + info = &clk->pclk_sel->pclk_info[i]; >> + } >> + spin_unlock_irqrestore(&clocks_lock, flags); >> + >> + return info; >> +} >> + >> +/* >> + * Set pclk as cclk's parent and add clock sibling node to current parents >> + * children list >> + */ >> +static void change_parent(struct clk *cclk, struct clk *pclk) >> +{ >> + unsigned long flags; >> + >> + spin_lock_irqsave(&clocks_lock, flags); >> + list_del(&cclk->sibling); >> + list_add(&cclk->sibling, &pclk->children); >> + >> + cclk->pclk = pclk; >> + spin_unlock_irqrestore(&clocks_lock, flags); >> +} >> + >> +/* >> + * calculates current programmed rate of pll1 >> + * >> + * In normal mode >> + * rate = (2 * M[15:8] * Fin)/(N * 2^P) >> + * >> + * In Dithered mode >> + * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P) >> + */ >> +void pll1_clk_recalc(struct clk *clk) >> +{ >> + struct pll_clk_config *config = clk->private_data; >> + unsigned int num = 2, den = 0, val, mode = 0; >> + unsigned long flags; >> + >> + spin_lock_irqsave(&clocks_lock, flags); >> + mode = (readl(config->mode_reg) >> PLL_MODE_SHIFT) & >> + PLL_MODE_MASK; >> + >> + val = readl(config->cfg_reg); >> + /* calculate denominator */ >> + den = (val >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK; >> + den = 1 << den; >> + den *= (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK; >> + >> + /* calculate numerator & denominator */ >> + if (!mode) { >> + /* Normal mode */ >> + num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK; >> + } else { >> + /* Dithered mode */ >> + num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK; >> + den *= 256; >> + } >> + >> + clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000; >> + spin_unlock_irqrestore(&clocks_lock, flags); >> +} >> + >> +/* calculates current programmed rate of ahb or apb bus */ >> +void bus_clk_recalc(struct clk *clk) >> +{ >> + struct bus_clk_config *config = clk->private_data; >> + unsigned int div; >> + unsigned long flags; >> + >> + spin_lock_irqsave(&clocks_lock, flags); >> + div = ((readl(config->reg) >> config->shift) & config->mask) + 1; >> + clk->rate = (unsigned long)clk->pclk->rate / div; >> + spin_unlock_irqrestore(&clocks_lock, flags); >> +} >> + >> +/* >> + * calculates current programmed rate of auxiliary synthesizers >> + * used by: UART, FIRDA >> + * >> + * Fout from synthesizer can be given from two equations: >> + * Fout1 = (Fin * X/Y)/2 >> + * Fout2 = Fin * X/Y >> + * >> + * Selection of eqn 1 or 2 is programmed in register >> + */ >> +void aux_clk_recalc(struct clk *clk) >> +{ >> + struct aux_clk_config *config = clk->private_data; >> + struct pclk_info *pclk_info = NULL; >> + unsigned int num = 1, den = 1, val, eqn; >> + unsigned long flags; >> + >> + /* get current programmed parent */ >> + pclk_info = pclk_info_get(clk); >> + if (!pclk_info) { >> + spin_lock_irqsave(&clocks_lock, flags); >> + clk->pclk = NULL; >> + clk->rate = 0; >> + spin_unlock_irqrestore(&clocks_lock, flags); >> + return; >> + } >> + >> + change_parent(clk, pclk_info->pclk); >> + >> + spin_lock_irqsave(&clocks_lock, flags); >> + if (pclk_info->scalable) { >> + val = readl(config->synth_reg); >> + >> + eqn = (val >> AUX_EQ_SEL_SHIFT) & AUX_EQ_SEL_MASK; >> + if (eqn == AUX_EQ1_SEL) >> + den *= 2; >> + >> + /* calculate numerator */ >> + num = (val >> AUX_XSCALE_SHIFT) & AUX_XSCALE_MASK; >> + >> + /* calculate denominator */ >> + den *= (val >> AUX_YSCALE_SHIFT) & AUX_YSCALE_MASK; >> + val = (((clk->pclk->rate/10000) * num) / den) * 10000; >> + } else >> + val = clk->pclk->rate; >> + >> + clk->rate = val; >> + spin_unlock_irqrestore(&clocks_lock, flags); >> +} >> + >> +/* >> + * calculates current programmed rate of gpt synthesizers >> + * Fout from synthesizer can be given from below equations: >> + * Fout= Fin/((2 ^ (N+1)) * (M+1)) >> + */ >> +void gpt_clk_recalc(struct clk *clk) >> +{ >> + struct aux_clk_config *config = clk->private_data; >> + struct pclk_info *pclk_info = NULL; >> + unsigned int div = 1, val; >> + unsigned long flags; >> + >> + pclk_info = pclk_info_get(clk); >> + if (!pclk_info) { >> + spin_lock_irqsave(&clocks_lock, flags); >> + clk->pclk = NULL; >> + clk->rate = 0; >> + spin_unlock_irqrestore(&clocks_lock, flags); >> + return; >> + } >> + >> + change_parent(clk, pclk_info->pclk); >> + >> + spin_lock_irqsave(&clocks_lock, flags); >> + if (pclk_info->scalable) { >> + val = readl(config->synth_reg); >> + div += (val >> GPT_MSCALE_SHIFT) & GPT_MSCALE_MASK; >> + div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1); >> + } >> + >> + clk->rate = (unsigned long)clk->pclk->rate / div; >> + spin_unlock_irqrestore(&clocks_lock, flags); >> +} >> + >> +/* >> + * Used for clocks that always have same value as the parent clock divided by a >> + * fixed divisor >> + */ >> +void follow_parent(struct clk *clk) >> +{ >> + unsigned long flags; >> + >> + spin_lock_irqsave(&clocks_lock, flags); >> + clk->rate = clk->pclk->rate; >> + spin_unlock_irqrestore(&clocks_lock, flags); >> +} >> + >> +/** >> + * recalc_root_clocks - recalculate and propagate all root clocks >> + * >> + * Recalculates all root clocks (clocks with no parent), which if the >> + * clock's .recalc is set correctly, should also propagate their rates. >> + */ >> +void recalc_root_clocks(void) >> +{ >> + propagate_rate(&root_clks); >> +} > > I understand (I think) how speed change can propagate through the clocks. > However I think it will be hard to notify users that the clock rate has changed, > because there is nothing in the clk framework that supports that. If you have > drivers with dynamic clocks, do you have any plans on how you will > notify drivers? yes, the clock framework doesn't really defines interface to notify frequency change. But at all the times it should contain and reflect the correct system state w.r.t. the frequency and clock selection and hence propagate_rate is must. > OMAP uses CPUfreq but that is really about the CPU. As it happens, all > their clk:s always change frequency at the same operating points as the > CPU. So they can have pre/post calls from CPUfreq in their code, but > this will not work with things like PrimeCells where other users of the cell > may not have operating points correlated with CPU operating points. > > (I'm not requesting you to solve this problem, more to be aware of it.) I think generally in embedded systems (at least in our case :) ) the CPU clock itself is not completly independent. It is generally tied with some system clock, which has an impact on bus and peripheral clocks. In that sense cpu freq would be a better mean to notify frequency change. In any case, clock framework don't intend to do it. It only need to reflect correct system state. Is this understanding correct? >> diff --git a/arch/arm/plat-spear/include/plat/clkdev.h b/arch/arm/plat-spear/include/plat/clkdev.h >> new file mode 100644 >> index 0000000..9b1cd54 >> --- /dev/null >> +++ b/arch/arm/plat-spear/include/plat/clkdev.h >> @@ -0,0 +1,20 @@ >> +/* >> + * arch/arm/plat-spear/include/plat/clkdev.h >> + * >> + * Clock Dev framework definitions for SPEAr platform >> + * >> + * Copyright (C) 2009 ST Microelectronics >> + * Viresh Kumar<viresh.kumar@st.com> >> + * >> + * This file is licensed under the terms of the GNU General Public >> + * License version 2. This program is licensed "as is" without any >> + * warranty of any kind, whether express or implied. >> + */ >> + >> +#ifndef __ASM_PLAT_CLKDEV_H >> +#define __ASM_PLAT_CLKDEV_H >> + >> +#define __clk_get(clk) ({ 1; }) >> +#define __clk_put(clk) do { } while (0) >> + >> +#endif /* __ASM_PLAT_CLKDEV_H */ >> diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h >> new file mode 100755 >> index 0000000..c220274 >> --- /dev/null >> +++ b/arch/arm/plat-spear/include/plat/clock.h >> @@ -0,0 +1,130 @@ >> +/* >> + * arch/arm/plat-spear/include/plat/clock.h >> + * >> + * Clock framework definitions for SPEAr platform >> + * >> + * Copyright (C) 2009 ST Microelectronics >> + * Viresh Kumar<viresh.kumar@st.com> >> + * >> + * This file is licensed under the terms of the GNU General Public >> + * License version 2. This program is licensed "as is" without any >> + * warranty of any kind, whether express or implied. >> + */ >> + >> +#ifndef __ASM_PLAT_CLOCK_H >> +#define __ASM_PLAT_CLOCK_H >> + >> +#include <linux/list.h> >> +#include <asm/clkdev.h> >> +#include <linux/types.h> >> + >> +/* clk values */ >> +#define KHZ (1000) >> +#define MHZ (1000000) > > This looks far to generic to be hidden in some weird special architecture. > And I *think* the preferred way to encode frequencies in the kernel is raw > Hertz measure with all the extra zeroes. > > Doing > .foo = MHZ *48; > > Is a bit awkward, don't you think it's better to do: > #define MHZ(f) f * 1000000 > .foo = MHZ(48); > > If you absolutely want to do this, I would suggest to add the KHZ and MHZ > macros to some global kernel file but I honestly cannot say which one. > Perhaps inlcude/linux/clk.h? I would let Viresh, comment on this. >> + >> +/* clk structure flags */ >> +#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */ >> +#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */ >> + >> +/** >> + * struct clkops - clock operations >> + * @enable: pointer to clock enable function >> + * @disable: pointer to clock disable function >> + */ >> +struct clkops { >> + int (*enable) (struct clk *); >> + void (*disable) (struct clk *); >> +}; >> + >> +/** >> + * struct pclk_info - parents info >> + * @pclk: pointer to parent clk >> + * @pclk_mask: value to be written for selecting this parent >> + * @scalable: Is parent scalable (1 - YES, 0 - NO) >> + */ >> +struct pclk_info { >> + struct clk *pclk; >> + u8 pclk_mask; >> + u8 scalable; >> +}; >> + >> +/** >> + * struct pclk_sel - parents selection configuration >> + * @pclk_info: pointer to array of parent clock info >> + * @pclk_count: number of parents >> + * @pclk_sel_reg: register for selecting a parent >> + * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also) >> + */ >> +struct pclk_sel { >> + struct pclk_info *pclk_info; >> + u8 pclk_count; >> + unsigned int *pclk_sel_reg; >> + unsigned int pclk_sel_mask; >> +}; >> + >> +/** >> + * struct clk - clock structure >> + * @usage_count: num of users who enabled this clock >> + * @flags: flags for clock properties >> + * @rate: programmed clock rate in Hz >> + * @en_reg: clk enable/disable reg >> + * @en_reg_bit: clk enable/disable bit >> + * @ops: clk enable/disable ops - generic_clkops selected if NULL >> + * @recalc: pointer to clock rate recalculate function >> + * @pclk: current parent clk >> + * @pclk_sel: pointer to parent selection structure >> + * @pclk_sel_shift: register shift for selecting parent of this clock >> + * @children: list for childrens or this clock >> + * @sibling: node for list of clocks having same parents >> + * @private_data: clock specific private data >> + */ >> +struct clk { >> + unsigned int usage_count; >> + unsigned int flags; >> + unsigned long rate; >> + unsigned int *en_reg; >> + u8 en_reg_bit; >> + const struct clkops *ops; >> + void (*recalc) (struct clk *); >> + >> + struct clk *pclk; >> + struct pclk_sel *pclk_sel; >> + unsigned int pclk_sel_shift; >> + >> + struct list_head children; >> + struct list_head sibling; >> + void *private_data; >> +}; >> + >> +/* pll configuration structure */ >> +struct pll_clk_config { >> + unsigned int *mode_reg; >> + unsigned int *cfg_reg; >> +}; >> + >> +/* ahb and apb bus configuration structure */ >> +struct bus_clk_config { >> + unsigned int *reg; >> + unsigned int mask; >> + unsigned int shift; >> +}; >> + >> +/* >> + * Aux clk configuration structure: applicable to GPT, UART and FIRDA >> + */ >> +struct aux_clk_config { >> + unsigned int *synth_reg; >> +}; >> + >> +/* platform specific clock functions */ >> +void clk_register(struct clk_lookup *cl); >> +void recalc_root_clocks(void); >> + >> +/* clock recalc functions */ >> +void follow_parent(struct clk *clk); >> +void pll1_clk_recalc(struct clk *clk); >> +void bus_clk_recalc(struct clk *clk); >> +void gpt_clk_recalc(struct clk *clk); >> +void aux_clk_recalc(struct clk *clk); >> + >> +#endif /* __ASM_PLAT_CLOCK_H */ >> -- >> 1.6.0.2 regards Shiraz ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines 2010-03-11 10:18 ` Shiraz HASHIM @ 2010-03-12 8:46 ` Linus Walleij 0 siblings, 0 replies; 51+ messages in thread From: Linus Walleij @ 2010-03-12 8:46 UTC (permalink / raw) To: linux-arm-kernel 2010/3/11 Shiraz HASHIM <shiraz.hashim@st.com>: > On 3/11/2010 12:30 PM, Linus Walleij wrote: >> 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: >> (...) >>> + ? ? ? if (unlikely(clk->flags & RESET_TO_ENABLE)) >>> + ? ? ? ? ? ? ? val &= ~(1 << clk->en_reg_bit); >>> + ? ? ? else >>> + ? ? ? ? ? ? ? val |= 1 << clk->en_reg_bit; >>> + ? ? ? writel(val, clk->en_reg); >> >> I don't understand one bit of this. (...) > > The intention to use RESET_TO_ENABLE flag is to generalize clock > enable/disable across platforms. I misread the entire thing, there was some bad parsing inside my head... Sorry about this. >> OMAP uses CPUfreq but that is really about the CPU. As it happens, all >> their clk:s always change frequency at the same operating points as the >> CPU. So they can have pre/post calls from CPUfreq in their code, but >> this will not work with things like PrimeCells where other users of the cell >> may not have operating points correlated with CPU operating points. >> >> (I'm not requesting you to solve this problem, more to be aware of it.) > > I think generally in embedded systems (at least in our case :) ) the CPU clock > itself is not completly independent. It is generally tied with some system > clock, which has an impact on bus and peripheral clocks. In that sense cpu freq > would be a better mean to notify frequency change. > In any case, clock framework don't intend to do it. It only need to reflect > correct system state. Is this understanding correct? Currently it's like that but I think clk really needs a frequency change notification mechanism. I will have to deal with it some day I think :-/ Yours, Linus Walleij ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines 2010-03-11 7:00 ` [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines Linus Walleij 2010-03-11 10:18 ` Shiraz HASHIM @ 2010-03-12 4:19 ` Viresh KUMAR 1 sibling, 0 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-12 4:19 UTC (permalink / raw) To: linux-arm-kernel On 3/11/2010 12:30 PM, Linus Walleij wrote: > 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: > >> +{ >> + unsigned int val; >> + >> + if (!clk->en_reg) >> + return -EFAULT; >> + >> + val = readl(clk->en_reg); >> + if (unlikely(clk->flags & RESET_TO_ENABLE)) >> + val &= ~(1 << clk->en_reg_bit); >> + else >> + val |= 1 << clk->en_reg_bit; >> + writel(val, clk->en_reg); > > I don't understand one bit of this. What happens if the RESET_TO_ENABLE > flag is set for the clock? The exact same bit is &-masked and then > immediately |:ed to 1 again. Then it is written to the register. Practical > effect: absolutely none. > > Is there a writel(val, clk->en_reg); missing from the unlikely() execution > path? Already explained by shiraz. > >> + >> + return 0; >> +} >> + >> +static void generic_clk_disable(struct clk *clk) >> +{ >> + unsigned int val; >> + >> + if (!clk->en_reg) >> + return; >> + >> + val = readl(clk->en_reg); >> + if (unlikely(clk->flags & RESET_TO_ENABLE)) >> + val |= 1 << clk->en_reg_bit; >> + else >> + val &= ~(1 << clk->en_reg_bit); > > Same issue here... > >> + >> + writel(val, clk->en_reg); >> +} >> + >> +/* generic clk ops */ >> +static struct clkops generic_clkops = { >> + .enable = generic_clk_enable, >> + .disable = generic_clk_disable, >> +}; >> + >> +/* >> + * clk_enable - inform the system when the clock source should be running. >> + * @clk: clock source >> + * >> + * If the clock can not be enabled/disabled, this should return success. >> + * >> + * Returns success (0) or negative errno. >> + */ >> +int clk_enable(struct clk *clk) >> +{ >> + unsigned long flags; >> + int ret = 0; >> + >> + if (!clk || IS_ERR(clk)) >> + return -EFAULT; >> + >> + spin_lock_irqsave(&clocks_lock, flags); >> + if (clk->usage_count++ == 0) { > > Isnt if (++clk.>usage_count == 1) easier to understand, or is it just me? > BTW doing this: > clk->usage_count++; > if (clk->usage_count == 1) > will not use more memory, the compiler optimize this, so choose the > version you think is most readable. If you think this is very readable, by > all means keep it. > I will simplify it, to make it more readable. >> + if (clk->ops && clk->ops->enable) >> + ret = clk->ops->enable(clk); >> + } >> + spin_unlock_irqrestore(&clocks_lock, flags); >> + >> + return ret; >> +} >> +EXPORT_SYMBOL(clk_enable); >> + >> +/* >> + * clk_disable - inform the system when the clock source is no longer required. >> + * @clk: clock source >> + * >> + * Inform the system that a clock source is no longer required by >> + * a driver and may be shut down. >> + * >> + * Implementation detail: if the clock source is shared between >> + * multiple drivers, clk_enable() calls must be balanced by the >> + * same number of clk_disable() calls for the clock source to be >> + * disabled. >> + */ >> +void clk_disable(struct clk *clk) >> +{ >> + unsigned long flags; >> + >> + if (!clk || IS_ERR(clk)) >> + return; >> + >> + WARN_ON(clk->usage_count == 0); >> + >> + spin_lock_irqsave(&clocks_lock, flags); >> + if (--clk->usage_count == 0) { > > Same readability issue here. I will simplify it, to make it more readable. > >> + if (!clk || IS_ERR(clk) || !parent || IS_ERR(parent)) >> + return -EFAULT; >> + if (clk->usage_count == 0) >> + return -EBUSY; > > Why will the clk_set_parent() call fail if there are *no* users of the clock? > Should it not be the other way around? Or what am I misunderstanding here? > My mistake. should be !=. >> + if (!clk->pclk_sel) >> + return -EPERM; >> + if (clk->pclk == parent) >> + return 0; >> + >> + for (i = 0; i < clk->pclk_sel->pclk_count; i++) { >> + if (clk->pclk_sel->pclk_info[i].pclk == parent) { >> + found = 1; >> + break; >> + } >> + } >> + >> + if (!found) >> + return -EPERM; > > What about -ENODEV or so? (I don't know what people typically > use for clocks that don't exist.) Will correct it to return correct error. > >> + */ >> +void recalc_root_clocks(void) >> +{ >> + propagate_rate(&root_clks); >> +} > > I understand (I think) how speed change can propagate through the clocks. > However I think it will be hard to notify users that the clock rate has changed, > because there is nothing in the clk framework that supports that. If you have > drivers with dynamic clocks, do you have any plans on how you will > notify drivers? > > OMAP uses CPUfreq but that is really about the CPU. As it happens, all > their clk:s always change frequency at the same operating points as the > CPU. So they can have pre/post calls from CPUfreq in their code, but > this will not work with things like PrimeCells where other users of the cell > may not have operating points correlated with CPU operating points. > > (I'm not requesting you to solve this problem, more to be aware of it.) > already answered by shiraz. >> diff --git a/arch/arm/plat-spear/include/plat/clkdev.h b/arch/arm/plat-spear/include/plat/clkdev.h >> +/* clk values */ >> +#define KHZ (1000) >> +#define MHZ (1000000) > > This looks far to generic to be hidden in some weird special architecture. > And I *think* the preferred way to encode frequencies in the kernel is raw > Hertz measure with all the extra zeroes. > > Doing > .foo = MHZ *48; > > Is a bit awkward, don't you think it's better to do: > #define MHZ(f) f * 1000000 > .foo = MHZ(48); > > If you absolutely want to do this, I would suggest to add the KHZ and MHZ > macros to some global kernel file but I honestly cannot say which one. > Perhaps inlcude/linux/clk.h? > I will better remove them. regards, viresh kumar. ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines 2010-03-03 5:07 ` [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines Viresh KUMAR 2010-03-03 5:07 ` [PATCH 06/11] ST SPEAr: Added source files for SPEAr platform Viresh KUMAR 2010-03-11 7:00 ` [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines Linus Walleij @ 2010-03-11 10:28 ` Russell King - ARM Linux 2010-03-12 4:22 ` Viresh KUMAR 2 siblings, 1 reply; 51+ messages in thread From: Russell King - ARM Linux @ 2010-03-11 10:28 UTC (permalink / raw) To: linux-arm-kernel On Wed, Mar 03, 2010 at 10:37:35AM +0530, Viresh KUMAR wrote: > +/* array of all spear 3xx clock lookups */ > +static struct clk_lookup *spear_clk_lookups[] = { > + /* root clks */ > + &osc_32k_cl, > + &osc_24m_cl, This is rather wasteful - rather than defining structures, and then having a one-time-used set of pointers to the structures, why not just declare the whole lot as an array like most other implementations do? ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines 2010-03-11 10:28 ` Russell King - ARM Linux @ 2010-03-12 4:22 ` Viresh KUMAR 0 siblings, 0 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-12 4:22 UTC (permalink / raw) To: linux-arm-kernel On 3/11/2010 3:58 PM, Russell King - ARM Linux wrote: > On Wed, Mar 03, 2010 at 10:37:35AM +0530, Viresh KUMAR wrote: >> +/* array of all spear 3xx clock lookups */ >> +static struct clk_lookup *spear_clk_lookups[] = { >> + /* root clks */ >> + &osc_32k_cl, >> + &osc_24m_cl, > > This is rather wasteful - rather than defining structures, and then having > a one-time-used set of pointers to the structures, why not just declare > the whole lot as an array like most other implementations do? > I did it to make it more readable. But, obviously it is wasting some amount of memory for just nothing. Will change it with an array implementation. regards, viresh kumar. ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform 2010-03-03 5:07 ` [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform Viresh KUMAR 2010-03-03 5:07 ` [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines Viresh KUMAR @ 2010-03-10 5:40 ` Linus Walleij 2010-03-10 6:32 ` Viresh KUMAR 1 sibling, 1 reply; 51+ messages in thread From: Linus Walleij @ 2010-03-10 5:40 UTC (permalink / raw) To: linux-arm-kernel 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: > ?arch/arm/plat-spear/include/plat/gpt.h | ?108 ++++++++++++++++++++++++++++++++ If this file is only supposed to be used from plat-spear/time.c, move it down into plat-spear/gpt.h and #include "gpt.h" so noone else will accidentally use it. > (...) > > +#ifndef __ASM_PLAT_GPT_H > +#define __ASM_PLAT_GPT_H This file to macro match i.e. __PLAT_GPT_H again I think... (But see below.) > + > +/* register offsets */ > +#define GPT_CTRL_OFF ? ? ? ? ? 0x80 /* Control Register */ > +#define GPT_INT_OFF ? ? ? ? ? ?0x84 /* Interrupt Regiset */ > +#define GPT_LOAD_OFF ? ? ? ? ? 0x88 /* Load Register */ > +#define GPT_COUNT_OFF ? ? ? ? ?0x8C /* Current Count Register */ Some people want you to do all the indentation e.g. between GPT_CTRL_OFF -> 0x80 with TABs only, and I tend to do that to keep everybody happy. (This would go for all .h files with register definitions. > + > +/* CTRL Reg Bit Values */ > +#define GPT_CTRL_MATCH_INT ? ? 0x0100 > +#define GPT_CTRL_ENABLE ? ? ? ? ? ? ? ?0x0020 > +#define GPT_CTRL_MODE_AR ? ? ? 0x0010 > + > +#define GPT_CTRL_PRESCALER1 ? ?0x0 > +#define GPT_CTRL_PRESCALER2 ? ?0x1 > +#define GPT_CTRL_PRESCALER4 ? ?0x2 > +#define GPT_CTRL_PRESCALER8 ? ?0x3 > +#define GPT_CTRL_PRESCALER16 ? 0x4 > +#define GPT_CTRL_PRESCALER32 ? 0x5 > +#define GPT_CTRL_PRESCALER64 ? 0x6 > +#define GPT_CTRL_PRESCALER128 ?0x7 > +#define GPT_CTRL_PRESCALER256 ?0x8 > + > +/* INT Reg Bit Values */ > +#define GPT_STATUS_MATCH ? ? ? 0x0001 > + > +/* clock sources */ > +#define SPEAR_TIMER_SRC_PLL3_CLK ? ? ? 0x00 > +#define SPEAR_TIMER_SRC_SYS_CLK ? ? ? ? ? ? ? ?0x01 > + > +/** > + * struct spear_timer - spear general purpose timer representation > + * @id: timer identifier 0 onwards > + * @phys_base: physical base address of timer > + * @irq: irq to which this gpt is attached > + * @prescaler: the prescaler for input freq at which timer is working > + * @fclk: gpt functional clock > + * @io_base: virtual base address of timer > + * @reserved: indication that gpt is reserved now > + * @enabled: indication that gpt is enabled > + * > + * The timer structure represent the timer channel available in SPEAr. Each > + * timer unit in SPEAr contains two individual timer channels with different > + * set of configuration registers * and irq. But the point to remember is > + * this that the fclk is common for each channels withing a timer unit. > + */ > + > +struct spear_timer { > + ? ? ? unsigned int id; > + ? ? ? unsigned long phys_base; > + ? ? ? int irq; > + ? ? ? int prescaler; > + ? ? ? struct clk *fclk; > + ? ? ? void __iomem *io_base; > + ? ? ? unsigned reserved:1; > + ? ? ? unsigned enabled:1; > +}; > + > +/* > + * Following functions are exported by gpt.c which can be used by other > + * kernel entities > + */ > +int spear_timer_init(struct spear_timer *, int); > + > +struct spear_timer *spear_timer_request(void); > +struct spear_timer *spear_timer_request_specific(int id); > + > +int spear_timer_free(struct spear_timer *timer); > +int spear_timer_enable(struct spear_timer *timer); > +int spear_timer_disable(struct spear_timer *timer); > + > +int spear_timer_get_irq(struct spear_timer *timer); > + > +struct clk *spear_timer_get_fclk(struct spear_timer *timer); > + > +int spear_timer_start(struct spear_timer *timer); > +int spear_timer_stop(struct spear_timer *timer); > + > +int spear_timer_set_source(struct spear_timer *timer, int source); > +int spear_timer_set_load(struct spear_timer *timer, int autoreload, > + ? ? ? ? ? ? ? u16 value); > +int spear_timer_set_load_start(struct spear_timer *timer, int autoreload, > + ? ? ? ? ? ? ? u16 value); > +int spear_timer_match_irq(struct spear_timer *timer, int enable); > +int spear_timer_set_prescaler(struct spear_timer *timer, int prescaler); > + > +int spear_timer_read_status(struct spear_timer *timer); > +int spear_timer_clear_status(struct spear_timer *timer, u16 value); > + > +int spear_timer_read_counter(struct spear_timer *timer); > + > +int spear_timer_active(struct spear_timer *); Am I right in assuming that this will only ever be used from the plat/timer.c file? I would contemplate moving away the abstraction API altogether and put everything into timer.c, and just hardcode in the timers you're using as clocksource and clock event, and put the register definitions and offsets from base there as well. This will get down the number of files and reduce the forest of files in a nice way. If you have some other use of timers that you're planning, the API may be justified, please detail the uses you have in mind in that case. I know writing APIs is great fun, but sometimes it's easier to read the code if you just get rid of them and keep things simple... Yours, Linus Walleij ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform 2010-03-10 5:40 ` [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform Linus Walleij @ 2010-03-10 6:32 ` Viresh KUMAR 2010-03-10 9:31 ` Linus Walleij 0 siblings, 1 reply; 51+ messages in thread From: Viresh KUMAR @ 2010-03-10 6:32 UTC (permalink / raw) To: linux-arm-kernel Linus, On 3/10/2010 11:10 AM, Linus Walleij wrote: > 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: > >> arch/arm/plat-spear/include/plat/gpt.h | 108 ++++++++++++++++++++++++++++++++ > > If this file is only supposed to be used from plat-spear/time.c, move it down > into plat-spear/gpt.h and #include "gpt.h" so noone else will > accidentally use it. GPT's on SPEAr can be used from time.c, platform specific drivers and machine specific drivers or any driver wishing to use hardware timer. In first two cases "gpt.h" will work, but in rest of cases we need gpt.h to be in plat-spear/include/plat Is it okay? > >> (...) >> >> +#ifndef __ASM_PLAT_GPT_H >> +#define __ASM_PLAT_GPT_H > > This file to macro match i.e. __PLAT_GPT_H again I think... > (But see below.) will be changed > >> + >> +/* register offsets */ >> +#define GPT_CTRL_OFF 0x80 /* Control Register */ >> +#define GPT_INT_OFF 0x84 /* Interrupt Regiset */ >> +#define GPT_LOAD_OFF 0x88 /* Load Register */ >> +#define GPT_COUNT_OFF 0x8C /* Current Count Register */ > > Some people want you to do all the indentation e.g. between > GPT_CTRL_OFF -> 0x80 with TABs only, and I tend to do that > to keep everybody happy. (This would go for all .h files with > register definitions. > I have done it the way you said. I don't know what happened to formatting, even if i see my original patchset, i see tabs and no spaces. I will take care of this in next version of patchset too. >> + >> + * Following functions are exported by gpt.c which can be used by other >> + * kernel entities >> + */ >> +int spear_timer_init(struct spear_timer *, int); >> + >> +struct spear_timer *spear_timer_request(void); >> +struct spear_timer *spear_timer_request_specific(int id); >> + >> +int spear_timer_free(struct spear_timer *timer); >> +int spear_timer_enable(struct spear_timer *timer); >> +int spear_timer_disable(struct spear_timer *timer); >> + >> +int spear_timer_get_irq(struct spear_timer *timer); >> + >> +struct clk *spear_timer_get_fclk(struct spear_timer *timer); >> + >> +int spear_timer_start(struct spear_timer *timer); >> +int spear_timer_stop(struct spear_timer *timer); >> + >> +int spear_timer_set_source(struct spear_timer *timer, int source); >> +int spear_timer_set_load(struct spear_timer *timer, int autoreload, >> + u16 value); >> +int spear_timer_set_load_start(struct spear_timer *timer, int autoreload, >> + u16 value); >> +int spear_timer_match_irq(struct spear_timer *timer, int enable); >> +int spear_timer_set_prescaler(struct spear_timer *timer, int prescaler); >> + >> +int spear_timer_read_status(struct spear_timer *timer); >> +int spear_timer_clear_status(struct spear_timer *timer, u16 value); >> + >> +int spear_timer_read_counter(struct spear_timer *timer); >> + >> +int spear_timer_active(struct spear_timer *); > > Am I right in assuming that this will only ever be used from the plat/timer.c > file? This will be used by any module looking to use hardware timer. > > I would contemplate moving away the abstraction API altogether and put > everything into timer.c, and just hardcode in the timers you're using as > clocksource and clock event, and put the register definitions and > offsets from base there as well. This will get down the number of files > and reduce the forest of files in a nice way. > > If you have some other use of timers that you're planning, the API may > be justified, please detail the uses you have in mind in that case. > > I know writing APIs is great fun, but sometimes it's easier to read the > code if you just get rid of them and keep things simple... > Explained earlier. viresh kumar ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform 2010-03-10 6:32 ` Viresh KUMAR @ 2010-03-10 9:31 ` Linus Walleij 2010-03-10 10:11 ` Viresh KUMAR 0 siblings, 1 reply; 51+ messages in thread From: Linus Walleij @ 2010-03-10 9:31 UTC (permalink / raw) To: linux-arm-kernel 2010/3/10 Viresh KUMAR <viresh.kumar@st.com>: > Linus Walleij: >> If this file is only supposed to be used from plat-spear/time.c, move it down >> into plat-spear/gpt.h and #include "gpt.h" so noone else will >> accidentally use it. > > GPT's on SPEAr can be used from time.c, platform specific drivers and machine > specific drivers or any driver wishing to use hardware timer. > In first two cases "gpt.h" will work, but in rest of cases we need gpt.h to be > in plat-spear/include/plat > > Is it okay? If you have or have already planned to write such platform, machine or subsystem drivers, it's OK, if there are no such users and you cannot easily give one, it's overdesigned IMHO. Some realistic examples of such drivers will make me change my mind :-) The reason I persist is that I've seen such unutilized timer API:s before and no other user than the system timer in sight. I never understood what they were to be used for, and I still don't, so help me understand. The kernel has many internal timer API:s based on clockevent available already so why add yet another, platform-specific one? Yours, Linus Walleij ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform 2010-03-10 9:31 ` Linus Walleij @ 2010-03-10 10:11 ` Viresh KUMAR 2010-03-10 14:16 ` Paul Mundt 2010-03-11 6:43 ` Linus Walleij 0 siblings, 2 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-10 10:11 UTC (permalink / raw) To: linux-arm-kernel On 3/10/2010 3:01 PM, Linus Walleij wrote: > 2010/3/10 Viresh KUMAR <viresh.kumar@st.com>: >> Linus Walleij: >>> If this file is only supposed to be used from plat-spear/time.c, move it down >>> into plat-spear/gpt.h and #include "gpt.h" so noone else will >>> accidentally use it. >> >> GPT's on SPEAr can be used from time.c, platform specific drivers and machine >> specific drivers or any driver wishing to use hardware timer. >> In first two cases "gpt.h" will work, but in rest of cases we need gpt.h to be >> in plat-spear/include/plat >> >> Is it okay? > > If you have or have already planned to write such platform, machine > or subsystem drivers, it's OK, if there are no such users and you cannot > easily give one, it's overdesigned IMHO. Some realistic examples of such > drivers will make me change my mind :-) > > The reason I persist is that I've seen such unutilized timer API:s before and > no other user than the system timer in sight. I never understood what they > were to be used for, and I still don't, so help me understand. The kernel > has many internal timer API:s based on clockevent available already so > why add yet another, platform-specific one? > As you may have seen in spear.h files in mach folders, we have multiple hardware timers in our design (3 in spear3xx, 4 in spear6xx and each timer have two independent channels. That doubles the timers count, so it is 6 and 8). One timer (or two channels) are used by clock event and clock source, but rest of the timers are still available. So we need some way to export this functionality of our hardware. It can be considered simply as a driver for GPT. What do you say? viresh. ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform 2010-03-10 10:11 ` Viresh KUMAR @ 2010-03-10 14:16 ` Paul Mundt 2010-03-10 16:36 ` Thomas Gleixner 2010-03-11 6:43 ` Linus Walleij 1 sibling, 1 reply; 51+ messages in thread From: Paul Mundt @ 2010-03-10 14:16 UTC (permalink / raw) To: linux-arm-kernel On Wed, Mar 10, 2010 at 03:41:51PM +0530, Viresh KUMAR wrote: > On 3/10/2010 3:01 PM, Linus Walleij wrote: > > 2010/3/10 Viresh KUMAR <viresh.kumar@st.com>: > >> Linus Walleij: > >>> If this file is only supposed to be used from plat-spear/time.c, move it down > >>> into plat-spear/gpt.h and #include "gpt.h" so noone else will > >>> accidentally use it. > >> > >> GPT's on SPEAr can be used from time.c, platform specific drivers and machine > >> specific drivers or any driver wishing to use hardware timer. > >> In first two cases "gpt.h" will work, but in rest of cases we need gpt.h to be > >> in plat-spear/include/plat > >> > >> Is it okay? > > > > If you have or have already planned to write such platform, machine > > or subsystem drivers, it's OK, if there are no such users and you cannot > > easily give one, it's overdesigned IMHO. Some realistic examples of such > > drivers will make me change my mind :-) > > > > The reason I persist is that I've seen such unutilized timer API:s before and > > no other user than the system timer in sight. I never understood what they > > were to be used for, and I still don't, so help me understand. The kernel > > has many internal timer API:s based on clockevent available already so > > why add yet another, platform-specific one? > > > > As you may have seen in spear.h files in mach folders, we have multiple hardware > timers in our design (3 in spear3xx, 4 in spear6xx and each timer have two > independent channels. That doubles the timers count, so it is 6 and 8). > One timer (or two channels) are used by clock event and clock source, but rest of > the timers are still available. So we need some way to export this functionality > of our hardware. It can be considered simply as a driver for GPT. > > What do you say? > This is hardly a unique situation for your platform, this is true for most platforms. There's no reason why clockevents couldn't just be extended and drivers could then just grab unused clockevents and pin them accordingly. Most of the infrastructure is already in place for something like that, without really having to do anything special. Having said that, most drivers have pretty lame reasons for trying to get at fixed timer channels, and most of the time they can easily get by with an hrtimer instead. There's also the issue that you're effectively bypassing nohz by having some timer channel off on the side doing who knows what. You would need a pretty compelling reason for why you are sidestepping all of the existing infrastructure anyways. There are still some legitimate users for dedicated timers that we may want to have decoupled from sched_clock() (like the trace clock) and so on, but when people start rolling their own timer APIs it always sets off warning bells, as it's almost always because they want to do something in a driver that existing infrastructure already provides for them. In cases like these, it's better to see what precisely you plan to do with these timer channels before getting in to API semantics, though. ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform 2010-03-10 14:16 ` Paul Mundt @ 2010-03-10 16:36 ` Thomas Gleixner 2010-03-10 22:16 ` Tony Lindgren 0 siblings, 1 reply; 51+ messages in thread From: Thomas Gleixner @ 2010-03-10 16:36 UTC (permalink / raw) To: linux-arm-kernel On Wed, 10 Mar 2010, Paul Mundt wrote: > On Wed, Mar 10, 2010 at 03:41:51PM +0530, Viresh KUMAR wrote: > > As you may have seen in spear.h files in mach folders, we have multiple hardware > > timers in our design (3 in spear3xx, 4 in spear6xx and each timer have two > > independent channels. That doubles the timers count, so it is 6 and 8). > > One timer (or two channels) are used by clock event and clock source, but rest of > > the timers are still available. So we need some way to export this functionality > > of our hardware. It can be considered simply as a driver for GPT. > > > > What do you say? > > > This is hardly a unique situation for your platform, this is true for > most platforms. There's no reason why clockevents couldn't just be > extended and drivers could then just grab unused clockevents and pin them > accordingly. Most of the infrastructure is already in place for something > like that, without really having to do anything special. > > Having said that, most drivers have pretty lame reasons for trying to get > at fixed timer channels, and most of the time they can easily get by with > an hrtimer instead. There's also the issue that you're effectively > bypassing nohz by having some timer channel off on the side doing who > knows what. You would need a pretty compelling reason for why you are > sidestepping all of the existing infrastructure anyways. Right, and that's exactly the reason why we did not add the few missing bits to make clock events directly usable from drivers. Thanks, tglx ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform 2010-03-10 16:36 ` Thomas Gleixner @ 2010-03-10 22:16 ` Tony Lindgren 2010-03-10 23:29 ` Paul Mundt 0 siblings, 1 reply; 51+ messages in thread From: Tony Lindgren @ 2010-03-10 22:16 UTC (permalink / raw) To: linux-arm-kernel * Thomas Gleixner <tglx@linutronix.de> [100310 08:38]: > On Wed, 10 Mar 2010, Paul Mundt wrote: > > On Wed, Mar 10, 2010 at 03:41:51PM +0530, Viresh KUMAR wrote: > > > As you may have seen in spear.h files in mach folders, we have multiple hardware > > > timers in our design (3 in spear3xx, 4 in spear6xx and each timer have two > > > independent channels. That doubles the timers count, so it is 6 and 8). > > > One timer (or two channels) are used by clock event and clock source, but rest of > > > the timers are still available. So we need some way to export this functionality > > > of our hardware. It can be considered simply as a driver for GPT. > > > > > > What do you say? > > > > > This is hardly a unique situation for your platform, this is true for > > most platforms. There's no reason why clockevents couldn't just be > > extended and drivers could then just grab unused clockevents and pin them > > accordingly. Most of the infrastructure is already in place for something > > like that, without really having to do anything special. > > > > Having said that, most drivers have pretty lame reasons for trying to get > > at fixed timer channels, and most of the time they can easily get by with > > an hrtimer instead. There's also the issue that you're effectively > > bypassing nohz by having some timer channel off on the side doing who > > knows what. You would need a pretty compelling reason for why you are > > sidestepping all of the existing infrastructure anyways. > > Right, and that's exactly the reason why we did not add the few > missing bits to make clock events directly usable from drivers. Yeah still no direct users so far for the 12 hardware timers on omaps.. I guess the only use I could see is bit banging data over a few GPIO lines using a FIQ handler. Another thing to consider is that most likely all hardware timers are not able to wake up the system from idle, which would easily cause some mysterious errors for drivers. Tony ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform 2010-03-10 22:16 ` Tony Lindgren @ 2010-03-10 23:29 ` Paul Mundt 2010-03-10 23:42 ` Thomas Gleixner 0 siblings, 1 reply; 51+ messages in thread From: Paul Mundt @ 2010-03-10 23:29 UTC (permalink / raw) To: linux-arm-kernel On Wed, Mar 10, 2010 at 02:16:53PM -0800, Tony Lindgren wrote: > * Thomas Gleixner <tglx@linutronix.de> [100310 08:38]: > > On Wed, 10 Mar 2010, Paul Mundt wrote: > > > This is hardly a unique situation for your platform, this is true for > > > most platforms. There's no reason why clockevents couldn't just be > > > extended and drivers could then just grab unused clockevents and pin them > > > accordingly. Most of the infrastructure is already in place for something > > > like that, without really having to do anything special. > > > > > > Having said that, most drivers have pretty lame reasons for trying to get > > > at fixed timer channels, and most of the time they can easily get by with > > > an hrtimer instead. There's also the issue that you're effectively > > > bypassing nohz by having some timer channel off on the side doing who > > > knows what. You would need a pretty compelling reason for why you are > > > sidestepping all of the existing infrastructure anyways. > > > > Right, and that's exactly the reason why we did not add the few > > missing bits to make clock events directly usable from drivers. > > Yeah still no direct users so far for the 12 hardware timers on > omaps.. I guess the only use I could see is bit banging data > over a few GPIO lines using a FIQ handler. > > Another thing to consider is that most likely all hardware timers > are not able to wake up the system from idle, which would easily > cause some mysterious errors for drivers. > Even if most drivers shouldn't be touching clockevents directly, there are still legitimate cases. In SMP configurations where a single timer block is shared across multiple CPUs it would be easier to have the boot CPU register all of the timer channels under clockevents and have the secondaries grab one at random for setting up their local timers. (Even if they're not truly "local" timers, it's still a better situation than broadcast IPIs). clockevents would need some minor extension, including dealing with unregistration for the CPU hotplug case, but it's a pretty good fit for the problem otherwise. If all timer channels are equal then there's also the possibility of matching device IDs against the CPU's struct device, but depending on the CPU topology is a pretty dire hack, particularly as most timer channels have differing capabilities. ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform 2010-03-10 23:29 ` Paul Mundt @ 2010-03-10 23:42 ` Thomas Gleixner 0 siblings, 0 replies; 51+ messages in thread From: Thomas Gleixner @ 2010-03-10 23:42 UTC (permalink / raw) To: linux-arm-kernel On Thu, 11 Mar 2010, Paul Mundt wrote: > On Wed, Mar 10, 2010 at 02:16:53PM -0800, Tony Lindgren wrote: > > * Thomas Gleixner <tglx@linutronix.de> [100310 08:38]: > > > On Wed, 10 Mar 2010, Paul Mundt wrote: > > > > This is hardly a unique situation for your platform, this is true for > > > > most platforms. There's no reason why clockevents couldn't just be > > > > extended and drivers could then just grab unused clockevents and pin them > > > > accordingly. Most of the infrastructure is already in place for something > > > > like that, without really having to do anything special. > > > > > > > > Having said that, most drivers have pretty lame reasons for trying to get > > > > at fixed timer channels, and most of the time they can easily get by with > > > > an hrtimer instead. There's also the issue that you're effectively > > > > bypassing nohz by having some timer channel off on the side doing who > > > > knows what. You would need a pretty compelling reason for why you are > > > > sidestepping all of the existing infrastructure anyways. > > > > > > Right, and that's exactly the reason why we did not add the few > > > missing bits to make clock events directly usable from drivers. > > > > Yeah still no direct users so far for the 12 hardware timers on > > omaps.. I guess the only use I could see is bit banging data > > over a few GPIO lines using a FIQ handler. > > > > Another thing to consider is that most likely all hardware timers > > are not able to wake up the system from idle, which would easily > > cause some mysterious errors for drivers. > > > Even if most drivers shouldn't be touching clockevents directly, there > are still legitimate cases. In SMP configurations where a single timer > block is shared across multiple CPUs it would be easier to have the boot > CPU register all of the timer channels under clockevents and have the > secondaries grab one at random for setting up their local timers. (Even > if they're not truly "local" timers, it's still a better situation than > broadcast IPIs). clockevents would need some minor extension, including > dealing with unregistration for the CPU hotplug case, but it's a pretty > good fit for the problem otherwise. No objections against that, but that's not a use case for drivers and limited to (arch) core code functionality. Thanks, tglx ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform 2010-03-10 10:11 ` Viresh KUMAR 2010-03-10 14:16 ` Paul Mundt @ 2010-03-11 6:43 ` Linus Walleij 2010-03-11 9:47 ` Shiraz HASHIM 1 sibling, 1 reply; 51+ messages in thread From: Linus Walleij @ 2010-03-11 6:43 UTC (permalink / raw) To: linux-arm-kernel 2010/3/10 Viresh KUMAR <viresh.kumar@st.com>: > One timer (or two channels) are used by clock event and clock source, but rest of > the timers are still available. So we need some way to export this functionality > of our hardware. It can be considered simply as a driver for GPT. The timer people have already explained well enough I think, we have some 16 timers on U8500, one we use as clocksource, one for clock events and 14 are currently unused. I plan to add them as clock events as soon as there is some practical use for them. I think there is nothing stopping you from modelling some extra clock events for the remaining timers if you absolutely want to, the kernel will just disregard them currently, which is just as good/bad as the way you're exposing the custom API in these patches. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform 2010-03-11 6:43 ` Linus Walleij @ 2010-03-11 9:47 ` Shiraz HASHIM 2010-03-11 11:26 ` Linus Walleij 0 siblings, 1 reply; 51+ messages in thread From: Shiraz HASHIM @ 2010-03-11 9:47 UTC (permalink / raw) To: linux-arm-kernel Hello Linus, On 3/11/2010 12:13 PM, Linus Walleij wrote: > 2010/3/10 Viresh KUMAR <viresh.kumar@st.com>: > >> One timer (or two channels) are used by clock event and clock source, but rest of >> the timers are still available. So we need some way to export this functionality >> of our hardware. It can be considered simply as a driver for GPT. > > The timer people have already explained well enough I think, we have some 16 > timers on U8500, one we use as clocksource, one for clock events and 14 are > currently unused. I plan to add them as clock events as soon as there is some > practical use for them. > I think there is nothing stopping you from modelling some extra clock events > for the remaining timers if you absolutely want to, the kernel will > just disregard > them currently, which is just as good/bad as the way you're exposing the custom > API in these patches. Can we use clockevents directly? I though they are abstracted by the kernel framework and using them directly is not advisable/feasible. regards Shiraz ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform 2010-03-11 9:47 ` Shiraz HASHIM @ 2010-03-11 11:26 ` Linus Walleij 0 siblings, 0 replies; 51+ messages in thread From: Linus Walleij @ 2010-03-11 11:26 UTC (permalink / raw) To: linux-arm-kernel 2010/3/11 Shiraz HASHIM <shiraz.hashim@st.com>: > Can we use clockevents directly? I though they are abstracted by the kernel > framework and using them directly is not advisable/feasible. Not that I know, but as tglx says it might soon be possible to do so, and if you have a patch for using some surplus clockevents for this along with some example of it actually being used too, people will probably react, atleast they will have opinions. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 02/11] ST SPEAr: Added basic header files for SPEAr3xx machine family 2010-03-03 5:07 ` [PATCH 02/11] ST SPEAr: Added basic header files for SPEAr3xx machine family Viresh KUMAR 2010-03-03 5:07 ` [PATCH 03/11] ST SPEAr: Added basic header files for SPEAr6xx " Viresh KUMAR @ 2010-03-09 20:42 ` Linus Walleij 2010-03-10 6:01 ` Viresh KUMAR 2010-03-11 10:33 ` Russell King - ARM Linux 2 siblings, 1 reply; 51+ messages in thread From: Linus Walleij @ 2010-03-09 20:42 UTC (permalink / raw) To: linux-arm-kernel Hi Viresh, 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: > (...) > diff --git a/arch/arm/mach-spear3xx/include/mach/debug-macro.S b/arch/arm/mach-spear3xx/include/mach/debug-macro.S > new file mode 100644 > index 0000000..2f6c5bd > --- /dev/null > +++ b/arch/arm/mach-spear3xx/include/mach/debug-macro.S > @@ -0,0 +1,38 @@ > +/* > + * arch/arm/mach-spear3xx/include/mach/debug-macro.S > + * > + * Debugging macro include header spear3xx machine family > + * > + * Copyright (C) 2009 ST Microelectronics > + * Viresh Kumar<viresh.kumar@st.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#include <linux/amba/serial.h> > +#include <mach/spear.h> > + > + .macro addruart, rx > + mrc p15, 0, \rx, c1, c0 > + tst \rx, #1 @ MMU enabled? > + moveq \rx, =SPEAR3XX_ICM1_UART_BASE @ Physical base > + movne \rx, =VA_SPEAR3XX_ICM1_UART_BASE @ Virtual base > + .endm > + > + .macro senduart, rd, rx > + strb \rd, [\rx, #UART01x_DR] @ ASC_TX_BUFFER > + .endm > + > + .macro waituart, rd, rx > +1001: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER > + tst \rd, #UART01x_FR_TXFF @ TX_FULL > + bne 1001b > + .endm > + > + .macro busyuart, rd, rx > +1002: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER > + tst \rd, #UART011_FR_TXFE @ TX_EMPTY > + beq 1002b > + .endm Apart from that the base offset is named SPEAR6XX_ICM1_UART0_BASE this is the same file in 3xx and 6xx series. Can you rename the base offset to SPEARXXX_ICM1_UART0_BASE or something similar in both machines and move this file to plat-spear/include/plat/debug-macro.S? You'll probably need mach/include/mach/debug-macro.S to #include <plat/debug-macro.S> I think. > diff --git a/arch/arm/mach-spear6xx/include/mach/dma.h b/arch/arm/mach-spear6xx/include/mach/dma.h > new file mode 100644 > index 0000000..c4afd17 > --- /dev/null > +++ b/arch/arm/mach-spear6xx/include/mach/dma.h > @@ -0,0 +1,17 @@ > +/* > + * arch/arm/mach-spear6xx/include/mach/dma.h > + * > + * Generic SPEAr6XX machine family DMA support > + * > + * Copyright (C) 2009 ST Microelectronics > + * Rajeev Kumar<rajeev-dlh.kumar@st.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#ifndef __ASM_ARCH_DMA_H > +#define __ASM_ARCH_DMA_H > + > +#endif /* __ASM_ARCH_DMA_H */ Is this file needed? (Perhaps...) Anyway, the name of that #define should probably be __MACH_DMA_H if it shall match the filepath. > (...) > diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h > new file mode 100755 > index 0000000..d83dae9 > --- /dev/null > +++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h > @@ -0,0 +1,163 @@ > +/* > + * arch/arm/mach-spear3xx/include/mach/misc_regs.h > + * > + * Miscellaneous registers definitions for SPEAr3xx machine family > + * > + * Copyright (C) 2009 ST Microelectronics > + * Viresh Kumar<viresh.kumar@st.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#ifndef __ASM_MACH_MISC_REGS_H > +#define __ASM_MACH_MISC_REGS_H It's not __ASM_MACH* really, but just __MACH* if it's supposed to follow the filename... > + > +#include <mach/spear.h> > + > +#define MISC_BASE ? ? ? ? ? ? ?VA_SPEAR3XX_ICM3_MISC_REG_BASE > + > +#define SOC_CFG_CTR ? ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x000)) > +#define DIAG_CFG_CTR ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x004)) > +#define PLL1_CTR ? ? ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x008)) > +#define PLL1_FRQ ? ? ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x00C)) > +#define PLL1_MOD ? ? ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x010)) > +#define PLL2_CTR ? ? ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x014)) > +/* PLL_CTR register masks */ > +#define PLL_ENABLE ? ? ? ? ? ? 2 > +#define PLL_MODE_SHIFT ? ? ? ? 4 > +#define PLL_MODE_MASK ? ? ? ? ?0x3 > +#define PLL_MODE_NORMAL ? ? ? ? ? ? ? ?0 > +#define PLL_MODE_FRACTION ? ? ?1 > +#define PLL_MODE_DITH_DSB ? ? ?2 > +#define PLL_MODE_DITH_SSB ? ? ?3 > + > +#define PLL2_FRQ ? ? ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x018)) > +/* PLL FRQ register masks */ > +#define PLL_DIV_N_SHIFT ? ? ? ? ? ? ? ?0 > +#define PLL_DIV_N_MASK ? ? ? ? 0xFF > +#define PLL_DIV_P_SHIFT ? ? ? ? ? ? ? ?8 > +#define PLL_DIV_P_MASK ? ? ? ? 0x7 > +#define PLL_NORM_FDBK_M_SHIFT ?24 > +#define PLL_NORM_FDBK_M_MASK ? 0xFF > +#define PLL_DITH_FDBK_M_SHIFT ?16 > +#define PLL_DITH_FDBK_M_MASK ? 0xFFFF > + > +#define PLL2_MOD ? ? ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x01C)) > +#define PLL_CLK_CFG ? ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x020)) > +#define CORE_CLK_CFG ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x024)) > +/* CORE CLK CFG register masks */ > +#define PLL_HCLK_RATIO_SHIFT ? 10 > +#define PLL_HCLK_RATIO_MASK ? ?0x3 > +#define HCLK_PCLK_RATIO_SHIFT ?8 > +#define HCLK_PCLK_RATIO_MASK ? 0x3 > + > +#define PERIP_CLK_CFG ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x028)) > +/* PERIP_CLK_CFG register masks */ > +#define UART_CLK_SHIFT ? ? ? ? 4 > +#define UART_CLK_MASK ? ? ? ? ?0x1 > +#define FIRDA_CLK_SHIFT ? ? ? ? ? ? ? ?5 > +#define FIRDA_CLK_MASK ? ? ? ? 0x3 > +#define GPT0_CLK_SHIFT ? ? ? ? 8 > +#define GPT1_CLK_SHIFT ? ? ? ? 11 > +#define GPT2_CLK_SHIFT ? ? ? ? 12 > +#define GPT_CLK_MASK ? ? ? ? ? 0x1 > +#define AUX_CLK_PLL3_MASK ? ? ?0 > +#define AUX_CLK_PLL1_MASK ? ? ?1 > + > +#define PERIP1_CLK_ENB ? ? ? ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x02C)) > +/* PERIP1_CLK_ENB register masks */ > +#define UART_CLK_ENB ? ? ? ? ? 3 > +#define SSP_CLK_ENB ? ? ? ? ? ?5 > +#define I2C_CLK_ENB ? ? ? ? ? ?7 > +#define JPEG_CLK_ENB ? ? ? ? ? 8 > +#define FIRDA_CLK_ENB ? ? ? ? ?10 > +#define GPT1_CLK_ENB ? ? ? ? ? 11 > +#define GPT2_CLK_ENB ? ? ? ? ? 12 > +#define ADC_CLK_ENB ? ? ? ? ? ?15 > +#define RTC_CLK_ENB ? ? ? ? ? ?17 > +#define GPIO_CLK_ENB ? ? ? ? ? 18 > +#define DMA_CLK_ENB ? ? ? ? ? ?19 > +#define SMI_CLK_ENB ? ? ? ? ? ?21 > +#define GMAC_CLK_ENB ? ? ? ? ? 23 > +#define USBD_CLK_ENB ? ? ? ? ? 24 > +#define USBH_CLK_ENB ? ? ? ? ? 25 > +#define C3_CLK_ENB ? ? ? ? ? ? 31 > + > +#define SOC_CORE_ID ? ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x030)) > +#define RAS_CLK_ENB ? ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x034)) > +#define PERIP1_SOF_RST ? ? ? ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x038)) > +/* PERIP1_SOF_RST register masks */ > +#define JPEG_SOF_RST ? ? ? ? ? 8 > + > +#define SOC_USER_ID ? ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x03C)) > +#define RAS_SOF_RST ? ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x040)) > +#define PRSC1_CLK_CFG ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x044)) > +#define PRSC2_CLK_CFG ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x048)) > +#define PRSC3_CLK_CFG ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x04C)) > +/* gpt synthesizer register masks */ > +#define GPT_MSCALE_SHIFT ? ? ? 0 > +#define GPT_MSCALE_MASK ? ? ? ? ? ? ? ?0xFFF > +#define GPT_NSCALE_SHIFT ? ? ? 12 > +#define GPT_NSCALE_MASK ? ? ? ? ? ? ? ?0xF > + > +#define AMEM_CLK_CFG ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x050)) > +#define EXPI_CLK_CFG ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x054)) > +#define CLCD_CLK_SYNT ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x05C)) > +#define FIRDA_CLK_SYNT ? ? ? ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x060)) > +#define UART_CLK_SYNT ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x064)) > +#define GMAC_CLK_SYNT ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x068)) > +#define RAS1_CLK_SYNT ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x06C)) > +#define RAS2_CLK_SYNT ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x070)) > +#define RAS3_CLK_SYNT ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x074)) > +#define RAS4_CLK_SYNT ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x078)) > +/* aux clk synthesiser register masks for irda to ras4 */ > +#define AUX_EQ_SEL_SHIFT ? ? ? 30 > +#define AUX_EQ_SEL_MASK ? ? ? ? ? ? ? ?1 > +#define AUX_EQ1_SEL ? ? ? ? ? ?0 > +#define AUX_EQ2_SEL ? ? ? ? ? ?1 > +#define AUX_XSCALE_SHIFT ? ? ? 16 > +#define AUX_XSCALE_MASK ? ? ? ? ? ? ? ?0xFFF > +#define AUX_YSCALE_SHIFT ? ? ? 0 > +#define AUX_YSCALE_MASK ? ? ? ? ? ? ? ?0xFFF > + > +#define ICM1_ARB_CFG ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x07C)) > +#define ICM2_ARB_CFG ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x080)) > +#define ICM3_ARB_CFG ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x084)) > +#define ICM4_ARB_CFG ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x088)) > +#define ICM5_ARB_CFG ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x08C)) > +#define ICM6_ARB_CFG ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x090)) > +#define ICM7_ARB_CFG ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x094)) > +#define ICM8_ARB_CFG ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x098)) > +#define ICM9_ARB_CFG ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x09C)) > +#define DMA_CHN_CFG ? ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x0A0)) > +#define USB2_PHY_CFG ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x0A4)) > +#define GMAC_CFG_CTR ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x0A8)) > +#define EXPI_CFG_CTR ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x0AC)) > +#define PRC1_LOCK_CTR ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x0C0)) > +#define PRC2_LOCK_CTR ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x0C4)) > +#define PRC3_LOCK_CTR ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x0C8)) > +#define PRC4_LOCK_CTR ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x0CC)) > +#define PRC1_IRQ_CTR ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x0D0)) > +#define PRC2_IRQ_CTR ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x0D4)) > +#define PRC3_IRQ_CTR ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x0D8)) > +#define PRC4_IRQ_CTR ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x0DC)) > +#define PWRDOWN_CFG_CTR ? ? ? ?((unsigned int *)(MISC_BASE + 0x0E0)) > +#define COMPSSTL_1V8_CFG ? ? ? ((unsigned int *)(MISC_BASE + 0x0E4)) > +#define COMPSSTL_2V5_CFG ? ? ? ((unsigned int *)(MISC_BASE + 0x0E8)) > +#define COMPCOR_3V3_CFG ? ? ? ?((unsigned int *)(MISC_BASE + 0x0EC)) > +#define SSTLPAD_CFG_CTR ? ? ? ?((unsigned int *)(MISC_BASE + 0x0F0)) > +#define BIST1_CFG_CTR ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x0F4)) > +#define BIST2_CFG_CTR ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x0F8)) > +#define BIST3_CFG_CTR ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x0FC)) > +#define BIST4_CFG_CTR ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x100)) > +#define BIST5_CFG_CTR ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x104)) > +#define BIST1_STS_RES ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x108)) > +#define BIST2_STS_RES ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x10C)) > +#define BIST3_STS_RES ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x110)) > +#define BIST4_STS_RES ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x114)) > +#define BIST5_STS_RES ? ? ? ? ?((unsigned int *)(MISC_BASE + 0x118)) > +#define SYSERR_CFG_CTR ? ? ? ? ? ? ? ? ((unsigned int *)(MISC_BASE + 0x11C)) > + > +#endif /* __ASM_MACH_MISC_REGS_H */ Personally I like to push down these definitions into the actual driver files, so that all PLL+CLK stuff goes into clock.c, all GPT stuff into timer.c etc. It has the convenience of easily finding everything in a single file and at the same time surely blocking some other driver from poking around in the same registers. If you want to keep this file anyway, move it from mach-spear3xx/include/mach to just mach-spear3xx and include like this: #include "misc_regs.h" and thus avoid the entire drivers/* tree (etc) from being able to #include <mach/misc_regs.h> because surely any machine-specific special driver using these very machine-specific registers will be in mach-spear3xx/ anyway. > (...) > diff --git a/arch/arm/mach-spear3xx/include/mach/system.h b/arch/arm/mach-spear3xx/include/mach/system.h > new file mode 100644 > index 0000000..b7bc53f > --- /dev/null > +++ b/arch/arm/mach-spear3xx/include/mach/system.h > @@ -0,0 +1,41 @@ > +/* > + * arch/arm/mach-spear3xx/include/mach/system.h > + * > + * SPEAr3xx Machine family specific architecture functions > + * > + * Copyright (C) 2009 ST Microelectronics > + * Viresh Kumar<viresh.kumar@st.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#ifndef __ASM_MACH_SYSTEM_H > +#define __ASM_MACH_SYSTEM_H Again __MACH_SYSTEM_H > + > +#include <linux/io.h> > +#include <linux/sysctl_sp810.h> In regard to earlier comment: #include <asm/hardware/sysctl_sp810.h> > +#include <mach/spear.h> > + > +static inline void arch_idle(void) > +{ > + ? ? ? /* > + ? ? ? ?* This should do all the clock switching > + ? ? ? ?* and wait for interrupt tricks > + ? ? ? ?*/ > + ? ? ? cpu_do_idle(); > +} > + > +static inline void arch_reset(char mode, const char *cmd) > +{ > + ? ? ? if (mode == 's') { > + ? ? ? ? ? ? ? /* software reset, Jump into ROM at address 0 */ > + ? ? ? ? ? ? ? cpu_reset(0); > + ? ? ? } else { > + ? ? ? ? ? ? ? /* hardware reset, Use on-chip reset capability */ > + ? ? ? ? ? ? ? sysctl_soft_reset(SPEAR3XX_ICM3_SYS_CTRL_BASE); > + ? ? ? } > +} > + > +#endif /* __ASM_MACH_SYSTEM_H */ Again this file is identical to the same file for 6xx. Define a generic SPEAR_ICM3_SYS_CTRL_BASE or so and move to plat-spear/include/plat/system.h (I don't know how this works, perhaps you have to have a skeleton mach/include/mach/system.h that will just #include <plat/system.h> for this to work.) > diff --git a/arch/arm/mach-spear3xx/include/mach/timex.h b/arch/arm/mach-spear3xx/include/mach/timex.h > new file mode 100644 > index 0000000..29708db > --- /dev/null > +++ b/arch/arm/mach-spear3xx/include/mach/timex.h > @@ -0,0 +1,19 @@ > +/* > + * arch/arm/mach-spear3xx/include/mach/timex.h > + * > + * SPEAr3XX machine family specific timex definitions > + * > + * Copyright (C) 2009 ST Microelectronics > + * Viresh Kumar<viresh.kumar@st.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#ifndef __ASM_MACH_TIMEX_H > +#define __ASM_MACH_TIMEX_H Again __MACH_TIMEX_H > + > +#define CLOCK_TICK_RATE ? ? ? ? ? ? ? ? ? ? ? ?48000000 > + > +#endif /* __ASM_MACH_TIMEX_H */ > diff --git a/arch/arm/mach-spear3xx/include/mach/uncompress.h b/arch/arm/mach-spear3xx/include/mach/uncompress.h > new file mode 100644 > index 0000000..08ec3b1 > --- /dev/null > +++ b/arch/arm/mach-spear3xx/include/mach/uncompress.h > @@ -0,0 +1,43 @@ > +/* > + * arch/arm/mach-spear3xx/include/mach/uncompress.h > + * > + * Serial port stubs for kernel decompress status messages > + * > + * Copyright (C) 2009 ST Microelectronics > + * Viresh Kumar<viresh.kumar@st.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#include <linux/io.h> > +#include <linux/amba/serial.h> > +#include <mach/spear.h> > + > +#ifndef __ASM_MACH_UNCOMPRESS_H > +#define __ASM_MACH_UNCOMPRESS_H > +/* > + * This does not append a newline > + */ > +static inline void putc(int c) > +{ > + ? ? ? void __iomem *base = (void __iomem *)SPEAR3XX_ICM1_UART_BASE; > + > + ? ? ? while (readl(base + UART01x_FR) & UART01x_FR_TXFF) > + ? ? ? ? ? ? ? barrier(); > + > + ? ? ? writel(c, base + UART01x_DR); > +} > + > +static inline void flush(void) > +{ > +} > + > +/* > + * nothing to do > + */ > +#define arch_decomp_setup() > +#define arch_decomp_wdog() > + > +#endif /* __ASM_MACH_UNCOMPRESS_H */ Apart from that the base offset is named SPEAR6XX_ICM1_UART0_BASE this is the same file in 3xx and 6xx series. Can you rename the base offset to SPEARXXX_ICM1_UART0_BASE or something similar in both machines and move this file to plat-spear/include/plat/uncompress.h? (Perhaps mach/include/mach/uncompress.h has to contain a single #include <plat/uncompress.h> I haven't tested.) > diff --git a/arch/arm/mach-spear3xx/include/mach/vmalloc.h b/arch/arm/mach-spear3xx/include/mach/vmalloc.h > new file mode 100644 > index 0000000..4f236f3 > --- /dev/null > +++ b/arch/arm/mach-spear3xx/include/mach/vmalloc.h > @@ -0,0 +1,22 @@ > +/* > + * arch/arm/mach-spear3xx/include/mach/vmalloc.h > + * > + * Defining Vmalloc area for SPEAr3xx machine family > + * > + * Copyright (C) 2009 ST Microelectronics > + * Viresh Kumar<viresh.kumar@st.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#ifndef __ASM_MACH_VMALLOC_H > +#define __ASM_MACH_VMALLOC_H Again __MACH_VMALLOC_H > + > +#include <mach/memory.h> > + > +#define VMALLOC_SIZE ? ? ? ? ? (0x30000000) > +#define VMALLOC_END ? ? ? ? ? ?(PAGE_OFFSET + VMALLOC_SIZE) > + > +#endif /* __ASM_MACH_VMALLOC_H */ This is exactly the same file as in spear6xx again move to plat-spear. Might need a single #include <plat/vmalloc.h> Most comments on this file are in relation to the 6xx header files, so they apply to that patch as well. Mostly "move to plat-spear" stuff. Just replace in the proper places. (The entry-macro is unique for both platforms though!) Yours, Linus Walleij ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 02/11] ST SPEAr: Added basic header files for SPEAr3xx machine family 2010-03-09 20:42 ` [PATCH 02/11] ST SPEAr: Added basic header files for SPEAr3xx machine family Linus Walleij @ 2010-03-10 6:01 ` Viresh KUMAR 2010-03-10 6:07 ` Linus Walleij 0 siblings, 1 reply; 51+ messages in thread From: Viresh KUMAR @ 2010-03-10 6:01 UTC (permalink / raw) To: linux-arm-kernel Linus, On 3/10/2010 2:12 AM, Linus Walleij wrote: > Hi Viresh, > > 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: >> (...) >> diff --git a/arch/arm/mach-spear3xx/include/mach/debug-macro.S b/arch/arm/mach-spear3xx/include/mach/debug-macro.S >> + .macro busyuart, rd, rx >> +1002: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER >> + tst \rd, #UART011_FR_TXFE @ TX_EMPTY >> + beq 1002b >> + .endm > > Apart from that the base offset is named SPEAR6XX_ICM1_UART0_BASE > this is the same file in 3xx and 6xx series. Can you rename the base offset > to SPEARXXX_ICM1_UART0_BASE or something similar in both machines > and move this file to plat-spear/include/plat/debug-macro.S? OK. This will be done. > > You'll probably need mach/include/mach/debug-macro.S to > #include <plat/debug-macro.S> I think. > I think so. >> diff --git a/arch/arm/mach-spear6xx/include/mach/dma.h b/arch/arm/mach-spear6xx/include/mach/dma.h >> new file mode 100644 >> index 0000000..c4afd17 >> --- /dev/null >> +++ b/arch/arm/mach-spear6xx/include/mach/dma.h >> @@ -0,0 +1,17 @@ >> +/* >> + * arch/arm/mach-spear6xx/include/mach/dma.h >> + * >> + * Generic SPEAr6XX machine family DMA support >> + * >> + * Copyright (C) 2009 ST Microelectronics >> + * Rajeev Kumar<rajeev-dlh.kumar@st.com> >> + * >> + * This file is licensed under the terms of the GNU General Public >> + * License version 2. This program is licensed "as is" without any >> + * warranty of any kind, whether express or implied. >> + */ >> + >> +#ifndef __ASM_ARCH_DMA_H >> +#define __ASM_ARCH_DMA_H >> + >> +#endif /* __ASM_ARCH_DMA_H */ > > Is this file needed? (Perhaps...) Anyway, the name of that #define should > probably be __MACH_DMA_H if it shall match the filepath. > It is not required now, was required by earlier kernels. will be removed. >> (...) >> diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h >> new file mode 100755 >> index 0000000..d83dae9 >> +#ifndef __ASM_MACH_MISC_REGS_H >> +#define __ASM_MACH_MISC_REGS_H > > It's not __ASM_MACH* really, but just __MACH* if it's supposed to follow > the filename... Will be done globally. > >> + >> +#include <mach/spear.h> >> + >> +#define MISC_BASE VA_SPEAR3XX_ICM3_MISC_REG_BASE >> + >> +#define SOC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x000)) >> +#define DIAG_CFG_CTR ((unsigned int *)(MISC_BASE + 0x004)) >> +#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x008)) >> +#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x00C)) >> +#define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x010)) >> +#define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x014)) >> +/* PLL_CTR register masks */ >> +#define PLL_ENABLE 2 >> +#define PLL_MODE_SHIFT 4 >> +#define PLL_MODE_MASK 0x3 >> +#define PLL_MODE_NORMAL 0 >> +#define PLL_MODE_FRACTION 1 >> +#define PLL_MODE_DITH_DSB 2 >> +#define PLL_MODE_DITH_SSB 3 >> + >> +#define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x018)) >> +/* PLL FRQ register masks */ >> +#define PLL_DIV_N_SHIFT 0 >> +#define PLL_DIV_N_MASK 0xFF >> +#define PLL_DIV_P_SHIFT 8 >> +#define PLL_DIV_P_MASK 0x7 >> +#define PLL_NORM_FDBK_M_SHIFT 24 >> +#define PLL_NORM_FDBK_M_MASK 0xFF >> +#define PLL_DITH_FDBK_M_SHIFT 16 >> +#define PLL_DITH_FDBK_M_MASK 0xFFFF >> + >> +#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C)) >> +#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020)) >> +#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024)) >> +/* CORE CLK CFG register masks */ >> +#define PLL_HCLK_RATIO_SHIFT 10 >> +#define PLL_HCLK_RATIO_MASK 0x3 >> +#define HCLK_PCLK_RATIO_SHIFT 8 >> +#define HCLK_PCLK_RATIO_MASK 0x3 >> + >> +#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x028)) >> +/* PERIP_CLK_CFG register masks */ >> +#define UART_CLK_SHIFT 4 >> +#define UART_CLK_MASK 0x1 >> +#define FIRDA_CLK_SHIFT 5 >> +#define FIRDA_CLK_MASK 0x3 >> +#define GPT0_CLK_SHIFT 8 >> +#define GPT1_CLK_SHIFT 11 >> +#define GPT2_CLK_SHIFT 12 >> +#define GPT_CLK_MASK 0x1 >> +#define AUX_CLK_PLL3_MASK 0 >> +#define AUX_CLK_PLL1_MASK 1 >> + >> +#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C)) >> +/* PERIP1_CLK_ENB register masks */ >> +#define UART_CLK_ENB 3 >> +#define SSP_CLK_ENB 5 >> +#define I2C_CLK_ENB 7 >> +#define JPEG_CLK_ENB 8 >> +#define FIRDA_CLK_ENB 10 >> +#define GPT1_CLK_ENB 11 >> +#define GPT2_CLK_ENB 12 >> +#define ADC_CLK_ENB 15 >> +#define RTC_CLK_ENB 17 >> +#define GPIO_CLK_ENB 18 >> +#define DMA_CLK_ENB 19 >> +#define SMI_CLK_ENB 21 >> +#define GMAC_CLK_ENB 23 >> +#define USBD_CLK_ENB 24 >> +#define USBH_CLK_ENB 25 >> +#define C3_CLK_ENB 31 >> + >> +#define SOC_CORE_ID ((unsigned int *)(MISC_BASE + 0x030)) >> +#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x034)) >> +#define PERIP1_SOF_RST ((unsigned int *)(MISC_BASE + 0x038)) >> +/* PERIP1_SOF_RST register masks */ >> +#define JPEG_SOF_RST 8 >> + >> +#define SOC_USER_ID ((unsigned int *)(MISC_BASE + 0x03C)) >> +#define RAS_SOF_RST ((unsigned int *)(MISC_BASE + 0x040)) >> +#define PRSC1_CLK_CFG ((unsigned int *)(MISC_BASE + 0x044)) >> +#define PRSC2_CLK_CFG ((unsigned int *)(MISC_BASE + 0x048)) >> +#define PRSC3_CLK_CFG ((unsigned int *)(MISC_BASE + 0x04C)) >> +/* gpt synthesizer register masks */ >> +#define GPT_MSCALE_SHIFT 0 >> +#define GPT_MSCALE_MASK 0xFFF >> +#define GPT_NSCALE_SHIFT 12 >> +#define GPT_NSCALE_MASK 0xF >> + >> +#define AMEM_CLK_CFG ((unsigned int *)(MISC_BASE + 0x050)) >> +#define EXPI_CLK_CFG ((unsigned int *)(MISC_BASE + 0x054)) >> +#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x05C)) >> +#define FIRDA_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x060)) >> +#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x064)) >> +#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x068)) >> +#define RAS1_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x06C)) >> +#define RAS2_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x070)) >> +#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074)) >> +#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078)) >> +/* aux clk synthesiser register masks for irda to ras4 */ >> +#define AUX_EQ_SEL_SHIFT 30 >> +#define AUX_EQ_SEL_MASK 1 >> +#define AUX_EQ1_SEL 0 >> +#define AUX_EQ2_SEL 1 >> +#define AUX_XSCALE_SHIFT 16 >> +#define AUX_XSCALE_MASK 0xFFF >> +#define AUX_YSCALE_SHIFT 0 >> +#define AUX_YSCALE_MASK 0xFFF >> + >> +#define ICM1_ARB_CFG ((unsigned int *)(MISC_BASE + 0x07C)) >> +#define ICM2_ARB_CFG ((unsigned int *)(MISC_BASE + 0x080)) >> +#define ICM3_ARB_CFG ((unsigned int *)(MISC_BASE + 0x084)) >> +#define ICM4_ARB_CFG ((unsigned int *)(MISC_BASE + 0x088)) >> +#define ICM5_ARB_CFG ((unsigned int *)(MISC_BASE + 0x08C)) >> +#define ICM6_ARB_CFG ((unsigned int *)(MISC_BASE + 0x090)) >> +#define ICM7_ARB_CFG ((unsigned int *)(MISC_BASE + 0x094)) >> +#define ICM8_ARB_CFG ((unsigned int *)(MISC_BASE + 0x098)) >> +#define ICM9_ARB_CFG ((unsigned int *)(MISC_BASE + 0x09C)) >> +#define DMA_CHN_CFG ((unsigned int *)(MISC_BASE + 0x0A0)) >> +#define USB2_PHY_CFG ((unsigned int *)(MISC_BASE + 0x0A4)) >> +#define GMAC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0A8)) >> +#define EXPI_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0AC)) >> +#define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C0)) >> +#define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C4)) >> +#define PRC3_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C8)) >> +#define PRC4_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0CC)) >> +#define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D0)) >> +#define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D4)) >> +#define PRC3_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D8)) >> +#define PRC4_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0DC)) >> +#define PWRDOWN_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0E0)) >> +#define COMPSSTL_1V8_CFG ((unsigned int *)(MISC_BASE + 0x0E4)) >> +#define COMPSSTL_2V5_CFG ((unsigned int *)(MISC_BASE + 0x0E8)) >> +#define COMPCOR_3V3_CFG ((unsigned int *)(MISC_BASE + 0x0EC)) >> +#define SSTLPAD_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F0)) >> +#define BIST1_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F4)) >> +#define BIST2_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F8)) >> +#define BIST3_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0FC)) >> +#define BIST4_CFG_CTR ((unsigned int *)(MISC_BASE + 0x100)) >> +#define BIST5_CFG_CTR ((unsigned int *)(MISC_BASE + 0x104)) >> +#define BIST1_STS_RES ((unsigned int *)(MISC_BASE + 0x108)) >> +#define BIST2_STS_RES ((unsigned int *)(MISC_BASE + 0x10C)) >> +#define BIST3_STS_RES ((unsigned int *)(MISC_BASE + 0x110)) >> +#define BIST4_STS_RES ((unsigned int *)(MISC_BASE + 0x114)) >> +#define BIST5_STS_RES ((unsigned int *)(MISC_BASE + 0x118)) >> +#define SYSERR_CFG_CTR ((unsigned int *)(MISC_BASE + 0x11C)) >> + >> +#endif /* __ASM_MACH_MISC_REGS_H */ > > Personally I like to push down these definitions into the actual driver files, > so that all PLL+CLK stuff goes into clock.c, all GPT stuff into timer.c etc. > It has the convenience of easily finding everything in a single file and > at the same time surely blocking some other driver from poking around > in the same registers. Background: This file defines miscellaneous registers for spear machines. They provide features like enabling/disabling peripherals, clocks, selecting clock sources, etc. I wanted to keep this file because, i didn't wanted people using same miscellaneous registers make different macros. It is actually like a module for machines, and so this can be kept separate. > > If you want to keep this file anyway, move it from mach-spear3xx/include/mach > to just mach-spear3xx and include like this: #include "misc_regs.h" and > thus avoid the entire drivers/* tree (etc) from being able to #include > <mach/misc_regs.h> > because surely any machine-specific special driver using these very > machine-specific > registers will be in mach-spear3xx/ anyway. Surely, any standard driver will not use them. Actually we have kept clock framework code common to different machines in plat-spear. And here we need to use misc_regs.h, for this reason i kept it in mach/include/mach. Is it Okay? > >> (...) >> diff --git a/arch/arm/mach-spear3xx/include/mach/system.h b/arch/arm/mach-spear3xx/include/mach/system.h >> new file mode 100644 >> index 0000000..b7bc53f >> + >> +#ifndef __ASM_MACH_SYSTEM_H >> +#define __ASM_MACH_SYSTEM_H > > Again __MACH_SYSTEM_H > >> + >> +#include <linux/io.h> >> +#include <linux/sysctl_sp810.h> > > In regard to earlier comment: > #include <asm/hardware/sysctl_sp810.h> OK. > >> +#include <mach/spear.h> >> + >> +static inline void arch_idle(void) >> +{ >> + /* >> + * This should do all the clock switching >> + * and wait for interrupt tricks >> + */ >> + cpu_do_idle(); >> +} >> + >> +static inline void arch_reset(char mode, const char *cmd) >> +{ >> + if (mode == 's') { >> + /* software reset, Jump into ROM at address 0 */ >> + cpu_reset(0); >> + } else { >> + /* hardware reset, Use on-chip reset capability */ >> + sysctl_soft_reset(SPEAR3XX_ICM3_SYS_CTRL_BASE); >> + } >> +} >> + >> +#endif /* __ASM_MACH_SYSTEM_H */ > > Again this file is identical to the same file for 6xx. Define a generic > SPEAR_ICM3_SYS_CTRL_BASE or so and move to > plat-spear/include/plat/system.h > OK. > (I don't know how this works, perhaps you have to have a skeleton > mach/include/mach/system.h that will just #include <plat/system.h> > for this to work.) Yes. > >> diff --git a/arch/arm/mach-spear3xx/include/mach/timex.h b/arch/arm/mach-spear3xx/include/mach/timex.h >> new file mode 100644 >> index 0000000..29708db >> --- /dev/null >> +++ b/arch/arm/mach-spear3xx/include/mach/timex.h >> @@ -0,0 +1,19 @@ >> +/* >> + * arch/arm/mach-spear3xx/include/mach/timex.h >> + * >> + * SPEAr3XX machine family specific timex definitions >> + * >> + * Copyright (C) 2009 ST Microelectronics >> + * Viresh Kumar<viresh.kumar@st.com> >> + * >> + * This file is licensed under the terms of the GNU General Public >> + * License version 2. This program is licensed "as is" without any >> + * warranty of any kind, whether express or implied. >> + */ >> + >> +#ifndef __ASM_MACH_TIMEX_H >> +#define __ASM_MACH_TIMEX_H > > Again __MACH_TIMEX_H OK > >> + >> +#define CLOCK_TICK_RATE 48000000 >> + >> +#endif /* __ASM_MACH_TIMEX_H */ >> diff --git a/arch/arm/mach-spear3xx/include/mach/uncompress.h b/arch/arm/mach-spear3xx/include/mach/uncompress.h >> new file mode 100644 >> index 0000000..08ec3b1 >> --- /dev/null >> +++ b/arch/arm/mach-spear3xx/include/mach/uncompress.h >> @@ -0,0 +1,43 @@ >> +/* >> + * arch/arm/mach-spear3xx/include/mach/uncompress.h >> + * >> + * Serial port stubs for kernel decompress status messages >> + * >> + * Copyright (C) 2009 ST Microelectronics >> + * Viresh Kumar<viresh.kumar@st.com> >> + * >> + * This file is licensed under the terms of the GNU General Public >> + * License version 2. This program is licensed "as is" without any >> + * warranty of any kind, whether express or implied. >> + */ >> + >> +#include <linux/io.h> >> +#include <linux/amba/serial.h> >> +#include <mach/spear.h> >> + >> +#ifndef __ASM_MACH_UNCOMPRESS_H >> +#define __ASM_MACH_UNCOMPRESS_H >> +/* >> + * This does not append a newline >> + */ >> +static inline void putc(int c) >> +{ >> + void __iomem *base = (void __iomem *)SPEAR3XX_ICM1_UART_BASE; >> + >> + while (readl(base + UART01x_FR) & UART01x_FR_TXFF) >> + barrier(); >> + >> + writel(c, base + UART01x_DR); >> +} >> + >> +static inline void flush(void) >> +{ >> +} >> + >> +/* >> + * nothing to do >> + */ >> +#define arch_decomp_setup() >> +#define arch_decomp_wdog() >> + >> +#endif /* __ASM_MACH_UNCOMPRESS_H */ > > Apart from that the base offset is named SPEAR6XX_ICM1_UART0_BASE > this is the same file in 3xx and 6xx series. Can you rename the base offset > to SPEARXXX_ICM1_UART0_BASE or something similar in both machines > and move this file to plat-spear/include/plat/uncompress.h? OK > > (Perhaps mach/include/mach/uncompress.h has to contain a single > #include <plat/uncompress.h> I haven't tested.) yes, this is required. > >> diff --git a/arch/arm/mach-spear3xx/include/mach/vmalloc.h b/arch/arm/mach-spear3xx/include/mach/vmalloc.h >> new file mode 100644 >> index 0000000..4f236f3 >> --- /dev/null >> +++ b/arch/arm/mach-spear3xx/include/mach/vmalloc.h >> @@ -0,0 +1,22 @@ >> +/* >> + * arch/arm/mach-spear3xx/include/mach/vmalloc.h >> + * >> + * Defining Vmalloc area for SPEAr3xx machine family >> + * >> + * Copyright (C) 2009 ST Microelectronics >> + * Viresh Kumar<viresh.kumar@st.com> >> + * >> + * This file is licensed under the terms of the GNU General Public >> + * License version 2. This program is licensed "as is" without any >> + * warranty of any kind, whether express or implied. >> + */ >> + >> +#ifndef __ASM_MACH_VMALLOC_H >> +#define __ASM_MACH_VMALLOC_H > > Again __MACH_VMALLOC_H > >> + >> +#include <mach/memory.h> >> + >> +#define VMALLOC_SIZE (0x30000000) >> +#define VMALLOC_END (PAGE_OFFSET + VMALLOC_SIZE) >> + >> +#endif /* __ASM_MACH_VMALLOC_H */ > > This is exactly the same file as in spear6xx again move to plat-spear. > Might need a single #include <plat/vmalloc.h> > > Most comments on this file are in relation to the 6xx header files, so they > apply to that patch as well. Mostly "move to plat-spear" stuff. Just > replace in the proper places. > > (The entry-macro is unique for both platforms though!) OK. will be done. viresh kumar. ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 02/11] ST SPEAr: Added basic header files for SPEAr3xx machine family 2010-03-10 6:01 ` Viresh KUMAR @ 2010-03-10 6:07 ` Linus Walleij 0 siblings, 0 replies; 51+ messages in thread From: Linus Walleij @ 2010-03-10 6:07 UTC (permalink / raw) To: linux-arm-kernel 2010/3/10 Viresh KUMAR <viresh.kumar@st.com>: > On 3/10/2010 2:12 AM, Linus Walleij wrote: >> If you want to keep this file anyway, move it from mach-spear3xx/include/mach >> to just mach-spear3xx and include like this: #include "misc_regs.h" and >> thus avoid the entire drivers/* tree (etc) from being able to #include >> <mach/misc_regs.h> >> because surely any machine-specific special driver using these very >> machine-specific >> registers will be in mach-spear3xx/ anyway. > > Surely, any standard driver will not use them. Actually we have kept clock > framework code common to different machines in plat-spear. > And here we need to use misc_regs.h, for this reason i kept it in > mach/include/mach. Okay so the plat-spear code use <mach/misc_regs.h> that is different between different machines? Then it's correct of course, sorry for going astray, please keep it there then. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 02/11] ST SPEAr: Added basic header files for SPEAr3xx machine family 2010-03-03 5:07 ` [PATCH 02/11] ST SPEAr: Added basic header files for SPEAr3xx machine family Viresh KUMAR 2010-03-03 5:07 ` [PATCH 03/11] ST SPEAr: Added basic header files for SPEAr6xx " Viresh KUMAR 2010-03-09 20:42 ` [PATCH 02/11] ST SPEAr: Added basic header files for SPEAr3xx machine family Linus Walleij @ 2010-03-11 10:33 ` Russell King - ARM Linux 2010-03-12 4:39 ` Viresh KUMAR 2 siblings, 1 reply; 51+ messages in thread From: Russell King - ARM Linux @ 2010-03-11 10:33 UTC (permalink / raw) To: linux-arm-kernel On Wed, Mar 03, 2010 at 10:37:32AM +0530, Viresh KUMAR wrote: > diff --git a/arch/arm/mach-spear3xx/include/mach/dma.h b/arch/arm/mach-spear3xx/include/mach/dma.h > new file mode 100644 > index 0000000..9b93bc6 > --- /dev/null > +++ b/arch/arm/mach-spear3xx/include/mach/dma.h > @@ -0,0 +1,18 @@ > +/* > + * arch/arm/mach-spear3xx/include/mach/dma.h > + * > + * Generic DMA support for SPEAr3xx machine family > + * > + * Copyright (C) 2009 ST Microelectronics > + * Viresh Kumar<viresh.kumar@st.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#ifndef __ASM_ARCH_DMA_H > +#define __ASM_ARCH_DMA_H > + > +#endif /* __ASM_ARCH_DMA_H */ > + You don't need to provide this file if you don't use it. > diff --git a/arch/arm/mach-spear3xx/include/mach/vmalloc.h b/arch/arm/mach-spear3xx/include/mach/vmalloc.h > new file mode 100644 > index 0000000..4f236f3 > --- /dev/null > +++ b/arch/arm/mach-spear3xx/include/mach/vmalloc.h > @@ -0,0 +1,22 @@ > +/* > + * arch/arm/mach-spear3xx/include/mach/vmalloc.h > + * > + * Defining Vmalloc area for SPEAr3xx machine family > + * > + * Copyright (C) 2009 ST Microelectronics > + * Viresh Kumar<viresh.kumar@st.com> > + * > + * This file is licensed under the terms of the GNU General Public > + * License version 2. This program is licensed "as is" without any > + * warranty of any kind, whether express or implied. > + */ > + > +#ifndef __ASM_MACH_VMALLOC_H > +#define __ASM_MACH_VMALLOC_H > + > +#include <mach/memory.h> > + > +#define VMALLOC_SIZE (0x30000000) > +#define VMALLOC_END (PAGE_OFFSET + VMALLOC_SIZE) Don't define it like this - define VMALLOC_END to be the maximum virtual address which you can permit the vmalloc area to extend to - which is generally the start of your peripheral mappings. It's rather pointless defining it in terms of PAGE_OFFSET, because this can vary, whereas the start of your peripheral mappings tends to be fixed. ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 02/11] ST SPEAr: Added basic header files for SPEAr3xx machine family 2010-03-11 10:33 ` Russell King - ARM Linux @ 2010-03-12 4:39 ` Viresh KUMAR 0 siblings, 0 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-12 4:39 UTC (permalink / raw) To: linux-arm-kernel On 3/11/2010 4:03 PM, Russell King - ARM Linux wrote: > On Wed, Mar 03, 2010 at 10:37:32AM +0530, Viresh KUMAR wrote: >> diff --git a/arch/arm/mach-spear3xx/include/mach/dma.h b/arch/arm/mach-spear3xx/include/mach/dma.h >> new file mode 100644 >> index 0000000..9b93bc6 >> --- /dev/null >> +++ b/arch/arm/mach-spear3xx/include/mach/dma.h >> @@ -0,0 +1,18 @@ >> +/* >> + * arch/arm/mach-spear3xx/include/mach/dma.h >> + * >> + * Generic DMA support for SPEAr3xx machine family >> + * >> + * Copyright (C) 2009 ST Microelectronics >> + * Viresh Kumar<viresh.kumar@st.com> >> + * >> + * This file is licensed under the terms of the GNU General Public >> + * License version 2. This program is licensed "as is" without any >> + * warranty of any kind, whether express or implied. >> + */ >> + >> +#ifndef __ASM_ARCH_DMA_H >> +#define __ASM_ARCH_DMA_H >> + >> +#endif /* __ASM_ARCH_DMA_H */ >> + > > You don't need to provide this file if you don't use it. > It will be removed. >> diff --git a/arch/arm/mach-spear3xx/include/mach/vmalloc.h b/arch/arm/mach-spear3xx/include/mach/vmalloc.h >> new file mode 100644 >> index 0000000..4f236f3 >> --- /dev/null >> +++ b/arch/arm/mach-spear3xx/include/mach/vmalloc.h >> @@ -0,0 +1,22 @@ >> +/* >> + * arch/arm/mach-spear3xx/include/mach/vmalloc.h >> + * >> + * Defining Vmalloc area for SPEAr3xx machine family >> + * >> + * Copyright (C) 2009 ST Microelectronics >> + * Viresh Kumar<viresh.kumar@st.com> >> + * >> + * This file is licensed under the terms of the GNU General Public >> + * License version 2. This program is licensed "as is" without any >> + * warranty of any kind, whether express or implied. >> + */ >> + >> +#ifndef __ASM_MACH_VMALLOC_H >> +#define __ASM_MACH_VMALLOC_H >> + >> +#include <mach/memory.h> >> + >> +#define VMALLOC_SIZE (0x30000000) >> +#define VMALLOC_END (PAGE_OFFSET + VMALLOC_SIZE) > > Don't define it like this - define VMALLOC_END to be the maximum virtual > address which you can permit the vmalloc area to extend to - which is > generally the start of your peripheral mappings. > > It's rather pointless defining it in terms of PAGE_OFFSET, because this > can vary, whereas the start of your peripheral mappings tends to be > fixed. > OK. Will be changed. regards, viresh kumar ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 01/11] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file 2010-03-03 5:07 ` [PATCH 01/11] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file Viresh KUMAR 2010-03-03 5:07 ` [PATCH 02/11] ST SPEAr: Added basic header files for SPEAr3xx machine family Viresh KUMAR @ 2010-03-09 20:14 ` Linus Walleij 2010-03-10 5:09 ` Viresh KUMAR 2010-03-11 10:45 ` Russell King - ARM Linux 1 sibling, 2 replies; 51+ messages in thread From: Linus Walleij @ 2010-03-09 20:14 UTC (permalink / raw) To: linux-arm-kernel 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: > Signed-off-by: Viresh Kumar <viresh.kumar@st.com> > --- > ?include/linux/sysctl_sp810.h | ? 59 ++++++++++++++++++++++++++++++++++++++++++ > ?1 files changed, 59 insertions(+), 0 deletions(-) > ?create mode 100644 include/linux/sysctl_sp810.h > (...) To the rest of the world this is probably a number of register definitions and an obscure inline function, so the entire internal kernel API does not need to know about it. Move it to arch/arm/include/asm/hardware Yours, Linus Walleij ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 01/11] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file 2010-03-09 20:14 ` [PATCH 01/11] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file Linus Walleij @ 2010-03-10 5:09 ` Viresh KUMAR 2010-03-11 10:45 ` Russell King - ARM Linux 1 sibling, 0 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-10 5:09 UTC (permalink / raw) To: linux-arm-kernel Linus, On 3/10/2010 1:44 AM, Linus Walleij wrote: > 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: > >> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> >> --- >> include/linux/sysctl_sp810.h | 59 ++++++++++++++++++++++++++++++++++++++++++ >> 1 files changed, 59 insertions(+), 0 deletions(-) >> create mode 100644 include/linux/sysctl_sp810.h >> (...) > > To the rest of the world this is probably a number of register definitions and > an obscure inline function, so the entire internal kernel API does not need > to know about it. > > Move it to arch/arm/include/asm/hardware OK. viresh ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 01/11] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file 2010-03-09 20:14 ` [PATCH 01/11] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file Linus Walleij 2010-03-10 5:09 ` Viresh KUMAR @ 2010-03-11 10:45 ` Russell King - ARM Linux 2010-03-12 5:19 ` Viresh KUMAR 1 sibling, 1 reply; 51+ messages in thread From: Russell King - ARM Linux @ 2010-03-11 10:45 UTC (permalink / raw) To: linux-arm-kernel On Tue, Mar 09, 2010 at 09:14:53PM +0100, Linus Walleij wrote: > 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: > > > Signed-off-by: Viresh Kumar <viresh.kumar@st.com> > > --- > > ?include/linux/sysctl_sp810.h | ? 59 ++++++++++++++++++++++++++++++++++++++++++ > > ?1 files changed, 59 insertions(+), 0 deletions(-) > > ?create mode 100644 include/linux/sysctl_sp810.h > > (...) > > To the rest of the world this is probably a number of register definitions and > an obscure inline function, so the entire internal kernel API does not need > to know about it. It'll also give people heart-attacks because they'll think it adds a new set of deprecated binary sysctl() interfaces to the kernel. Best drop the 'sysctl' part of the name as well. ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 01/11] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file 2010-03-11 10:45 ` Russell King - ARM Linux @ 2010-03-12 5:19 ` Viresh KUMAR 0 siblings, 0 replies; 51+ messages in thread From: Viresh KUMAR @ 2010-03-12 5:19 UTC (permalink / raw) To: linux-arm-kernel On 3/11/2010 4:15 PM, Russell King - ARM Linux wrote: > On Tue, Mar 09, 2010 at 09:14:53PM +0100, Linus Walleij wrote: >> 2010/3/3 Viresh KUMAR <viresh.kumar@st.com>: >> >>> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> >>> --- >>> include/linux/sysctl_sp810.h | 59 ++++++++++++++++++++++++++++++++++++++++++ >>> 1 files changed, 59 insertions(+), 0 deletions(-) >>> create mode 100644 include/linux/sysctl_sp810.h >>> (...) >> >> To the rest of the world this is probably a number of register definitions and >> an obscure inline function, so the entire internal kernel API does not need >> to know about it. > > It'll also give people heart-attacks because they'll think it adds a new > set of deprecated binary sysctl() interfaces to the kernel. > > Best drop the 'sysctl' part of the name as well. > OK. will be removed. ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 00/11] Adding Support for SPEAr Platform under ARM architecture 2010-03-03 5:07 [PATCH 00/11] Adding Support for SPEAr Platform under ARM architecture Viresh KUMAR 2010-03-03 5:07 ` [PATCH 01/11] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file Viresh KUMAR @ 2010-03-07 15:54 ` viresh kumar 2010-03-08 13:48 ` Armando VISCONTI 1 sibling, 1 reply; 51+ messages in thread From: viresh kumar @ 2010-03-07 15:54 UTC (permalink / raw) To: linux-arm-kernel Hello Russell, On Wed, Mar 3, 2010 at 10:37 AM, Viresh KUMAR <viresh.kumar@st.com> wrote: > Following set of patches are for adding ST Microelctronics SPEAr Platform under > ARM architecture in Linux. > > Hierarchy in SPEAr is as follows: > SPEAr (Platform) > ? ? ? ?- SPEAr3XX (3XX SOC series, based on ARM9) > ? ? ? ? ? ? ? ?- SPEAr300 (SOC) > ? ? ? ? ? ? ? ? ? ? ? ?- SPEAr300_EVB (Evaluation Board) > ? ? ? ? ? ? ? ?- SPEAr310 (SOC) > ? ? ? ? ? ? ? ? ? ? ? ?- SPEAr310_EVB (Evaluation Board) > ? ? ? ? ? ? ? ?- SPEAr320 (SOC) > ? ? ? ? ? ? ? ? ? ? ? ?- SPEAr320_EVB (Evaluation Board) > ? ? ? ?- SPEAr6XX (6XX SOC series, based on ARM9) > ? ? ? ? ? ? ? ?- SPEAr600 (SOC) > ? ? ? ? ? ? ? ? ? ? ? ?- SPEAr600_EVB (Evaluation Board) > ? ? ? ?- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9) > ? ? ? ? ? ? ? ?- SPEAr1300 (SOC) > > Current patch will add support for SPEAr3XX and SPEAr6XX family. SPEAr13XX is > under development phase. > Is this patch set fine? Or do i need resubmit it? regards, viresh kumar, ST Microelectronics ^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH 00/11] Adding Support for SPEAr Platform under ARM architecture 2010-03-07 15:54 ` [PATCH 00/11] Adding Support for SPEAr Platform under ARM architecture viresh kumar @ 2010-03-08 13:48 ` Armando VISCONTI 0 siblings, 0 replies; 51+ messages in thread From: Armando VISCONTI @ 2010-03-08 13:48 UTC (permalink / raw) To: linux-arm-kernel Dear Russell, We really would like to contribute back to the linux community with the SPEAr architecture, as we already did for the u-boot loader. We started just adding the minimum required to boot up the system, but we will definetely add all the remaining peripheral in the next merging windows. Can you possibly just spend some times on this patch set and give us your feedback? We would really appreciate. :-) Thx very much, Armando viresh kumar wrote: > Hello Russell, > > On Wed, Mar 3, 2010 at 10:37 AM, Viresh KUMAR <viresh.kumar@st.com> wrote: > >> Following set of patches are for adding ST Microelctronics SPEAr Platform under >> ARM architecture in Linux. >> >> Hierarchy in SPEAr is as follows: >> SPEAr (Platform) >> - SPEAr3XX (3XX SOC series, based on ARM9) >> - SPEAr300 (SOC) >> - SPEAr300_EVB (Evaluation Board) >> - SPEAr310 (SOC) >> - SPEAr310_EVB (Evaluation Board) >> - SPEAr320 (SOC) >> - SPEAr320_EVB (Evaluation Board) >> - SPEAr6XX (6XX SOC series, based on ARM9) >> - SPEAr600 (SOC) >> - SPEAr600_EVB (Evaluation Board) >> - SPEAr13XX (13XX SOC series, based on ARM CORTEXA9) >> - SPEAr1300 (SOC) >> >> Current patch will add support for SPEAr3XX and SPEAr6XX family. SPEAr13XX is >> under development phase. >> >> > > Is this patch set fine? Or do i need resubmit it? > > > regards, > viresh kumar, > ST Microelectronics > ^ permalink raw reply [flat|nested] 51+ messages in thread
end of thread, other threads:[~2010-03-12 8:46 UTC | newest] Thread overview: 51+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2010-03-03 5:07 [PATCH 00/11] Adding Support for SPEAr Platform under ARM architecture Viresh KUMAR 2010-03-03 5:07 ` [PATCH 01/11] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file Viresh KUMAR 2010-03-03 5:07 ` [PATCH 02/11] ST SPEAr: Added basic header files for SPEAr3xx machine family Viresh KUMAR 2010-03-03 5:07 ` [PATCH 03/11] ST SPEAr: Added basic header files for SPEAr6xx " Viresh KUMAR 2010-03-03 5:07 ` [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform Viresh KUMAR 2010-03-03 5:07 ` [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines Viresh KUMAR 2010-03-03 5:07 ` [PATCH 06/11] ST SPEAr: Added source files for SPEAr platform Viresh KUMAR 2010-03-03 5:07 ` [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family Viresh KUMAR 2010-03-03 5:07 ` [PATCH 08/11] ST SPEAr: Added source files for SPEAr6xx " Viresh KUMAR 2010-03-03 5:07 ` [PATCH 09/11] ST SPEAr: Added support for SPEAr platform and machines in arch/arm/ Viresh KUMAR 2010-03-03 5:07 ` [PATCH 10/11] ST SPEAr: Added default configuration files for SPEAr machines Viresh KUMAR 2010-03-03 5:07 ` [PATCH 11/11] ST SPEAr: Updated Maintainers and added Documentation/arm/SPEAr Viresh KUMAR 2010-03-11 20:18 ` [PATCH 10/11] ST SPEAr: Added default configuration files for SPEAr machines Linus Walleij 2010-03-11 20:26 ` Russell King - ARM Linux 2010-03-12 4:12 ` Viresh KUMAR 2010-03-09 6:46 ` [PATCH 07/11] ST SPEAr: Added source files for SPEAr3xx machine family Linus Walleij 2010-03-09 7:05 ` Viresh KUMAR 2010-03-10 5:15 ` Linus Walleij 2010-03-10 6:10 ` viresh kumar 2010-03-11 10:41 ` Russell King - ARM Linux 2010-03-12 5:19 ` Viresh KUMAR 2010-03-11 11:22 ` [PATCH 06/11] ST SPEAr: Added source files for SPEAr platform Linus Walleij 2010-03-11 7:00 ` [PATCH 05/11] ST SPEAr: Added clock framework for SPEAr platform and machines Linus Walleij 2010-03-11 10:18 ` Shiraz HASHIM 2010-03-12 8:46 ` Linus Walleij 2010-03-12 4:19 ` Viresh KUMAR 2010-03-11 10:28 ` Russell King - ARM Linux 2010-03-12 4:22 ` Viresh KUMAR 2010-03-10 5:40 ` [PATCH 04/11] ST SPEAr: Added basic header files for SPEAr platform Linus Walleij 2010-03-10 6:32 ` Viresh KUMAR 2010-03-10 9:31 ` Linus Walleij 2010-03-10 10:11 ` Viresh KUMAR 2010-03-10 14:16 ` Paul Mundt 2010-03-10 16:36 ` Thomas Gleixner 2010-03-10 22:16 ` Tony Lindgren 2010-03-10 23:29 ` Paul Mundt 2010-03-10 23:42 ` Thomas Gleixner 2010-03-11 6:43 ` Linus Walleij 2010-03-11 9:47 ` Shiraz HASHIM 2010-03-11 11:26 ` Linus Walleij 2010-03-09 20:42 ` [PATCH 02/11] ST SPEAr: Added basic header files for SPEAr3xx machine family Linus Walleij 2010-03-10 6:01 ` Viresh KUMAR 2010-03-10 6:07 ` Linus Walleij 2010-03-11 10:33 ` Russell King - ARM Linux 2010-03-12 4:39 ` Viresh KUMAR 2010-03-09 20:14 ` [PATCH 01/11] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file Linus Walleij 2010-03-10 5:09 ` Viresh KUMAR 2010-03-11 10:45 ` Russell King - ARM Linux 2010-03-12 5:19 ` Viresh KUMAR 2010-03-07 15:54 ` [PATCH 00/11] Adding Support for SPEAr Platform under ARM architecture viresh kumar 2010-03-08 13:48 ` Armando VISCONTI
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