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mail2.ecloud.global; auth=pass smtp.mailfrom=maud_spierings@murena.io Message-ID: <6462d084-5861-4df6-94ca-dbd23e619a61@murena.io> Date: Thu, 1 Oct 2026 17:40:06 +0200 MIME-Version: 1.0 Subject: Re: [PATCH v5 01/21] drm/bridge: inno-hdmi: fix swapped HSYNC and VSYNC polarity To: Michal Wilczynski , Vinod Koul , Manivannan Sadhasivam , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Andy Yan , Philipp Zabel , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Dominique Belhachemi , Brian Masney , Jerome Brunet Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, Marek Szyprowski , Graham Markall , Icenowy Zheng , Chaoyi Chen , Joshua Peisach , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , Byron Stanoszek References: <20260929-jh7110-clean-send-v5-0-82b4d8e3c6c7@samsung.com> <20260929-jh7110-clean-send-v5-1-82b4d8e3c6c7@samsung.com> Content-Language: en-US From: Maud Spierings In-Reply-To: <20260929-jh7110-clean-send-v5-1-82b4d8e3c6c7@samsung.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261001_084013_707616_C12B7D3D X-CRM114-Status: GOOD ( 14.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Michal, Fixed! Thanks! Tested-by: Maud Spierings Kind regards, Maud On 9/29/26 12:30, Michal Wilczynski wrote: > v_HSYNC_POLARITY() and v_VSYNC_POLARITY() write the wrong bits: the > hardware puts HSYNC in bit 2 and VSYNC in bit 3, the macros do the > opposite. Most CEA modes drive both syncs with the same polarity so it > goes unnoticed; it only shows up on modes where the two differ. > > Fixes: 412d4ae6b7a5 ("drm/rockchip: hdmi: add Innosilicon HDMI support") > Reported-by: Maud Spierings > Closes: https://lore.kernel.org/all/e780ecb8-918f-4816-99c8-b69b10b25a18@murena.io/ > Reported-by: Byron Stanoszek > Closes: https://lore.kernel.org/all/b8b046ee-c574-3e16-6079-2fc415633dae@winds.org/ > Suggested-by: Dominique Belhachemi > Signed-off-by: Michal Wilczynski > --- > drivers/gpu/drm/bridge/inno-hdmi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/inno-hdmi.c b/drivers/gpu/drm/bridge/inno-hdmi.c > index dd35f5a875d3d842fee6d2ead0de88503f9914e1..d7c33b92e2ddf4ced84d17304463f44be52270b8 100644 > --- a/drivers/gpu/drm/bridge/inno-hdmi.c > +++ b/drivers/gpu/drm/bridge/inno-hdmi.c > @@ -122,8 +122,8 @@ enum { > #define v_VIDEO_MUTE(n) ((n) << 0) > > #define HDMI_VIDEO_TIMING_CTL 0x08 > -#define v_HSYNC_POLARITY(n) ((n) << 3) > -#define v_VSYNC_POLARITY(n) ((n) << 2) > +#define v_VSYNC_POLARITY(n) ((n) << 3) > +#define v_HSYNC_POLARITY(n) ((n) << 2) > #define v_INETLACE(n) ((n) << 1) > #define v_EXTERANL_VIDEO(n) ((n) << 0) > >