From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA951C0015E for ; Tue, 1 Aug 2023 16:56:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HLpqdcM5Z2+qGTTzYUvMm9p6g7+2xmHY0fZEHRZ3RVs=; b=KZsTQB/NUdgJXy vxTEnfToxwquNrwESJYnmeD6KtgIJRXM1ko+0HQTUKPUZJq8lJl+jnu4UhMYMyfFOTpboWdgQocaF aIuhmVD7F8c4W5icAlk4Sx7qIEJRauFLYDJrBP1yJg9R2W8cV4EAGt3bu1MklmHbxXhpgi8hbs5f+ W5iFGHgz1SNeuPP5IQYnMhoSZfWfs1/EKKgG/A4Ls9uc7CSrXZZ1jX5PNlwOUFM9kWYfTbhp4LzQV 5vhi3fPGf2nJXoYFv13OD0Q9BS87Gf53iPiOgTC6lRLCb4+UIZQ8W20LVzByQLoQ9I48IaFBBInht sgPQ21xuxcEZ1vtMWkNA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qQsfW-002rKX-02; Tue, 01 Aug 2023 16:56:22 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qQsfT-002rJp-0A for linux-arm-kernel@lists.infradead.org; Tue, 01 Aug 2023 16:56:20 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6946A61633; Tue, 1 Aug 2023 16:56:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7DEE0C433C7; Tue, 1 Aug 2023 16:56:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1690908977; bh=bRSvjQunUP9yovqAQ96bucssEOT5sj5mD8xWzV3Px4Q=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=HmtgyFmrFiQBDoe/wT1NEWRCT2cRd7s/N7x7MFxMaNOwRts1yi5Dt1jlCw0ZtIKYt 1iAPgviM85CXM05FLS+4jAeH3vy/pmTehsfD+ffIXoG5EYrWmpic3annYv6hnM6Vw6 rZZd4bl4zlBcUGjgGx20QRHiEONyJs3j7ruY/TtkalEvjiDYl74ODukQd9onsUI3/K GLsSULAvewtUGYzOhjBPaYnAaGn8FQAc+okVXYmHCrtGrlLXZB6kTP+pBfEgC41RoS RPiUDXTVafRmxqRxuO5MxDMHYK+CBpo3Z7VhyNTU/Vrpdrx/zmFhMWA6xl8v+4Pnum izFL+YMCCq9yg== Message-ID: <64ae76ef-a85a-7cc7-6bc3-a8ea46621d73@kernel.org> Date: Tue, 1 Aug 2023 19:56:12 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH v8 2/5] arm64: dts: ti: k3-j784s4-main: Add WIZ and SERDES PHY nodes Content-Language: en-US To: Jayesh Choudhary , nm@ti.com, vigneshr@ti.com Cc: s-vadapalli@ti.com, afd@ti.com, kristo@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, a-bhatia1@ti.com, r-ravikumar@ti.com, sabiya.d@ti.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20230801070019.219660-1-j-choudhary@ti.com> <20230801070019.219660-3-j-choudhary@ti.com> From: Roger Quadros In-Reply-To: <20230801070019.219660-3-j-choudhary@ti.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230801_095619_173193_B8CD75CB X-CRM114-Status: GOOD ( 17.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 01/08/2023 10:00, Jayesh Choudhary wrote: > From: Siddharth Vadapalli > > J784S4 SoC has 4 Serdes instances along with their respective WIZ > instances. Add device-tree nodes for them and disable them by default. > > Signed-off-by: Siddharth Vadapalli > [j-choudhary@ti.com: fix serdes_wiz clock order & disable serdes refclk] > Signed-off-by: Jayesh Choudhary > --- > arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 172 +++++++++++++++++++++ > 1 file changed, 172 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > index 8a816563706b..fbf5ab94d785 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > @@ -6,9 +6,19 @@ > */ > > #include > +#include > +#include > > #include "k3-serdes.h" > > +/ { > + serdes_refclk: serdes-refclk { standard name should begin with clock > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + status = "disabled"; > + }; > +}; > + > &cbass_main { > msmc_ram: sram@70000000 { > compatible = "mmio-sram"; > @@ -709,6 +719,168 @@ main_sdhci1: mmc@4fb0000 { > status = "disabled"; > }; > > + serdes_wiz0: wiz@5060000 { > + compatible = "ti,j784s4-wiz-10g"; > + #address-cells = <1>; > + #size-cells = <1>; > + power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>; > + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; > + assigned-clocks = <&k3_clks 404 6>; > + assigned-clock-parents = <&k3_clks 404 10>; > + num-lanes = <4>; > + #reset-cells = <1>; > + #clock-cells = <1>; > + ranges = <0x5060000 0x00 0x5060000 0x10000>; > +> + status = "disabled"; > + drop blank lines here and rest of this file where you set status to "disabled". > + serdes0: serdes@5060000 { phy@5060000 > + compatible = "ti,j721e-serdes-10g"; > + reg = <0x05060000 0x010000>; > + reg-names = "torrent_phy"; > + resets = <&serdes_wiz0 0>; > + reset-names = "torrent_reset"; > + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, > + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; > + clock-names = "refclk", "phy_en_refclk"; > + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, > + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, > + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; > + assigned-clock-parents = <&k3_clks 404 6>, > + <&k3_clks 404 6>, > + <&k3_clks 404 6>; > + #address-cells = <1>; > + #size-cells = <0>; > + #clock-cells = <1>; > + > + status = "disabled"; > + }; > + }; > + > + serdes_wiz1: wiz@5070000 { > + compatible = "ti,j784s4-wiz-10g"; > + #address-cells = <1>; > + #size-cells = <1>; > + power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>; > + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; > + assigned-clocks = <&k3_clks 405 6>; > + assigned-clock-parents = <&k3_clks 405 10>; > + num-lanes = <4>; > + #reset-cells = <1>; > + #clock-cells = <1>; > + ranges = <0x05070000 0x00 0x05070000 0x10000>; > + > + status = "disabled"; > + > + serdes1: serdes@5070000 { phy@5070000 > + compatible = "ti,j721e-serdes-10g"; > + reg = <0x05070000 0x010000>; > + reg-names = "torrent_phy"; > + resets = <&serdes_wiz1 0>; > + reset-names = "torrent_reset"; > + clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, > + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; > + clock-names = "refclk", "phy_en_refclk"; > + assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, > + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, > + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; > + assigned-clock-parents = <&k3_clks 405 6>, > + <&k3_clks 405 6>, > + <&k3_clks 405 6>; > + #address-cells = <1>; > + #size-cells = <0>; > + #clock-cells = <1>; > + > + status = "disabled"; > + }; > + }; > + > + serdes_wiz2: wiz@5020000 { > + compatible = "ti,j784s4-wiz-10g"; > + #address-cells = <1>; > + #size-cells = <1>; > + power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>; > + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; > + assigned-clocks = <&k3_clks 406 6>; > + assigned-clock-parents = <&k3_clks 406 10>; > + num-lanes = <4>; > + #reset-cells = <1>; > + #clock-cells = <1>; > + ranges = <0x05020000 0x00 0x05020000 0x10000>; > + > + status = "disabled"; > + > + serdes2: serdes@5020000 { phy@5020000 > + compatible = "ti,j721e-serdes-10g"; > + reg = <0x05020000 0x010000>; > + reg-names = "torrent_phy"; > + resets = <&serdes_wiz2 0>; > + reset-names = "torrent_reset"; > + clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, > + <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>; > + clock-names = "refclk", "phy_en_refclk"; > + assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>, > + <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>, > + <&serdes_wiz2 TI_WIZ_REFCLK_DIG>; > + assigned-clock-parents = <&k3_clks 406 6>, > + <&k3_clks 406 6>, > + <&k3_clks 406 6>; > + #address-cells = <1>; > + #size-cells = <0>; > + #clock-cells = <1>; > + > + status = "disabled"; > + }; > + }; > + > + serdes_wiz4: wiz@5050000 { > + compatible = "ti,j784s4-wiz-10g"; > + #address-cells = <1>; > + #size-cells = <1>; > + power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>; > + clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; > + assigned-clocks = <&k3_clks 407 6>; > + assigned-clock-parents = <&k3_clks 407 10>; > + num-lanes = <4>; > + #reset-cells = <1>; > + #clock-cells = <1>; > + ranges = <0x05050000 0x00 0x05050000 0x10000>, > + <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */ > + > + status = "disabled"; > + > + serdes4: serdes@5050000 { phy@5050000 > + /* > + * Note: we also map DPTX PHY registers as the Torrent > + * needs to manage those. > + */ > + compatible = "ti,j721e-serdes-10g"; > + reg = <0x05050000 0x010000>, > + <0x0a030a00 0x40>; /* DPTX PHY */ > + reg-names = "torrent_phy"; > + resets = <&serdes_wiz4 0>; > + reset-names = "torrent_reset"; > + clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, > + <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>; > + clock-names = "refclk", "phy_en_refclk"; > + assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, > + <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, > + <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; > + assigned-clock-parents = <&k3_clks 407 6>, > + <&k3_clks 407 6>, > + <&k3_clks 407 6>; > + #address-cells = <1>; > + #size-cells = <0>; > + #clock-cells = <1>; > + > + status = "disabled"; > + }; > + }; > + > main_navss: bus@30000000 { > compatible = "simple-bus"; > #address-cells = <2>; -- cheers, -roger _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel