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Fri, 10 Jul 2026 03:17:16 -0500 Received: from [10.136.35.241] (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Fri, 10 Jul 2026 03:17:11 -0500 Message-ID: <650c7050-2a77-4415-b597-3bb39ccfb1e8@amd.com> Date: Fri, 10 Jul 2026 13:47:10 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 5/8] riscv/runtime-const: Introduce runtime_const_mask_32() To: Charlie Jenkins CC: Arnd Bergmann , Thomas Gleixner , Ingo Molnar , Peter Zijlstra , Sebastian Andrzej Siewior , Paul Walmsley , Palmer Dabbelt , Albert Ou , Darren Hart , Davidlohr Bueso , =?UTF-8?Q?Andr=C3=A9_Almeida?= , , , Samuel Holland , , , , Alexandre Ghiti , Jisheng Zhang References: <20260630045531.3939-1-kprateek.nayak@amd.com> <20260630045531.3939-6-kprateek.nayak@amd.com> <178366995930.1208691.2993932866462893112.b4-review@b4> Content-Language: en-US From: K Prateek Nayak In-Reply-To: <178366995930.1208691.2993932866462893112.b4-review@b4> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 60pdV8geNf2LGy6amrH9UHz4HB+liaHa8OSGHsqTNViw7oXQ249X9/AxDXEBPT7AnEg8ZdRXgUBHxlYACOmZQGYW87ZjV6+TxVG2cyOG9c6BLMYOjzC1nP5NQn4+PaREJZUZvfXdr4LeQyTIGNWLIB0s1nzxYg+tFD2DgvDdG/QwyaWMRLRdmp/g8tHkI78gp1Wv5qk45RzbrqP6uvgGImmtG7kRzs3ss/ovE+nC5lWeewQ3jD5vK//MvYhWHJDhi/Wjss3OJgLPR9ENljPxVLxOxqIqWT/pG2P07+arTG+p/07FfAyTOeuH4/eZ/Ze+VQtAWfXsRNAuX9b8wBnN+RpKYQs28YmfhsMpQsShvtAfykKsjTiQna8TYWCjVeYU6RJDQgpOZNJxgyf4yas6IuPaWqlJziwI9WM1hTrkuZGFRWs9pbuthM4acsYljNrq X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2026 08:17:16.9680 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 32fd8548-7dad-4237-4418-08dede5ba7b3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B371.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH8PR12MB9816 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260710_011725_267877_0C020C74 X-CRM114-Status: GOOD ( 31.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello Charlie, On 7/10/2026 1:22 PM, Charlie Jenkins wrote: > [You don't often get email from thecharlesjenkins@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] > > On Tue, 30 Jun 2026 04:55:28 +0000, K Prateek Nayak wrote: >> Futex hash computation requires a mask operation with read-only after >> init data that will be converted to a runtime constant in the subsequent >> commit. >> >> Introduce runtime_const_mask_32 to further optimize the mask operation >> in the futex hash computation hot path. Since all the current use-cases >> are of the form GENMASK(n, 0), with n > 0, following sequence: > > I really appreciate you spending the time to do this, thank you! My pleasure! And I really appreciate you taking time to review and test this series. Thanks a ton for that! > >> >> >> diff --git a/arch/riscv/include/asm/runtime-const.h b/arch/riscv/include/asm/runtime-const.h >> index 1ce02605d2e4..dbf96c937dbb 100644 >> --- a/arch/riscv/include/asm/runtime-const.h >> +++ b/arch/riscv/include/asm/runtime-const.h >> @@ -262,6 +279,33 @@ static inline void __runtime_fixup_shift(void *where, unsigned long val) >> [ ... skip 24 lines ... ] >> + BUG_ON(!val || width > 31 || (GENMASK(width - 1, 0) != val)); >> + >> + __runtime_fixup_shift(where, 32 - width); >> + __runtime_fixup_shift(where + 4, 32 - width); >> +} >> + > > It would be "optimal" to use an andi when the mask is <=11 bits since > andi can fit an 11 bit mask. What you have is good enough but I'll leave > my stab at doing the andi patching here in case you want to apply it. > > From 9e5527aaddd464783af795aacdb6d094e11cc31e Mon Sep 17 00:00:00 2001 > From: Charlie Jenkins > Date: Thu, 9 Jul 2026 23:18:09 -0700 > Subject: [PATCH] riscv: Optimize __runtime_fixup_mask for masks with <= 11 > bits Peter seems to have merged the v5 series in his tree but If you could give your S-o-b, I can throw in a commit log, some testing along with a few cosmetic modifications, and send it for official review on top of queue:locking/core ;-) > > --- > arch/riscv/include/asm/insn.h | 2 ++ > arch/riscv/include/asm/runtime-const.h | 29 ++++++++++++++++++++++++-- > 2 files changed, 29 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h > index c3005573e8c9..0a34cd7305d0 100644 > --- a/arch/riscv/include/asm/insn.h > +++ b/arch/riscv/include/asm/insn.h > @@ -141,6 +141,7 @@ > #define RVG_OPCODE_JALR 0x67 > #define RVG_OPCODE_JAL 0x6f > #define RVG_OPCODE_SYSTEM 0x73 > +#define RVG_OPCODE_ANDI 0x13 > #define RVG_SYSTEM_CSR_OFF 20 > #define RVG_SYSTEM_CSR_MASK GENMASK(12, 0) > > @@ -175,6 +176,7 @@ > #define RVG_FUNCT3_BGE 0x5 > #define RVG_FUNCT3_BLTU 0x6 > #define RVG_FUNCT3_BGEU 0x7 > +#define RVG_FUNCT3_ANDI 0x7 > > /* parts of funct3 code for C extension*/ > #define RVC_FUNCT3_C_BEQZ 0x6 > diff --git a/arch/riscv/include/asm/runtime-const.h b/arch/riscv/include/asm/runtime-const.h > index dbf96c937dbb..24a9b13081f7 100644 > --- a/arch/riscv/include/asm/runtime-const.h > +++ b/arch/riscv/include/asm/runtime-const.h > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -302,8 +303,32 @@ static inline void __runtime_fixup_mask(void *where, unsigned long val) > */ > BUG_ON(!val || width > 31 || (GENMASK(width - 1, 0) != val)); > > - __runtime_fixup_shift(where, 32 - width); > - __runtime_fixup_shift(where + 4, 32 - width); > + /* > + * A riscv 'andi' instruction can fit an 11 bit immediate, so the mask > + * can be directly applied. Otherwise fall back to SRLI + SLLI. > + */ > + if (width < 11) { > + __le16 *parcel = where; > + u32 insn; > + __le32 res, nop; > + > + insn = (u32)le16_to_cpu(parcel[0]) | (u32)le16_to_cpu(parcel[1]) << 16; > + > + /* Replace the slli/slliw with an andi */ > + insn &= 0x000fcf80; > + insn |= val << 20 | RV_ENCODE_FUNCT3(ANDI) | RVG_OPCODE_ANDI; > + > + res = cpu_to_le32(insn); > + /* Replace the srli/srliw with a nop */ > + nop = cpu_to_le32(RISCV_INSN_NOP4); > + mutex_lock(&text_mutex); > + patch_text_nosync(where, &res, sizeof(insn)); > + patch_text_nosync(where + 4, &nop, sizeof(insn)); > + mutex_unlock(&text_mutex); > + } else { > + __runtime_fixup_shift(where, 32 - width); > + __runtime_fixup_shift(where + 4, 32 - width); > + } > } > > static inline void runtime_const_fixup(void (*fn)(void *, unsigned long), > -- > 2.54.0 > > > I would prefer including this, but I am happy to approve this > regardless. Ack! I'll keep it as an optimization on top to retain your attribution. > > Reviewed-by: Charlie Jenkins > Tested-by: Charlie Jenkins Thank you again! -- Thanks and Regards, Prateek