From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B24B4C54E60 for ; Tue, 12 Mar 2024 11:33:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:References:Subject:CC:To: MIME-Version:From:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LvSvEf7yDm8+/HhzKhF+hzoVlOHs87lNIsBXjFHxnDc=; b=39F31QOVNuIC5r 9Du0bAX5n2mCIzNsi2wT0MT/uqCUC0EiQXfl94jt2ka1X8sh7Xn2vcj4SqDLEIW5MrkzX5WkJREyn nhcQk2bqwrbEQNJGetXA7WekABe6Yf/EcMVbQJJ8krR74h7ROMgBtru6ynPgGlfOz3S9+MyRygGbE /vvfkaOkqeH1bAD5b6GMuaMpP7zwsbfqpXqld0bMx9NqqcH9tk75ZhDWFwyx1nTxJV5iDR46fH5++ q9LtUCJCcdXG03225Kx3eRyt6vk/aSBJoaVyE9bcCQjwQs8+3eHiTIiQn2da4NLyc7ZNxoXcfQPyL +epFq+XEUAMCyiubKSCw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rk0Nu-00000005XhW-1wu4; Tue, 12 Mar 2024 11:33:30 +0000 Received: from szxga04-in.huawei.com ([45.249.212.190]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rk0Nq-00000005Xfs-3l6n for linux-arm-kernel@lists.infradead.org; Tue, 12 Mar 2024 11:33:29 +0000 Received: from mail.maildlp.com (unknown [172.19.88.214]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4TvBLC0yzQz1xqhD; Tue, 12 Mar 2024 19:31:31 +0800 (CST) Received: from kwepemd100008.china.huawei.com (unknown [7.221.188.193]) by mail.maildlp.com (Postfix) with ESMTPS id 5C5EF1A016C; Tue, 12 Mar 2024 19:33:15 +0800 (CST) Received: from [10.67.121.2] (10.67.121.2) by kwepemd100008.china.huawei.com (7.221.188.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 12 Mar 2024 19:33:14 +0800 Message-ID: <65F03D79.2070008@hisilicon.com> Date: Tue, 12 Mar 2024 19:33:13 +0800 From: Wei Xu User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 MIME-Version: 1.0 To: Yang Xiwen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Alex Elder , Peter Griffin CC: , , , Subject: Re: [PATCH v3 0/3] arm64: dts: hi3798cv200: fix GICR size, add cache info, maintenance irq and GICH, GICV spaces References: <20240219-cache-v3-0-a33c57534ae9@outlook.com> In-Reply-To: X-Originating-IP: [10.67.121.2] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemd100008.china.huawei.com (7.221.188.193) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240312_043327_413630_6FB295DC X-CRM114-Status: GOOD ( 13.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Yang, On 2024/3/12 19:19, Yang Xiwen wrote: > On 2/19/2024 11:05 PM, Yang Xiwen via B4 Relay wrote: >> The patchset fixes some warnings reported by the kernel during boot. >> >> The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section >> 2.2.1 Master Processor. >> >> The cache line size and the set-associative info are from Cortex-A53 >> Documentation [2]. >> >> From the doc, it can be concluded that L1 i-cache is 4-way assoc, L1 >> d-cache is 2-way assoc and L2 cache is 16-way assoc. Calculate the dts >> props accordingly. >> >> Also, to use KVM's VGIC code, GICH, GICV registers spaces and maintenance >> IRQ are added to the dts with verification. >> >> [1]: https://github.com/96boards/documentation/blob/master/enterprise/poplar/hardware-docs/Processor_Datasheet_v2XX.pdf >> [2]: https://developer.arm.com/documentation/ddi0500/j/Level-1-Memory-System >> >> Signed-off-by: Yang Xiwen >> --- >> Changes in v3: >> - send patches to stable (Andrew Lunn) >> - rewrite the commit logs more formally (Andrew Lunn) >> - rename l2-cache0 to l2-cache (Krzysztof Kozlowski) >> - Link to v2: https://lore.kernel.org/r/20240218-cache-v2-0-1fd919e2bd3e@outlook.com >> >> Changes in v2: >> - arm64: dts: hi3798cv200: add GICH, GICV register spces and >> maintainance IRQ. >> - Link to v1: https://lore.kernel.org/r/20240218-cache-v1-0-2c0a8a4472e7@outlook.com >> >> --- >> Yang Xiwen (3): >> arm64: dts: hi3798cv200: fix the size of GICR >> arm64: dts: hi3798cv200: add GICH, GICV register space and irq >> arm64: dts: hi3798cv200: add cache info >> >> arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 43 +++++++++++++++++++++++++- >> 1 file changed, 42 insertions(+), 1 deletion(-) >> --- >> base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d >> change-id: 20240218-cache-11c8bf7566c2 >> >> Best regards, > > May someone apply this patchset to their tree so that it can land in stable at the end? This is a fix, not adding new functionalities. It's been 2 weeks already. > Sorry for the delay, I am too busy to catch up with this cycle. I will go through this patch set and maybe apply it during the next cycle. Best Regards, Wei _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel