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Wed, 11 Oct 2023 23:22:37 -0700 (PDT) Received: from [192.168.1.20] ([178.197.219.100]) by smtp.gmail.com with ESMTPSA id o6-20020a17090611c600b009ad875d12d7sm10581433eja.210.2023.10.11.23.22.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Oct 2023 23:22:37 -0700 (PDT) Message-ID: <65bc7dcc-02a1-4e7b-9ea3-6f421c4b1be3@linaro.org> Date: Thu, 12 Oct 2023 08:22:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 15/20] watchdog: s3c2410_wdt: Add support for Google tensor SoCs Content-Language: en-US To: Peter Griffin , robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, gregkh@linuxfoundation.org, cw00.choi@samsung.com Cc: tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, willmcvicker@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org References: <20231011184823.443959-1-peter.griffin@linaro.org> <20231011184823.443959-16-peter.griffin@linaro.org> From: Krzysztof Kozlowski Autocrypt: addr=krzysztof.kozlowski@linaro.org; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 11/10/2023 20:48, Peter Griffin wrote: > This patch adds the compatibles and drvdata for the Google > gs101 & gs201 SoCs found in Pixel 6 and Pixel 7 phones. Similar > to Exynos850 it has two watchdog instances, one for each cluster > and has some control bits in PMU registers. > > The watchdog IP found in gs101 SoCs also supports a few > additional bits/features in the WTCON register which we add > support for and an additional register detailed below. > > dbgack-mask - Enables masking WDT interrupt and reset request > according to asserted DBGACK input > > windowed-mode - Enabled Windowed watchdog mode > > Windowed watchdog mode also has an additional register WTMINCNT. > If windowed watchdog is enabled and you reload WTCNT when the > value is greater than WTMINCNT, it prompts interrupt or reset > request as if the watchdog time has expired. > > Signed-off-by: Peter Griffin > --- > drivers/watchdog/s3c2410_wdt.c | 127 ++++++++++++++++++++++++++++++--- > 1 file changed, 116 insertions(+), 11 deletions(-) > > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c > index 0b4bd883ff28..36c170047180 100644 > --- a/drivers/watchdog/s3c2410_wdt.c > +++ b/drivers/watchdog/s3c2410_wdt.c > @@ -31,12 +31,14 @@ > #define S3C2410_WTDAT 0x04 > #define S3C2410_WTCNT 0x08 > #define S3C2410_WTCLRINT 0x0c > - > +#define S3C2410_WTMINCNT 0x10 > #define S3C2410_WTCNT_MAXCNT 0xffff > > -#define S3C2410_WTCON_RSTEN (1 << 0) > -#define S3C2410_WTCON_INTEN (1 << 2) > -#define S3C2410_WTCON_ENABLE (1 << 5) > +#define S3C2410_WTCON_RSTEN (1 << 0) > +#define S3C2410_WTCON_INTEN (1 << 2) > +#define S3C2410_WTCON_ENABLE (1 << 5) > +#define S3C2410_WTCON_DBGACK_MASK (1 << 16) > +#define S3C2410_WTCON_WINDOWED_WD (1 << 20) > > #define S3C2410_WTCON_DIV16 (0 << 3) > #define S3C2410_WTCON_DIV32 (1 << 3) > @@ -51,6 +53,7 @@ > > #define S3C2410_WATCHDOG_ATBOOT (0) > #define S3C2410_WATCHDOG_DEFAULT_TIME (15) > +#define S3C2410_WINDOW_MULTIPLIER 2 > > #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404 > #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408 > @@ -67,6 +70,13 @@ > #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25 > #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24 > > +#define GS_CLUSTER0_NONCPU_OUT 0x1220 > +#define GS_CLUSTER1_NONCPU_OUT 0x1420 > +#define GS_CLUSTER0_NONCPU_INT_EN 0x1244 > +#define GS_CLUSTER1_NONCPU_INT_EN 0x1444 > +#define GS_CLUSTER2_NONCPU_INT_EN 0x1644 > +#define GS_RST_STAT_REG_OFFSET 0x3B44 > + > /** > * DOC: Quirk flags for different Samsung watchdog IP-cores > * > @@ -106,6 +116,8 @@ > #define QUIRK_HAS_PMU_RST_STAT (1 << 2) > #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) > #define QUIRK_HAS_PMU_CNT_EN (1 << 4) > +#define QUIRK_HAS_DBGACK_BIT (1 << 5) > +#define QUIRK_HAS_WTMINCNT_REG (1 << 6) > > /* These quirks require that we have a PMU register map */ > #define QUIRKS_HAVE_PMUREG \ > @@ -263,6 +275,54 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = { > QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, > }; > > +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = { > + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN, > + .mask_bit = 2, > + .mask_reset_inv = true, > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, > + .rst_stat_bit = 0, > + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT, > + .cnt_en_bit = 8, > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN | > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG, > +}; > + > +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = { > + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN, > + .mask_bit = 2, > + .mask_reset_inv = true, > + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, > + .rst_stat_bit = 1, > + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT, > + .cnt_en_bit = 7, > + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN | > + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG, > +}; > + > +static const struct s3c2410_wdt_variant drv_data_gs201_cl0 = { I do not see the difference between this and drv_data_gs101_cl0. Same for cluster 1. Looks like these are compatible, so make them compatible. Also same concerns as Guenter's has. Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel