From: Stephen Boyd <sboyd@kernel.org>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: mturquette@baylibre.com, matthias.bgg@gmail.com,
angelogioacchino.delregno@collabora.com, wenst@chromium.org,
msp@baylibre.com, amergnat@baylibre.com,
yangyingliang@huawei.com, u.kleine-koenig@pengutronix.de,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, kernel@collabora.com
Subject: Re: [PATCH v3 3/3] clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes
Date: Tue, 02 Jan 2024 16:51:40 -0800 [thread overview]
Message-ID: <65e4793fc4aaeadbda9b422e1ac8cc0c.sboyd@kernel.org> (raw)
In-Reply-To: <20231103102533.69280-4-angelogioacchino.delregno@collabora.com>
Quoting AngeloGioacchino Del Regno (2023-11-03 03:25:33)
> The top_dp and top_edp muxes can be both parented to either TVDPLL1
> or TVDPLL2, two identically specced PLLs for the specific purpose of
> giving out pixel clock: this becomes a problem when the MediaTek
> DisplayPort Interface (DPI) driver tries to set the pixel clock rate.
>
> In the usecase of two simultaneous outputs (using two controllers),
> it was seen that one of the displays would sometimes display garbled
> output (if any at all) and this was because:
> - top_edp was set to TVDPLL1, outputting X GHz
> - top_dp was set to TVDPLL2, outputting Y GHz
> - mtk_dpi calls clk_set_rate(top_edp, Z GHz)
> - top_dp is switched to TVDPLL1
> - TVDPLL1 changes its rate, top_edp outputs the wrong rate.
> - eDP display is garbled
>
> To solve this issue, remove all TVDPLL1 parents from `top_dp` and
> all TVDPLL2 parents from `top_edp`, plus, necessarily switch both
> clocks to use the new MUX_GATE_CLR_SET_UPD_INDEXED() macro to be
> able to use the right bit index for the new parents list.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
Applied to clk-next
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next prev parent reply other threads:[~2024-01-03 0:52 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-03 10:25 [PATCH v3 0/3] MediaTek clocks: Support mux indices list and 8195 DP AngeloGioacchino Del Regno
2023-11-03 10:25 ` [PATCH v3 1/3] clk: mediatek: clk-mux: Support custom parent indices for muxes AngeloGioacchino Del Regno
2023-11-23 4:03 ` Fei Shao
2024-01-03 0:51 ` Stephen Boyd
2023-11-03 10:25 ` [PATCH v3 2/3] clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes AngeloGioacchino Del Regno
2023-11-23 4:04 ` Fei Shao
2024-01-03 0:51 ` Stephen Boyd
2023-11-03 10:25 ` [PATCH v3 3/3] clk: mediatek: mt8188-topckgen: " AngeloGioacchino Del Regno
2023-11-06 8:50 ` Alexandre Mergnat
2023-11-06 8:58 ` Chen-Yu Tsai
2023-11-23 4:05 ` Fei Shao
2024-01-03 0:51 ` Stephen Boyd [this message]
2023-12-20 14:02 ` [PATCH v3 0/3] MediaTek clocks: Support mux indices list and 8195 DP AngeloGioacchino Del Regno
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