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Tue, 05 Mar 2024 01:27:41 -0800 (PST) Received: from localhost.localdomain ([2402:3a80:863:befc:ec5c:8cb:6f1e:1f69]) by smtp.gmail.com with ESMTPSA id y16-20020a056a00181000b006e63039486esm1812329pfa.189.2024.03.05.01.27.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Mar 2024 01:27:41 -0800 (PST) Message-ID: <65e6e58d.050a0220.6580e.7a57@mx.google.com> X-Google-Original-Message-ID: <20240103122005.GA3347@francesco-nb> (raw) From: pratikmanvar09@gmail.com To: francesco@dolcini.it Cc: festevam@gmail.com, jun.li@nxp.com, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, oe-kbuild-all@lists.linux.dev, pratik.manvar@ifm.com, pratikmanvar09@gmail.com, s.hauer@pengutronix.de, shawnguo@kernel.org, thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de, xiaoning.wang@nxp.com Subject: Re: [PATCH v3] pwm: imx27: workaround of the pwm output bug Date: Tue, 5 Mar 2024 14:57:29 +0530 X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240103110200.1018-1-pratikmanvar09@gmail.com> References: <20240103122005.GA3347@francesco-nb> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240305_012743_504458_DA78BBC8 X-CRM114-Status: GOOD ( 15.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello Francesco, Sorry for the abysmal delay. Thanks for your review and suggestions. >Hello Pratik, > >On Wed, Jan 03, 2024 at 04:32:00PM +0530, pratikmanvar09@gmail.com wrote: >> From: Clark Wang >> >> This fixes the pwm output bug when decrease the duty cycle. >> This is a limited workaround for the PWM IP issue TKT0577206. >> >> Root cause: >> When the SAR FIFO is empty, the new write value will be directly applied >> to SAR even the current period is not over. >> If the new SAR value is less than the old one, and the counter is >> greater than the new SAR value, the current period will not filp the >> level. This will result in a pulse with a duty cycle of 100%. >> >> Workaround: >> Add an old value SAR write before updating the new duty cycle to SAR. >> This will keep the new value is always in a not empty fifo, and can be >> wait to update after a period finished. >> >> Limitation: >> This workaround can only solve this issue when the PWM period is longer >> than 2us(or <500KHz). >> >> Reviewed-by: Jun Li >> Signed-off-by: Clark Wang >> Link: https://github.com/nxp-imx/linux-imx/commit/16181cc4eee61d87cbaba0e5a479990507816317 >> Tested-by: Pratik Manvar >> Signed-off-by: Pratik Manvar > >A very similar patch was already send in 2021 [1], did it had review >comments not addressed? Please have a look. > >In general please refrain from sending a new patch version every other >day, while every Linux kernel subsystem has different rules and a >difference pace of development, in this specific case sending a v3 just >adding your signed-off-by without allowing a little bit of time to wait >for more feedback is just not sane. Ok, I will keep this in mind. Thanks! > >[1] https://lore.kernel.org/all/?q=dfn%3Adrivers%2Fpwm%2Fpwm-imx27.c+AND+b%3A%22Clark+Wang%22 Ok, I did not check this. I will look into this. Thanks! Thanks & Regards, Pratik Manvar _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel