From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 157BDE95A8E for ; Mon, 9 Oct 2023 09:44:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LSaFLss1TvAuDAJnaCTszrYjTAN1nBXWQKpuUyTa9hU=; b=S3FuoOBq3drHKU vxUtzKkFi/zApDOu7wW3A+Zc2EPf4tBadrRiYA4y3+mlnAOEljhlwRfHJxZVHy0OGq4b1jb9pV3TN SHx2Fqqh9+t8eVwo/dZwA3Il+ubO0iyD+BGc30Exp2ENxvuSTSlTSyjeJPe7UdfX8ImPpz2s/9R7d IG41SaLJFmJQ2v+92ZwLKOAZkfqj+5poM9UsvWd0atqSKV4GgLS+yj5p0Kb0zXxzXoIY+uXBA4+Ej YD0RhONCRpA+I1B/Wzr+vFOcJ9Oj354LRj19JCvfXzDkjxTwDE7gr6deA2VX4nB2ki85hZq9bJZg1 ogcjxBYOqV32udrYXp+w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qpmnb-00A7cB-00; Mon, 09 Oct 2023 09:43:39 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qpmnY-00A7bM-01 for linux-arm-kernel@lists.infradead.org; Mon, 09 Oct 2023 09:43:37 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 592F01FB; Mon, 9 Oct 2023 02:44:15 -0700 (PDT) Received: from [192.168.1.3] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D6D583F7A6; Mon, 9 Oct 2023 02:43:33 -0700 (PDT) Message-ID: <66125bc2-ff2a-a209-a753-c2e3d8310a45@arm.com> Date: Mon, 9 Oct 2023 10:43:34 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH] drivers: perf: arm_pmuv3: Update 'pmc_width' based on actual HW event width Content-Language: en-US To: Anshuman Khandual , linux-arm-kernel@lists.infradead.org, Rob Herring , raphael.gault@arm.com Cc: Will Deacon , Mark Rutland , linux-kernel@vger.kernel.org References: <20231009043724.175100-1-anshuman.khandual@arm.com> From: James Clark In-Reply-To: <20231009043724.175100-1-anshuman.khandual@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231009_024336_092596_DC68B1AF X-CRM114-Status: GOOD ( 19.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 09/10/2023 05:37, Anshuman Khandual wrote: > This updates 'perf_event_mmap_page->pmc_width' based on actual HW event's > width that are currently missing i.e ARMPMU_EVT_63BIT and ARMPMU_EVT_47BIT. > Might be worth adding why this is needed or what the actual effect is. > Cc: Will Deacon > Cc: Mark Rutland > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Anshuman Khandual > --- > This applies on v6.6-rc5. > > drivers/perf/arm_pmuv3.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c > index fe4db1831662..94723d00548e 100644 > --- a/drivers/perf/arm_pmuv3.c > +++ b/drivers/perf/arm_pmuv3.c > @@ -1375,6 +1375,10 @@ void arch_perf_update_userpage(struct perf_event *event, > if (userpg->cap_user_rdpmc) { > if (event->hw.flags & ARMPMU_EVT_64BIT) > userpg->pmc_width = 64; > + else if (event->hw.flags & ARMPMU_EVT_63BIT) > + userpg->pmc_width = 63; > + else if (event->hw.flags & ARMPMU_EVT_47BIT) > + userpg->pmc_width = 47; Although it doesn't explicitly say it, the bit of the docs about pmc_width in Documentation/arch/arm64/perf.rst loosely implies that this is always either 64 or 32. Now that this isn't the case it could mislead someone in userspace that they don't have to handle the now arbitrary bit widths rather than just whole bytes/ints. I think the fix is as simple as adding something like "the width may not match the requested value or necessarily be a multiple of 8". Unless we think this is already widely known and I suppose we could leave it as is. (The existing bit in perf that uses it already handles it correctly). > else > userpg->pmc_width = 32; > } _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel