From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED362C27C53 for ; Fri, 7 Jun 2024 06:42:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4JtS1Kh1GpNcL0AKf+/CCzGAEQqNAiqVFPWHYG3W734=; b=dPGsgshDAy28gS 5SU2p9k8wkrB+xaGYuh0meljlUsX9Nzor19B3bLK2StFoEsvTgaGXArvCEftUS3WMPwgGuW6Jbgyc XdFk5ZIN6lQXa1yUukSFMGtl2QdxE1k9e8/r9+Co8HcxU+nYHA8HItBICmGaa0xei/0AXCFhDlZtE FNwRO/Gh/0RFXh11YnTymiz5WfFq06F2+3SYybNfeCjTj/sxezwELmmE6yvMYwDYJarj3VuteeO61 AZ7MyJUvI8h9JVYWyUKbO/DifeBtBop08pd6XQG67BQQ6ASlevUel+t/IOkgcG+lonRYt2nOg2wio zEuyO8qr37/h7FrtI8qg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFTIS-0000000Cjwf-0yKe; Fri, 07 Jun 2024 06:41:56 +0000 Received: from mx1.tq-group.com ([93.104.207.81]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFTIN-0000000Cju2-2q64 for linux-arm-kernel@lists.infradead.org; Fri, 07 Jun 2024 06:41:54 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1717742511; x=1749278511; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oDWXk9Ip84mUFg4/ADwA1LpVB7/h3jEawVahgnt2/Uc=; b=BDsWbsM4Vl+aoU3JjjVxxGFTA9Ck3IPcvXqHS6OhhgXlz1lXZbsTFU+T ElhtUdsiZwXo9kYgXtYuGw9dkYh8+k3tt1lZdaBID8gnSNHTMOj6v7omj yflWdg5bvZHHFV7Hv7lYJRC7vUUrbsMfcP+YoSnkGR7WFZSrdCqgAxK0J 5hoeweGkGyTjAUZNtM+S1wevLftPGrLaQ9z45IV362EwWl/GIyfyHq6sd rIGqhDNECGGxet4w0MshSGkYNZeX2btktqLG5chNK3JJz6CPtj69J4Qn1 QOI98z1zor2uv6YLBac/naV65cdeb61/7hEn508EPWebVSHtOQbx41HBQ A==; X-CSE-ConnectionGUID: 5Kjk5ea1S1+33Ri51/5AbQ== X-CSE-MsgGUID: aZeO6HILRgmYG2mb3kahhQ== X-IronPort-AV: E=Sophos;i="6.08,220,1712613600"; d="scan'208";a="37274501" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 07 Jun 2024 08:41:49 +0200 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 4795E170735; Fri, 7 Jun 2024 08:41:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1717742505; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=oDWXk9Ip84mUFg4/ADwA1LpVB7/h3jEawVahgnt2/Uc=; b=RxZ88pIN1B/ayw7taFUeqJxc5cTZM3sOiQj3SMST85ctsblSS+DjPwe46dFLcbrKMLdVlb HieWJHLTUu0M4ceY19Cmr+tFGXMObSWtDA7fBCS/trj5613nQbAffpVQqa50jLzn6IZC+8 DXAl4rcjnSe9+cxwEF8OWDCon8pxgQu6ugiN1S4qStOwgqxHoSnS9f/M1Y2uQBPlQdpUll qQhuMVUMXOctQnlmiemriQ2VmA0L6ekvaHb3wOl1IDW29ialDhv0dWuKmGxsXJlsiFC0oB WCT9QfsQKt+9uh9AXAc6rsqcOrhlTxH0zoZ6O0rInT7rnAVn6c8HrWxyYyeD7w== From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dong Aisheng , linux-arm-kernel@lists.infradead.org, Frank Li Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Frank Li Subject: Re: [PATCH 2/7] arm64: dts: imx8qm: add mipi subsystem Date: Fri, 07 Jun 2024 08:41:44 +0200 Message-ID: <6638616.G0QQBjFxQf@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20240606-imx8qm-dts-usb-v1-2-565721b64f25@nxp.com> References: <20240606-imx8qm-dts-usb-v1-0-565721b64f25@nxp.com> <20240606-imx8qm-dts-usb-v1-2-565721b64f25@nxp.com> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240606_234152_353720_B114F76B X-CRM114-Status: GOOD ( 13.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, thanks for the patch. What are your plans regarding imx8xqp? This memory region has dual use on imx8qxp mipi/lvds0. I would prefer imx8-ss-mipi.dtsi with common parts and a imx8qm-ss-mipi.dtsi adding/modifying imx8qm specific things. I'll send my current WIP as a response to this. Best regards, Alexander Am Donnerstag, 6. Juni 2024, 20:46:56 CEST schrieb Frank Li: > Add irqstear, pwm and i2c in mipi subsystem. > = > Signed-off-by: Frank Li > --- > arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi | 286 ++++++++++++++++= ++++++ > arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 + > 2 files changed, 287 insertions(+) > = > diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi b/arch/arm= 64/boot/dts/freescale/imx8qm-ss-mipi.dtsi > new file mode 100644 > index 0000000000000..bd18468923e52 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-mipi.dtsi > @@ -0,0 +1,286 @@ > +// SPDX-License-Identifier: GPL-2.0+ > + > +/* > + * Copyright 2024 NXP > + */ > + > +/ { > + dsi_ipg_clk: clock-dsi-ipg { > + compatible =3D "fixed-clock"; > + #clock-cells =3D <0>; > + clock-frequency =3D <120000000>; > + clock-output-names =3D "dsi_ipg_clk"; > + }; > + > + mipi_pll_div2_clk: clock-mipi-div2-pll { > + compatible =3D "fixed-clock"; > + #clock-cells =3D <0>; > + clock-frequency =3D <432000000>; > + clock-output-names =3D "mipi_pll_div2_clk"; > + }; > + > + mipi0_subsys: bus@56220000 { > + compatible =3D "simple-bus"; > + interrupt-parent =3D <&irqsteer_mipi0>; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + ranges =3D <0x56220000 0x0 0x56220000 0x10000>; > + > + irqsteer_mipi0: interrupt-controller@56220000 { > + compatible =3D "fsl,imx-irqsteer"; compatible =3D "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer" or even compatible =3D "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer". Please refer to [= 1]. [1] https://lore.kernel.org/all/20240528071141.92003-1-alexander.stein@ew.t= q-group.com/ > + reg =3D <0x56220000 0x1000>; > + interrupts =3D ; > + interrupt-controller; > + interrupt-parent =3D <&gic>; > + #interrupt-cells =3D <1>; > + clocks =3D <&mipi0_lis_lpcg IMX_LPCG_CLK_0>; > + clock-names =3D "ipg"; > + power-domains =3D <&pd IMX_SC_R_MIPI_0>; > + fsl,channel =3D <0>; > + fsl,num-irqs =3D <32>; > + }; > + > + mipi0_lis_lpcg: clock-controller@56223000 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x56223000 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&dsi_ipg_clk>; > + clock-indices =3D ; > + clock-output-names =3D "mipi0_lis_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_0>; > + }; > + > + mipi0_pwm_lpcg: clock-controller@5622300c { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x5622300c 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>, > + <&dsi_ipg_clk>; > + clock-indices =3D , ; > + clock-output-names =3D "mipi0_pwm_lpcg_clk", > + "mipi0_pwm_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_0_PWM_0>; > + }; > + > + mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x56223014 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&mipi0_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>; > + clock-indices =3D ; > + clock-output-names =3D "mipi0_i2c0_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_0_I2C_0>; > + }; > + > + mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x56223018 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&dsi_ipg_clk>; > + clock-indices =3D ; > + clock-output-names =3D "mipi0_i2c0_lpcg_ipg_s_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_0_I2C_0>; > + }; > + > + mipi0_i2c0_lpcg_clk: clock-controller@5622301c { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x5622301c 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>; > + clock-indices =3D ; > + clock-output-names =3D "mipi0_i2c0_lpcg_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_0_I2C_0>; > + }; > + > + mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x56223024 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&mipi0_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>; > + clock-indices =3D ; > + clock-output-names =3D "mipi0_i2c1_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_0_I2C_1>; > + }; > + > + mipi0_i2c1_lpcg_clk: clock-controller@5622302c { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x5622302c 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>; > + clock-indices =3D ; > + clock-output-names =3D "mipi0_i2c1_lpcg_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_0_I2C_1>; > + }; > + > + mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x56223028 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&dsi_ipg_clk>; > + clock-indices =3D ; > + clock-output-names =3D "mipi0_i2c1_lpcg_ipg_s_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_0_I2C_1>; > + }; > + > + pwm_mipi0: pwm@56224000 { > + compatible =3D "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; > + reg =3D <0x56224000 0x1000>; > + clocks =3D <&mipi0_pwm_lpcg IMX_LPCG_CLK_4>, > + <&mipi0_pwm_lpcg IMX_LPCG_CLK_0>; > + clock-names =3D "ipg", "per"; > + assigned-clocks =3D <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>; > + assigned-clock-rates =3D <24000000>; > + #pwm-cells =3D <3>; > + power-domains =3D <&pd IMX_SC_R_MIPI_0_PWM_0>; > + status =3D "disabled"; > + }; > + > + i2c0_mipi0: i2c@56226000 { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + compatible =3D "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg =3D <0x56226000 0x1000>; > + interrupts =3D <8>; > + clocks =3D <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>, > + <&mipi0_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>; > + clock-names =3D "per", "ipg"; > + assigned-clocks =3D <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>; > + assigned-clock-rates =3D <24000000>; > + power-domains =3D <&pd IMX_SC_R_MIPI_0_I2C_0>; > + status =3D "disabled"; > + }; > + }; > + > + mipi1_subsys: bus@57220000 { > + compatible =3D "simple-bus"; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + ranges =3D <0x57220000 0x0 0x57220000 0x10000>; > + > + irqsteer_mipi1: interrupt-controller@57220000 { > + compatible =3D "fsl,imx-irqsteer"; > + reg =3D <0x57220000 0x1000>; > + interrupts =3D ; > + interrupt-controller; > + interrupt-parent =3D <&gic>; > + #interrupt-cells =3D <1>; > + clocks =3D <&mipi1_lis_lpcg IMX_LPCG_CLK_0>; > + clock-names =3D "ipg"; > + power-domains =3D <&pd IMX_SC_R_MIPI_1>; > + fsl,channel =3D <0>; > + fsl,num-irqs =3D <32>; > + }; > + > + mipi1_lis_lpcg: clock-controller@57223000 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x57223000 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&dsi_ipg_clk>; > + clock-indices =3D ; > + clock-output-names =3D "mipi1_lis_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_1>; > + }; > + > + mipi1_pwm_lpcg: clock-controller@5722300c { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x5722300c 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>, > + <&dsi_ipg_clk>; > + clock-indices =3D , ; > + clock-output-names =3D "mipi1_pwm_lpcg_clk", > + "mipi1_pwm_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_1_PWM_0>; > + }; > + > + mipi1_i2c0_lpcg_clk: clock-controller@5722301c { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x5722301c 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>; > + clock-indices =3D ; > + clock-output-names =3D "mipi1_i2c0_lpcg_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_1_I2C_0>; > + }; > + > + mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x57223014 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&mipi1_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>; > + clock-indices =3D ; > + clock-output-names =3D "mipi1_i2c0_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_1_I2C_0>; > + }; > + > + mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x57223018 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&dsi_ipg_clk>; > + clock-indices =3D ; > + clock-output-names =3D "mipi1_i2c0_lpcg_ipg_s_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_1_I2C_0>; > + }; > + > + mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x57223024 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&mipi1_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>; > + clock-indices =3D ; > + clock-output-names =3D "mipi1_i2c1_lpcg_ipg_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_1_I2C_1>; > + }; > + > + mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x57223028 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&dsi_ipg_clk>; > + clock-indices =3D ; > + clock-output-names =3D "mipi1_i2c1_lpcg_ipg_s_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_1_I2C_1>; > + }; > + > + mipi1_i2c1_lpcg_clk: clock-controller@5722302c { > + compatible =3D "fsl,imx8qxp-lpcg"; > + reg =3D <0x5722302c 0x4>; > + #clock-cells =3D <1>; > + clocks =3D <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>; > + clock-indices =3D ; > + clock-output-names =3D "mipi1_i2c1_lpcg_clk"; > + power-domains =3D <&pd IMX_SC_R_MIPI_1_I2C_1>; > + }; > + > + pwm_mipi1: pwm@57224000 { > + compatible =3D "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; > + reg =3D <0x57224000 0x1000>; > + clocks =3D <&mipi1_pwm_lpcg IMX_LPCG_CLK_4>, > + <&mipi1_pwm_lpcg IMX_LPCG_CLK_0>; > + clock-names =3D "ipg", "per"; > + assigned-clocks =3D <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>; > + assigned-clock-rates =3D <24000000>; > + #pwm-cells =3D <3>; > + power-domains =3D <&pd IMX_SC_R_MIPI_1_PWM_0>; > + status =3D "disabled"; > + }; > + > + i2c0_mipi1: i2c@57226000 { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + compatible =3D "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; > + reg =3D <0x57226000 0x1000>; > + interrupts =3D <8>; > + interrupt-parent =3D <&irqsteer_mipi1>; > + clocks =3D <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>, > + <&mipi1_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>; > + clock-names =3D "per", "ipg"; > + assigned-clocks =3D <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>; > + assigned-clock-rates =3D <24000000>; > + power-domains =3D <&pd IMX_SC_R_MIPI_1_I2C_0>; > + status =3D "disabled"; > + }; > + }; > +}; > + > diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/= dts/freescale/imx8qm.dtsi > index 9f29fe4589668..846b95be22bbe 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi > @@ -577,3 +577,4 @@ clk_spdif1_rx: clock-spdif1-rx { > #include "imx8qm-ss-lsio.dtsi" > #include "imx8qm-ss-audio.dtsi" > #include "imx8qm-ss-lvds.dtsi" > +#include "imx8qm-ss-mipi.dtsi" > = > = -- = TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel