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[79.55.57.217]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427bb9976casm9090835e9.1.2024.07.16.02.27.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jul 2024 02:27:33 -0700 (PDT) Date: Tue, 16 Jul 2024 11:27:33 +0200 From: Matteo Martelli To: Maxime Ripard , Matteo Martelli Cc: Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Marcus Cooper , =?UTF-8?B?Q2zDqW1lbnQgUMOpcm9u?= , linux-sound@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Message-ID: <66963d0531f17_7063708a@njaxe.notmuch> In-Reply-To: <20240715-rigorous-bipedal-sloth-c8df1b@houat> References: <20240529140658.180966-2-matteomartelli3@gmail.com> <20240529140658.180966-3-matteomartelli3@gmail.com> <20240606-savvy-wallaby-of-champagne-d4a50e@houat> <6662bf1b61bbc_2f51737023@njaxe.notmuch> <20240702-copperhead-of-unusual-intensity-7f43a8@houat> <668419fb8ef9f_2a76d370f1@njaxe.notmuch> <20240715-rigorous-bipedal-sloth-c8df1b@houat> Subject: Re: [PATCH 1/1] ASoC: sunxi: sun4i-i2s: fix LRCLK polarity in i2s mode Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240716_022736_879056_5EF629BC X-CRM114-Status: GOOD ( 30.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Maxime Ripard wrote: > On Tue, Jul 02, 2024 at 05:17:15PM GMT, Matteo Martelli wrote: > > Maxime Ripard wrote: > > > On Fri, Jun 07, 2024 at 10:04:43AM GMT, Matteo Martelli wrote: > > > > Maxime Ripard wrote: > > > > > > - /* > > > > > > - * DAI clock polarity > > > > > > - * > > > > > > - * The setup for LRCK contradicts the datasheet, but under a > > > > > > - * scope it's clear that the LRCK polarity is reversed > > > > > > - * compared to the expected polarity on the bus. > > > > > > - */ > > > > > > > > > > I think we should keep that comment somewhere. > > > > > > > > I think that keeping that comment would be very misleading since the LRCLK > > > > setup would not contradict the datasheet anymore [1][2]. > > > > > > > > Also, do you recall any details about the mentioned scope test setup? Was i2s > > > > mode tested in that occasion? It would help clarify the situation. > > > > > > I can't remember if I tested i2s, I think I did though. But most of the > > > work was done on either TDM or DSP modes, and I remember very clearly > > > that the LRCK polarity was inverted compared to what Allwinner documents. > > > > > > So the doc was, at best, misleading for these formats and we should keep > > > the comments. > > > > Thanks for the reply Maxime, would you be able to point out the Allwinner > > document part that is (or was) misleading? The current datasheets (see links > > [1][2]) look correct, the current driver setup for TDM and DSP modes respects > > those datasheets and it's not "reversed compared to the expected polarity on > > the bus" as the comment states. > > I clearly remember having to debug something there, but I don't remember > much more, sorry. > > I guess if you have tested on the H3 I2S, TDM and DSP and it all works > as expected with your changes, go ahead and ignore my comment then. I did test it on the A64 SoC only (all modes I2S, TDM and DSP working). Best reguards, Matteo