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Thu, 23 May 2024 14:25:24 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3AFF420043; Thu, 23 May 2024 14:25:22 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E054D20040; Thu, 23 May 2024 14:25:21 +0000 (GMT) Received: from li-978a334c-2cba-11b2-a85c-a0743a31b510.ibm.com (unknown [9.152.224.238]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 23 May 2024 14:25:21 +0000 (GMT) Message-ID: <66a7077c5df86d0a541237996382ae583d690a14.camel@linux.ibm.com> Subject: Re: [PATCH v2 11/11] KVM: arm64: Get rid of the AArch32 register mapping code From: Nina Schoetterl-Glausch To: Marc Zyngier , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Cc: James Morse , Julien Thierry , Suzuki K Poulose , Andrew Scull , Will Deacon , Mark Rutland , Quentin Perret , David Brazdil , kernel-team@android.com Date: Thu, 23 May 2024 16:25:21 +0200 In-Reply-To: <20201102164045.264512-12-maz@kernel.org> References: <20201102164045.264512-1-maz@kernel.org> <20201102164045.264512-12-maz@kernel.org> User-Agent: Evolution 3.48.4 (3.48.4-1.fc38) MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: dIS4mzedkeYOUhEU40jF8cSIVctJGfFw X-Proofpoint-GUID: mDZJ3ICKHzZwW-sjSEVq4XxZ_Fr66Cxr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-23_09,2024-05-23_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 adultscore=0 priorityscore=1501 suspectscore=0 mlxscore=0 malwarescore=0 mlxlogscore=999 clxscore=1011 phishscore=0 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405230099 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240523_072538_012034_4B53C42F X-CRM114-Status: GOOD ( 24.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 2020-11-02 at 16:40 +0000, Marc Zyngier wrote: [...] > diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c > index dfb5218137ca..3f23f7478d2a 100644 > --- a/arch/arm64/kvm/guest.c > +++ b/arch/arm64/kvm/guest.c > @@ -252,10 +252,32 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) > memcpy(addr, valp, KVM_REG_SIZE(reg->id)); I was looking at KVM_(G|S)ET_ONE_REG implementations and something looks off to me here: ... if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) { u64 mode = (*(u64 *)valp) & PSR_AA32_MODE_MASK; switch (mode) { Masking and switch over mode here... case PSR_AA32_MODE_USR: if (!kvm_supports_32bit_el0()) return -EINVAL; break; case PSR_AA32_MODE_FIQ: case PSR_AA32_MODE_IRQ: ... > > if (*vcpu_cpsr(vcpu) & PSR_MODE32_BIT) { > - int i; > + int i, nr_reg; > + > + switch (*vcpu_cpsr(vcpu)) { ...but switching over mode without masking here. I don't know if this is as intended, but I thought I'd mention it. > + /* > + * Either we are dealing with user mode, and only the > + * first 15 registers (+ PC) must be narrowed to 32bit. > + * AArch32 r0-r14 conveniently map to AArch64 x0-x14. > + */ > + case PSR_AA32_MODE_USR: > + case PSR_AA32_MODE_SYS: > + nr_reg = 15; > + break; > + > + /* > + * Otherwide, this is a priviledged mode, and *all* the > + * registers must be narrowed to 32bit. > + */ > + default: > + nr_reg = 31; > + break; > + } > + > + for (i = 0; i < nr_reg; i++) > + vcpu_set_reg(vcpu, i, (u32)vcpu_get_reg(vcpu, i)); > > - for (i = 0; i < 16; i++) > - *vcpu_reg32(vcpu, i) = (u32)*vcpu_reg32(vcpu, i); > + *vcpu_pc(vcpu) = (u32)*vcpu_pc(vcpu); > } > out: > return err; > diff --git a/arch/arm64/kvm/regmap.c b/arch/arm64/kvm/regmap.c > deleted file mode 100644 > index ae7e290bb017..000000000000 > --- a/arch/arm64/kvm/regmap.c > +++ /dev/null > @@ -1,128 +0,0 @@ [...] > -unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num) > -{ > - unsigned long *reg_array = (unsigned long *)&vcpu->arch.ctxt.regs; > - unsigned long mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK; There used to be masking here at least. > - > - switch (mode) { > - case PSR_AA32_MODE_USR ... PSR_AA32_MODE_SVC: > - mode &= ~PSR_MODE32_BIT; /* 0 ... 3 */ > - break; > - > - case PSR_AA32_MODE_ABT: > - mode = 4; > - break; > - > - case PSR_AA32_MODE_UND: > - mode = 5; > - break; > - > - case PSR_AA32_MODE_SYS: > - mode = 0; /* SYS maps to USR */ > - break; > - > - default: > - BUG(); > - } > - > - return reg_array + vcpu_reg_offsets[mode][reg_num]; > -} _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel