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[79.47.255.50]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-371898ac074sm8334097f8f.106.2024.08.18.09.06.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Aug 2024 09:06:01 -0700 (PDT) Message-ID: <66c21be9.5d0a0220.2350c8.75dd@mx.google.com> X-Google-Original-Message-ID: Date: Sun, 18 Aug 2024 17:42:06 +0200 From: Christian Marangi To: Andrew Lunn Cc: Benjamin Larsson , Rob Herring , Krzysztof Kozlowski , Lorenzo Bianconi , linux-gpio@vger.kernel.org, linus.walleij@linaro.org, sean.wang@kernel.org, linux-mediatek@lists.infradead.org, lorenzo.bianconi83@gmail.com, krzk+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, upstream@airoha.com, angelogioacchino.delregno@collabora.com, conor+dt@kernel.org Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: airoha: Add EN7581 pinctrl controller References: <0d537e88b64847bc4e49756b249b2efdcf489b92.1723392444.git.lorenzo@kernel.org> <22144671-fc7c-4cb2-8bb6-ee7d3fbfcb0e@kernel.org> <20240816225257.GA2411475-robh@kernel.org> <1d223ae5-cd2c-4883-b293-bb182e90222b@genexis.eu> <6da7acc8-f77e-453c-b2fa-4eb9161f637c@lunn.ch> <3a52e550-1bb1-40fc-b7dd-b454d7c97f97@genexis.eu> <19793afa-dc62-421f-ba09-8ca2815ae4a2@lunn.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <19793afa-dc62-421f-ba09-8ca2815ae4a2@lunn.ch> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240818_090606_085542_5F586DA1 X-CRM114-Status: GOOD ( 23.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Aug 18, 2024 at 06:02:28PM +0200, Andrew Lunn wrote: > On Sun, Aug 18, 2024 at 02:48:05PM +0200, Benjamin Larsson wrote: > > On 17/08/2024 23:39, Andrew Lunn wrote: > > > How messy are the GPIO and PWM registers? Are there N blocks of > > > independent GPIO registers? and M blocks of independent PWM registers? > > > By that, does one block of GPIO registers contain all you need for one > > > GPIO controller? One block of PWM registers give you all you need for > > > one PWM controller? Or are the registers for one GPIO controller > > > scattered all over the place? > > > > > > Could you point at a public datasheet? > > > > > > Andrew > > > > > Hi, per my understanding there is no public datasheet/register reference > > manual. > > > > But here is the division of regions of the registers in the gpio block and > > how it is currently divided between the drivers (according to my current > > understanding). > > > > 1FBF0200, gpio/pinctrl > > 1FBF0204, gpio/pinctrl > > 1FBF0208, gpio/pinctrl > > 1FBF020C, gpio/pinctrl > > 1FBF0210, gpio/pinctrl > > 1FBF0214, gpio/pinctrl > > A typical SoC has multiple instances of a GPIO controller. Each GPIO > controller typically has 4 or 5 registers: In, Out, Direction, > Interrupt Enable, Interrupt Status. If these 4 or 5 registers are > contiguous, you could have one DT node per controller, rather than one > node for all GPIO controllers. > > If the hardware designer has really messed up and fully interleaved > GPIO and PWM, it might be better to have an MFD. The MFD node has a > single reg covering the entire range. The MFD would then map the whole > range, and provide accessors to the child devices. Hard code the > knowledge of what registers are where. Given how badly the hardware is > designed, it is unlikely it will get reused in the future, so there is > no point putting lots of stuff into DT. Hard code it. > Problem is that the MFD will also affect other stuff like watchdog... thermal sensor/monitor, clocks... They really messed and put in that range all kind of stuff so we would end up in a very big mapped range and lots of child for the MFD. -- Ansuel