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(93-34-91-161.ip49.fastwebnet.it. [93.34.91.161]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432aa6b60e9sm31713315e9.14.2024.11.06.10.11.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 10:11:22 -0800 (PST) Message-ID: <672bb14a.7b0a0220.fded0.9db6@mx.google.com> X-Google-Original-Message-ID: Date: Wed, 6 Nov 2024 19:11:18 +0100 From: Christian Marangi To: Andrew Lunn Cc: Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Matthias Brugger , AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, upstream@airoha.com Subject: Re: [net-next PATCH v3 3/3] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY References: <20241106122254.13228-1-ansuelsmth@gmail.com> <20241106122254.13228-4-ansuelsmth@gmail.com> <8e5fd144-2325-43ff-b2b8-92d7f5910392@lunn.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8e5fd144-2325-43ff-b2b8-92d7f5910392@lunn.ch> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241106_101125_925798_607BAA5E X-CRM114-Status: GOOD ( 21.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Nov 06, 2024 at 05:19:03PM +0100, Andrew Lunn wrote: > > +static const u8 dsa_r50ohm_table[] = { > > + 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, > > + 127, 127, 127, 127, 127, 127, 127, 126, 122, 117, > > + 112, 109, 104, 101, 97, 94, 90, 88, 84, 80, > > + 78, 74, 72, 68, 66, 64, 61, 58, 56, 53, > > + 51, 48, 47, 44, 42, 40, 38, 36, 34, 32, > > + 31, 28, 27, 24, 24, 22, 20, 18, 16, 16, > > + 14, 12, 11, 9 > > +}; > > + > > +static int en8855_get_r50ohm_val(struct device *dev, const char *calib_name, > > + u8 *dest) > > +{ > > + u32 shift_sel, val; > > + int ret; > > + int i; > > + > > + ret = nvmem_cell_read_u32(dev, calib_name, &val); > > + if (ret) > > + return ret; > > + > > + shift_sel = FIELD_GET(AN8855_SWITCH_EFUSE_R50O, val); > > + for (i = 0; i < ARRAY_SIZE(dsa_r50ohm_table); i++) > > + if (dsa_r50ohm_table[i] == shift_sel) > > + break; > > Is an exact match expected? Should this be >= so the nearest match is > found? > As strange as this is, yes this is what the original code does. > > + > > + if (i < 8 || i >= ARRAY_SIZE(dsa_r50ohm_table)) > > + *dest = dsa_r50ohm_table[25]; > > + else > > + *dest = dsa_r50ohm_table[i - 8]; > > + > > + return 0; > > +} > > + > > +static int an8855_probe(struct phy_device *phydev) > > +{ > > + struct device *dev = &phydev->mdio.dev; > > + struct device_node *node = dev->of_node; > > + struct air_an8855_priv *priv; > > + int ret; > > + > > + /* If we don't have a node, skip get calib */ > > + if (!node) > > + return 0; > > phydev->priv will be a NULL pointer, causing problems in > an8855_config_init() > Quite unlikely scenario since for the switch, defining the internal PHY in an MDIO node is mandatory but yes it's a fragility. 2 solution: - I check priv in config_init and skip that section - I always set phydev->priv Solution 1 is safer (handle case where for some reason en8855_get_r50ohm_val fails (it's really almost impossible)) but error prone if the PHY gets extended with other parts and priv starts to gets used for other thing. Solution 2 require an extra bool to signal full calibrarion read and is waste more resource (in case calib is not needed...) Anyway thanks for the review! -- Ansuel