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(93-34-91-161.ip49.fastwebnet.it. [93.34.91.161]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434f5774454sm94941465e9.13.2024.12.10.12.59.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2024 12:59:07 -0800 (PST) Message-ID: <6758ab9b.7b0a0220.3347af.914a@mx.google.com> X-Google-Original-Message-ID: Date: Tue, 10 Dec 2024 21:59:04 +0100 From: Christian Marangi To: Vladimir Oltean Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Srinivas Kandagatla , Heiner Kallweit , Russell King , Matthias Brugger , AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, upstream@airoha.com Subject: Re: [net-next PATCH v11 3/9] dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch References: <20241209134459.27110-1-ansuelsmth@gmail.com> <20241209134459.27110-4-ansuelsmth@gmail.com> <20241210204855.7pgvh74irualyxbn@skbuf> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241210204855.7pgvh74irualyxbn@skbuf> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241210_125910_901326_1D6C6577 X-CRM114-Status: GOOD ( 27.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Dec 10, 2024 at 10:48:55PM +0200, Vladimir Oltean wrote: > On Mon, Dec 09, 2024 at 02:44:20PM +0100, Christian Marangi wrote: > > Document support for Airoha AN8855 5-port Gigabit Switch. > > > > It does expose the 5 Internal PHYs on the MDIO bus and each port > > can access the Switch register space by configurting the PHY page. > > typo: configuring > Also below. > > > > > Each internal PHY might require calibration with the fused EFUSE on > > the switch exposed by the Airoha AN8855 SoC NVMEM. > > This paragraph should be irrelevant to the switch binding. > > > > > Signed-off-by: Christian Marangi > > --- > > .../net/dsa/airoha,an8855-switch.yaml | 105 ++++++++++++++++++ > > MAINTAINERS | 1 + > > 2 files changed, 106 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml > > > > diff --git a/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml > > new file mode 100644 > > index 000000000000..63bcbebd6a29 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml > > @@ -0,0 +1,105 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/net/dsa/airoha,an8855-switch.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Airoha AN8855 Gigabit Switch > > + > > +maintainers: > > + - Christian Marangi > > + > > +description: > > > + Airoha AN8855 is a 5-port Gigabit Switch. > > + > > + It does expose the 5 Internal PHYs on the MDIO bus and each port > > + can access the Switch register space by configurting the PHY page. > > + > > + Each internal PHY might require calibration with the fused EFUSE on > > + the switch exposed by the Airoha AN8855 SoC NVMEM. > > + > > +$ref: dsa.yaml# > > + > > +properties: > > + compatible: > > + const: airoha,an8855-switch > > + > > + reset-gpios: > > + description: > > + GPIO to be used to reset the whole device > > + maxItems: 1 > > Since this affects the whole device, the SoC node (handled by the > MFD driver) should handle it. Otherwise you expose the code to weird > race conditions where one child MFD device resets the whole chip after > the other MFD children have probed, and this undoes their settings. > OK. > > + > > + airoha,ext-surge: > > + $ref: /schemas/types.yaml#/definitions/flag > > + description: > > + Calibrate the internal PHY with the calibration values stored in EFUSE > > + for the r50Ohm values. > > Doesn't seem that this pertains to the switch. Do you think this should be placed in each PHY node? I wanted to prevent having to define a schema also for PHY if possible given how integrated these are. (originally it was defined in DT node to follow how it was done in Airoha SDK) -- Ansuel