From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC509C433EF for ; Thu, 19 May 2022 08:53:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sTnKKS7St32aqG4RQBnqVxcbEjvoU175qWKjP3YkEV8=; b=3MZ0C6IEmp8y3L kjWnm6O46X/gyMXqjiowK7YtiRmFhFdl0M8jmKciAdm6jJ7jAPS23D9IdRFOagRhCXlZ4pSGhHAbV eWiEg0W+f7IrhmZQo2FlD9bVPnMlxDJ+lJwT2OsZyC075KoN3CwOqjWORAT2uubRhpQ3hTa47hQjA ZHcaYT7Q28WvDj5BvIGsi/Lxa+A3LRnzS5azuEFfRY8UUEX73eIAVEwnORzCzVM6hOGe46oUciPqU 8MKvaKlWsiPnZlhizyxumQgzaie8sGKlCaFLKj9Uqog6r7PMRjDuYgbx7ItBM4H94p3/Qw0FcSrN2 RPE7WDvO9uo09HhRA82Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrbtG-005zJb-5l; Thu, 19 May 2022 08:52:14 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrbtC-005zHz-BG for linux-arm-kernel@lists.infradead.org; Thu, 19 May 2022 08:52:12 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 55F3215A1; Thu, 19 May 2022 01:52:07 -0700 (PDT) Received: from [10.57.35.249] (unknown [10.57.35.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E14CF3F73D; Thu, 19 May 2022 01:52:04 -0700 (PDT) Message-ID: <67628f62-5081-ba64-cdf6-7410928ba2c2@arm.com> Date: Thu, 19 May 2022 09:52:01 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.9.0 Subject: Re: [PATCH v2 1/2] perf: coresight_pmu: Add support for ARM CoreSight PMU driver To: Besar Wicaksono , robin.murphy@arm.com, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, sudeep.holla@arm.com, thanu.rangarajan@arm.com, Michael.Williams@arm.com, treding@nvidia.com, jonathanh@nvidia.com, vsethi@nvidia.com References: <20220509002810.12412-1-bwicaksono@nvidia.com> <20220515163044.50055-1-bwicaksono@nvidia.com> <20220515163044.50055-2-bwicaksono@nvidia.com> From: Suzuki K Poulose In-Reply-To: <20220515163044.50055-2-bwicaksono@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220519_015210_515974_5FF31302 X-CRM114-Status: GOOD ( 35.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 15/05/2022 17:30, Besar Wicaksono wrote: > Add support for ARM CoreSight PMU driver framework and interfaces. > The driver provides generic implementation to operate uncore PMU based > on ARM CoreSight PMU architecture. The driver also provides interface > to get vendor/implementation specific information, for example event > attributes and formating. > > The specification used in this implementation can be found below: > * ACPI Arm Performance Monitoring Unit table: > https://developer.arm.com/documentation/den0117/latest > * ARM Coresight PMU architecture: > https://developer.arm.com/documentation/ihi0091/latest > > Signed-off-by: Besar Wicaksono > --- > arch/arm64/configs/defconfig | 1 + > drivers/perf/Kconfig | 2 + > drivers/perf/Makefile | 1 + > drivers/perf/coresight_pmu/Kconfig | 11 + > drivers/perf/coresight_pmu/Makefile | 6 + > .../perf/coresight_pmu/arm_coresight_pmu.c | 1267 +++++++++++++++++ > .../perf/coresight_pmu/arm_coresight_pmu.h | 171 +++ > 7 files changed, 1459 insertions(+) > create mode 100644 drivers/perf/coresight_pmu/Kconfig > create mode 100644 drivers/perf/coresight_pmu/Makefile > create mode 100644 drivers/perf/coresight_pmu/arm_coresight_pmu.c > create mode 100644 drivers/perf/coresight_pmu/arm_coresight_pmu.h > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index 2ca8b1b336d2..8f2120182b25 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -1196,6 +1196,7 @@ CONFIG_PHY_UNIPHIER_USB3=y > CONFIG_PHY_TEGRA_XUSB=y > CONFIG_PHY_AM654_SERDES=m > CONFIG_PHY_J721E_WIZ=m > +CONFIG_ARM_CORESIGHT_PMU=y > CONFIG_ARM_SMMU_V3_PMU=m > CONFIG_FSL_IMX8_DDR_PMU=m > CONFIG_QCOM_L2_PMU=y > diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig > index 1e2d69453771..c4e7cd5b4162 100644 > --- a/drivers/perf/Kconfig > +++ b/drivers/perf/Kconfig > @@ -192,4 +192,6 @@ config MARVELL_CN10K_DDR_PMU > Enable perf support for Marvell DDR Performance monitoring > event on CN10K platform. > > +source "drivers/perf/coresight_pmu/Kconfig" > + > endmenu > diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile > index 57a279c61df5..4126a04b5583 100644 > --- a/drivers/perf/Makefile > +++ b/drivers/perf/Makefile > @@ -20,3 +20,4 @@ obj-$(CONFIG_ARM_DMC620_PMU) += arm_dmc620_pmu.o > obj-$(CONFIG_MARVELL_CN10K_TAD_PMU) += marvell_cn10k_tad_pmu.o > obj-$(CONFIG_MARVELL_CN10K_DDR_PMU) += marvell_cn10k_ddr_pmu.o > obj-$(CONFIG_APPLE_M1_CPU_PMU) += apple_m1_cpu_pmu.o > +obj-$(CONFIG_ARM_CORESIGHT_PMU) += coresight_pmu/ > diff --git a/drivers/perf/coresight_pmu/Kconfig b/drivers/perf/coresight_pmu/Kconfig > new file mode 100644 > index 000000000000..89174f54c7be > --- /dev/null > +++ b/drivers/perf/coresight_pmu/Kconfig > @@ -0,0 +1,11 @@ > +# SPDX-License-Identifier: GPL-2.0 > +# > +# Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. > + > +config ARM_CORESIGHT_PMU > + tristate "ARM Coresight PMU" > + depends on ACPI > + depends on ACPI_APMT || COMPILE_TEST > + help > + Provides support for Performance Monitoring Unit (PMU) events based on > + ARM CoreSight PMU architecture. > \ No newline at end of file > diff --git a/drivers/perf/coresight_pmu/Makefile b/drivers/perf/coresight_pmu/Makefile > new file mode 100644 > index 000000000000..a2a7a5fbbc16 > --- /dev/null > +++ b/drivers/perf/coresight_pmu/Makefile > @@ -0,0 +1,6 @@ > +# Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. > +# > +# SPDX-License-Identifier: GPL-2.0 > + > +obj-$(CONFIG_ARM_CORESIGHT_PMU) += \ > + arm_coresight_pmu.o > diff --git a/drivers/perf/coresight_pmu/arm_coresight_pmu.c b/drivers/perf/coresight_pmu/arm_coresight_pmu.c > new file mode 100644 > index 000000000000..36ac77ab85cd > --- /dev/null > +++ b/drivers/perf/coresight_pmu/arm_coresight_pmu.c > @@ -0,0 +1,1267 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * ARM CoreSight PMU driver. > + * > + * This driver adds support for uncore PMU based on ARM CoreSight Performance > + * Monitoring Unit Architecture. The PMU is accessible via MMIO registers and > + * like other uncore PMUs, it does not support process specific events and > + * cannot be used in sampling mode. > + * > + * This code is based on other uncore PMUs like ARM DSU PMU. It provides a > + * generic implementation to operate the PMU according to CoreSight PMU > + * architecture and ACPI ARM PMU table (APMT) documents below: > + * - ARM CoreSight PMU architecture document number: ARM IHI 0091 A.a-00bet0. > + * - APMT document number: ARM DEN0117. > + * The description of the PMU, like the PMU device identification, available > + * events, and configuration options, is vendor specific. The driver provides > + * interface for vendor specific code to get this information. This allows the > + * driver to be shared with PMU from different vendors. > + * > + * CoreSight PMU devices are named as arm_coresight_pmu where > + * is APMT node id. The description of the device, like the identifier, Please see my comment below, near coresight_pmu_alloc(). > + * supported events, and formats can be found in sysfs > + * /sys/bus/event_source/devices/arm_coresight_pmu > + * > + * The user should refer to the vendor technical documentation to get details > + * about the supported events. > + * > + * Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. > + * > + */ ... > +static int coresight_pmu_alloc(struct platform_device *pdev, > + struct coresight_pmu **coresight_pmu) > +{ > + struct acpi_apmt_node *apmt_node; > + struct device *dev; > + struct coresight_pmu *pmu; > + > + dev = &pdev->dev; > + apmt_node = *(struct acpi_apmt_node **)dev_get_platdata(dev); > + if (!apmt_node) { > + dev_err(dev, "failed to get APMT node\n"); > + return -ENOMEM; > + } > + > + pmu = devm_kzalloc(dev, sizeof(*pmu), GFP_KERNEL); > + if (!pmu) > + return -ENOMEM; > + > + *coresight_pmu = pmu; > + > + pmu->dev = dev; > + pmu->apmt_node = apmt_node; > + pmu->name = > + devm_kasprintf(dev, GFP_KERNEL, PMUNAME "%u", apmt_node->id); Could we not name this "__pmu" ? Or even let the "implementor" name it ? After all, for a *normal user*, all it matters is how to find a PMU device for my xyz IP. The coresight_pmu architecture is there to make the life easier for the software driver and the hardware implementation. We don't need to necessarily pass on this abstraction to an end-user and learn how to figure out which "arm_*_pmu" is my PCIe, or SMMU or xyz instance. Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel