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Wed, 9 Jul 2025 23:00:37 -0700 From: Nicolin Chen To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 29/29] iommu/tegra241-cmdqv: Add IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV support Date: Wed, 9 Jul 2025 22:59:21 -0700 Message-ID: <68161a980da41fa5022841209638aeff258557b5.1752126748.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|IA0PR12MB8423:EE_ X-MS-Office365-Filtering-Correlation-Id: f6e9762d-fc4d-4ce6-4af8-08ddbf772300 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?xvfLv8+4q+qFcugrt96eCbPQ2U9MdfMoJQVPZc5iafSsGMag52He9aLAEZww?= =?us-ascii?Q?NJpKxF69DaJCNgX7dFotNP3bpDbrqdRUOWRwCvfDLnBHUsgo79WshnwN3B+X?= =?us-ascii?Q?1pY5Ljg7Ih3l/4U0k6xHNdhKu46gROSBSXWgX/OTuXH85SKsYqf1CyzOQw1y?= =?us-ascii?Q?JRIIsgrqI3GXryI2BBO0QYefEAkre30wpeeeCqtGRtulzDVVnwmbVftQ0fdx?= =?us-ascii?Q?JXwzk+ULg6ngdwV8OecQPKmzCaTTSKI103F6TmYPQ9+95mPUjNUIhaS/y9WO?= =?us-ascii?Q?nsKByhZwyTDfJEoC2ED7d1OpgCWRfPIgoroHzGxYgd4SKKUOEI7AIu8ynUeF?= =?us-ascii?Q?PR2u+47alwVVyXbCOi0TsozGTpJQ9Z6Gu6m61tFD2cf6mNVI4/V99KkNphpo?= =?us-ascii?Q?MSHqsiHF8EmcVjJI+HkWL8xanBBt2vOiDYGKieszChfpDGa8p7EmM0mxefKE?= =?us-ascii?Q?JEiEbHvCpnPLShemWPe58jpHUMtjvfofM2MCAVDXhdtU4fyGL0RwdQaqY8Jq?= =?us-ascii?Q?rzh80rO+SZRmothB1cVeCHu9YGcOUddh+JrBXB36hZkM9pjkAv+EHsJen4lO?= =?us-ascii?Q?kkChQJuH4VfMV0nsD6clZ9runUCsNeDT2y7Ty0oNx0nBinZc10G9iHKKVQF/?= =?us-ascii?Q?B7Nu7pmID31q4ePqexG5nPinq4J281g3pxaROkgWfuE8jYSBWkraZBfnc85t?= =?us-ascii?Q?X2M7hHOP3Pqay5BZqL3PA0X+qpmfqu11oeWcu486dVymFkWDQMYS97N+yolP?= =?us-ascii?Q?sNfeOyeuPmXfph1xB++k9FCAIV8c0sA64XUoLazRpnTpfh8S6HWe+heJPaiU?= =?us-ascii?Q?Uzn/7/wJseUHMc4fKqnBcIV8LfbxVCCcfWPylWIdPNnOWc9b+8uBHgPr1ebn?= =?us-ascii?Q?BnfmGftTarRTLmTEGGalxyghZxF3wQ5FjJ091Dz2QYqIQMprvqwcKnQMGTjp?= =?us-ascii?Q?RkQ0xAl/JqBNFdFtxquoLWS1+gD6aGZliBDxP7QzJYt9LqSiQzTZ7Ij0430/?= =?us-ascii?Q?xm/v/atma2mgtjaSGnEcVoRjDSgQpB0ccjjwQ48gVuzZsOVRifi5xF9rTsW9?= =?us-ascii?Q?vAshZPWSvkqsJsYA/ue4JiZU258tVm8gRGh5gKJ2onXQW9YCxiH/U9IJ4P9a?= =?us-ascii?Q?FgtCxcOOTL7oLD2q974Scc4fF7rVm2EC0BoyVrgravNJXM+zRSTzv8RZXI7I?= =?us-ascii?Q?+den1vIT1IbGIT+Nk7pS4RoBLIX4xdBIn5fsfJVEGxzxhgP7uw98v4feXRkw?= =?us-ascii?Q?p5LL5Hx5VaUIDmdAgaXwuO35tHNUf1qxiCMxRDQTUP5z45SGOykKt4Ip+dVn?= =?us-ascii?Q?3VVb9bkV7UUq3v2haHHh8zNGcis2YKgxnS6Z9O1tZT163QZsLZIMVcs7JpCe?= =?us-ascii?Q?7MmIkwNJu1NK2Rm/ebiOoSQ28uj+TGl47mIDLq44m7g7crZgj5+8DEI/uzbW?= =?us-ascii?Q?AHGnt48C80jDYX2iw1EmVJDWcAqPGvVRgbabnbNBC8CInfXpZuca8avczvhS?= =?us-ascii?Q?0M7Bz0YDiOAbz7bXhTAVF5OMR6Zdwt7gCUQL?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 06:00:56.4136 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f6e9762d-fc4d-4ce6-4af8-08ddbf772300 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8423 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250709_230102_117309_FAACA6FC X-CRM114-Status: GOOD ( 14.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a new vEVENTQ type for VINTFs that are assigned to the user space. Simply report the two 64-bit LVCMDQ_ERR_MAPs register values. Reviewed-by: Alok Tiwari Reviewed-by: Pranjal Shrivastava Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- include/uapi/linux/iommufd.h | 15 +++++++++++++ .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 22 +++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 4e81610390c7..111ea81f91a2 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -1145,10 +1145,12 @@ struct iommufd_vevent_header { * enum iommu_veventq_type - Virtual Event Queue Type * @IOMMU_VEVENTQ_TYPE_DEFAULT: Reserved for future use * @IOMMU_VEVENTQ_TYPE_ARM_SMMUV3: ARM SMMUv3 Virtual Event Queue + * @IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV Extension IRQ */ enum iommu_veventq_type { IOMMU_VEVENTQ_TYPE_DEFAULT = 0, IOMMU_VEVENTQ_TYPE_ARM_SMMUV3 = 1, + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV = 2, }; /** @@ -1172,6 +1174,19 @@ struct iommu_vevent_arm_smmuv3 { __aligned_le64 evt[4]; }; +/** + * struct iommu_vevent_tegra241_cmdqv - Tegra241 CMDQV IRQ + * (IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV) + * @lvcmdq_err_map: 128-bit logical vcmdq error map, little-endian. + * (Refer to register LVCMDQ_ERR_MAPs per VINTF ) + * + * The 128-bit register value from HW exclusively reflect the error bits for a + * Virtual Interface represented by a vIOMMU object. Read and report directly. + */ +struct iommu_vevent_tegra241_cmdqv { + __aligned_le64 lvcmdq_err_map[2]; +}; + /** * struct iommu_veventq_alloc - ioctl(IOMMU_VEVENTQ_ALLOC) * @size: sizeof(struct iommu_veventq_alloc) diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c index 3eeb8444fadf..d5d43a1c7708 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -295,6 +295,20 @@ static inline int vcmdq_write_config(struct tegra241_vcmdq *vcmdq, u32 regval) /* ISR Functions */ +static void tegra241_vintf_user_handle_error(struct tegra241_vintf *vintf) +{ + struct iommufd_viommu *viommu = &vintf->vsmmu.core; + struct iommu_vevent_tegra241_cmdqv vevent_data; + int i; + + for (i = 0; i < LVCMDQ_ERR_MAP_NUM_64; i++) + vevent_data.lvcmdq_err_map[i] = + readq_relaxed(REG_VINTF(vintf, LVCMDQ_ERR_MAP_64(i))); + + iommufd_viommu_report_event(viommu, IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV, + &vevent_data, sizeof(vevent_data)); +} + static void tegra241_vintf0_handle_error(struct tegra241_vintf *vintf) { int i; @@ -340,6 +354,14 @@ static irqreturn_t tegra241_cmdqv_isr(int irq, void *devid) vintf_map &= ~BIT_ULL(0); } + /* Handle other user VINTFs and their LVCMDQs */ + while (vintf_map) { + unsigned long idx = __ffs64(vintf_map); + + tegra241_vintf_user_handle_error(cmdqv->vintfs[idx]); + vintf_map &= ~BIT_ULL(idx); + } + return IRQ_HANDLED; } -- 2.43.0