From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A10F5C433EF for ; Thu, 9 Jun 2022 05:04:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:To:Subject:MIME-Version: Date:Message-ID:Reply-To:Cc:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=LFTcLJxFdCp5h5reP6h/6rcayOsBLKeZSREL/t4M8oI=; b=CdDNRt2pqqXrWvRSkk1A2ZOkhP A+nse8VN6/jWXUtYeVsVhThDl4pbPfHbJZTEIc1cx9GZwVWPc60B6or6Mc5YCZJtEJJtSXrk1WYsd IjqbOxBbHIX4ut/vod3NtXaecHTJVgb9BK5srSIFdzDnAECLVoqdjJy29o9A48raG9EMO2iFwlkVl zBVem1avHjq0FdYG6lCN2w7A8R2AKPC9U1iDnHlZ+YOcnSZDlFswRb+tA/vurT0gAT8JmBB0xVHNR LASL0PHQ2sRaVCr52yCB0VGADANMkuUjTPsWiqsF72Q8cdPjbItCx6Yuw9FZpMoj7PHdKdc3K3NsY Gynysr/Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nzAJw-00GmhX-Hu; Thu, 09 Jun 2022 05:03:00 +0000 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nzAJs-00GmgK-AD for linux-arm-kernel@lists.infradead.org; Thu, 09 Jun 2022 05:02:58 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1654750976; x=1686286976; h=message-id:date:mime-version:subject:to:references:from: in-reply-to:content-transfer-encoding; bh=zXw+Mis03bohBkfK+hDhw/wFr5Kd1lzp07uRvIK3edI=; b=P1GJONz2K2EaOGT0cEUT4VWHgLrt2dzFE/o2OIXg5gwql6zku7N1ztqg DawpIxTrgAH4ph+nZQOgnRpSQMtNUSjX6h99k2RKFbSfjOH7iq+BUbCO4 lcpNi/29Na6wK3c2bzMjGUwOSp8P3VgWUmtZQkRWGPERXF3bLWFcnw5wZ U=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 08 Jun 2022 22:02:48 -0700 X-QCInternal: smtphost Received: from unknown (HELO nasanex01a.na.qualcomm.com) ([10.52.223.231]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2022 22:02:47 -0700 Received: from [10.242.59.11] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 8 Jun 2022 22:02:44 -0700 Message-ID: <6820a04b-16d2-3310-6491-835d8727edec@quicinc.com> Date: Thu, 9 Jun 2022 10:32:40 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.9.0 Subject: Re: [PATCH V5] arm64: perf: Make exporting of pmu events configurable Content-Language: en-US To: , , , , , , , , , , , References: <1653306574-20946-1-git-send-email-quic_c_spathi@quicinc.com> From: Srinivasarao Pathipati In-Reply-To: <1653306574-20946-1-git-send-email-quic_c_spathi@quicinc.com> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220608_220256_414394_5BC3BA3F X-CRM114-Status: GOOD ( 28.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Will / Robin , Could you please review this change. On 5/23/2022 5:19 PM, Srinivasarao Pathipati wrote: > The PMU export bit (PMCR_EL0.X) is getting reset during pmu reset, > Make is configurable using sysctls to enable/disable at runtime. > It can also be enabled at early bootup with kernel arguments. > > Signed-off-by: Srinivasarao Pathipati > --- > Changes since V4: > - Registering sysctls dynamically for only arm64 as suggested by Will > - Not removed the code to configure with kernel parameters > as the sysctl's kernel parameter(sysctl.kernel.export_pmu_events) > is not working at early bootup. pmu_reset() getting called before > sysctl's kernel parameter is set. > Changes since V3: > - export bit is now configurable with sysctl > - enabling export bit on reset instead of retaining > > Changes since V2: > Done below changes as per Will's comments > - enabling pmcr_x now configurable with kernel parameters and > by default it is disabled. > > Changes since V1: > - Preserving only PMCR_X bit as per Robin Murphy's comment. > > --- > Documentation/admin-guide/kernel-parameters.txt | 5 +++++ > Documentation/admin-guide/sysctl/kernel.rst | 9 +++++++++ > arch/arm64/kernel/perf_event.c | 24 ++++++++++++++++++++++++ > 3 files changed, 38 insertions(+) > > diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt > index de3da15..2bf1187 100644 > --- a/Documentation/admin-guide/kernel-parameters.txt > +++ b/Documentation/admin-guide/kernel-parameters.txt > @@ -5150,6 +5150,11 @@ > Useful for devices that are detected asynchronously > (e.g. USB and MMC devices). > > + export_pmu_events > + [KNL,ARM64] Sets the PMU export bit (PMCR_EL0.X), which enables > + the exporting of events over an IMPLEMENTATION DEFINED PMU event > + export bus to another device. > + > retain_initrd [RAM] Keep initrd memory after extraction > > rfkill.default_state= > diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst > index ddccd10..db42d4c 100644 > --- a/Documentation/admin-guide/sysctl/kernel.rst > +++ b/Documentation/admin-guide/sysctl/kernel.rst > @@ -892,6 +892,15 @@ The default value is 0 (access disabled). > > See Documentation/arm64/perf.rst for more information. > > +export_pmu_events (arm64 only) > +============================== > +Controls the PMU export bit (PMCR_EL0.X), which enables the exporting of > +events over an IMPLEMENTATION DEFINED PMU event export bus to another device. > + > +0: disables exporting of events (default). > + > +1: enables exporting of events. > + > > pid_max > ======= > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c > index cb69ff1..d93e7c4 100644 > --- a/arch/arm64/kernel/perf_event.c > +++ b/arch/arm64/kernel/perf_event.c > @@ -298,6 +298,7 @@ PMU_FORMAT_ATTR(long, "config1:0"); > PMU_FORMAT_ATTR(rdpmc, "config1:1"); > > static int sysctl_perf_user_access __read_mostly; > +static int sysctl_export_pmu_events __read_mostly; > > static inline bool armv8pmu_event_is_64bit(struct perf_event *event) > { > @@ -1025,6 +1026,17 @@ static int armv8pmu_filter_match(struct perf_event *event) > return evtype != ARMV8_PMUV3_PERFCTR_CHAIN; > } > > +static int __init export_pmu_events(char *str) > +{ > + /* Enable exporting of pmu events at early bootup with kernel > + * arguments. > + */ > + sysctl_export_pmu_events = 1; > + return 0; > +} > + > +early_param("export_pmu_events", export_pmu_events); > + > static void armv8pmu_reset(void *info) > { > struct arm_pmu *cpu_pmu = (struct arm_pmu *)info; > @@ -1047,6 +1059,9 @@ static void armv8pmu_reset(void *info) > if (armv8pmu_has_long_event(cpu_pmu)) > pmcr |= ARMV8_PMU_PMCR_LP; > > + if (sysctl_export_pmu_events) > + pmcr |= ARMV8_PMU_PMCR_X; > + > armv8pmu_pmcr_write(pmcr); > } > > @@ -1221,6 +1236,15 @@ static struct ctl_table armv8_pmu_sysctl_table[] = { > .extra1 = SYSCTL_ZERO, > .extra2 = SYSCTL_ONE, > }, > + { > + .procname = "export_pmu_events", > + .data = &sysctl_export_pmu_events, > + .maxlen = sizeof(unsigned int), > + .mode = 0644, > + .proc_handler = proc_dointvec_minmax, > + .extra1 = SYSCTL_ZERO, > + .extra2 = SYSCTL_ONE, > + }, > { } > }; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel