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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , Lorenzo Pieralisi , "linux-realtek-soc@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , Robin Murphy , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, Thanks for review. > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupts = , > > + , > > + , > > + ; > > Nit: At some point, it'd be good to be able to describe the EL2 virtual timer > interrupt too. Not specially important, but since these ARMv8.2 CPUs have it... I will add the EL2 virtual timer interrupt to timer node. > > + gic: interrupt-controller@ff100000 { > > + compatible = "arm,gic-v3"; > > + reg = <0xff100000 0x10000>, > > + <0xff140000 0xc0000>; > > Are you sure about the size of the GICR region? For 4 CPUs, it should be > 0x80000. Here, you have a range for 6 CPUs. The GICR region should be 0x80000 because the RTD1319 SoC have only 4 CPUs. Thank you. Regards, James _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel