From: Krzysztof Kozlowski <krzk@kernel.org>
To: Roy Luo <royluo@google.com>
Cc: "Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Peter Griffin" <peter.griffin@linaro.org>,
"André Draszik" <andre.draszik@linaro.org>,
"Tudor Ambarus" <tudor.ambarus@linaro.org>,
"Joy Chakraborty" <joychakr@google.com>,
"Naveen Kumar" <mnkumar@google.com>,
"Badhri Jagan Sridharan" <badhri@google.com>,
linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org
Subject: Re: [PATCH v4 1/2] dt-bindings: phy: google: Add Google Tensor G5 USB PHY
Date: Thu, 23 Oct 2025 08:57:55 +0200 [thread overview]
Message-ID: <698ba0ea-3367-4fc0-bd4f-0177283c2e77@kernel.org> (raw)
In-Reply-To: <20251023-collie-of-impossible-plenty-fc9382@kuoka>
On 23/10/2025 08:43, Krzysztof Kozlowski wrote:
> On Fri, Oct 17, 2025 at 11:51:58PM +0000, Roy Luo wrote:
>> Document the device tree bindings for the USB PHY interfaces integrated
>> with the DWC3 controller on Google Tensor SoCs, starting with G5
>> generation. The USB PHY on Tensor G5 includes two integrated Synopsys
>> PHY IPs: the eUSB 2.0 PHY IP and the USB 3.2/DisplayPort combo PHY IP.
>>
>> Due to a complete architectural overhaul in the Google Tensor G5, the
>> existing Samsung/Exynos USB PHY binding for older generations of Google
>> silicons such as gs101 are no longer compatible, necessitating this new
>> device tree binding.
>>
>> Signed-off-by: Roy Luo <royluo@google.com>
>> ---
>> .../bindings/phy/google,gs5-usb-phy.yaml | 104 ++++++++++++++++++
>> 1 file changed, 104 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml
>> new file mode 100644
>> index 000000000000..c92c20eba1ea
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/google,gs5-usb-phy.yaml
>> @@ -0,0 +1,104 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +# Copyright (C) 2025, Google LLC
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/google,gs5-usb-phy.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Google Tensor Series (G5+) USB PHY
>> +
>> +maintainers:
>> + - Roy Luo <royluo@google.com>
>> +
>> +description: |
>> + Describes the USB PHY interfaces integrated with the DWC3 USB controller on
>> + Google Tensor SoCs, starting with the G5 generation.
>> + Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PHY IP
>> + and USB 3.2/DisplayPort combo PHY IP.
>> + The hardware can support three PHY interfaces, which are selected using the
>> + first phandle argument in the PHY specifier::
>
> Just one ':', anyway this sentence and below does not belong to
> description but to phy-cells. You describe the cells.
>
> Or just mention the header with IDs - here or in phy-cells.
If you go with free-form text description in phy cells, then some
example could be:
renesas,rcar-gen2-usb-phy.yaml
For the header (in this case clocks):
display/msm/dsi-phy-common.yaml
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-10-23 6:58 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-17 23:51 [PATCH v4 0/2] Add Google Tensor SoC USB PHY support Roy Luo
2025-10-17 23:51 ` [PATCH v4 1/2] dt-bindings: phy: google: Add Google Tensor G5 USB PHY Roy Luo
2025-10-23 6:43 ` Krzysztof Kozlowski
2025-10-23 6:57 ` Krzysztof Kozlowski [this message]
2025-10-23 21:54 ` Roy Luo
2025-10-23 22:22 ` Roy Luo
2025-10-27 14:02 ` Krzysztof Kozlowski
2025-10-27 23:21 ` Roy Luo
2025-10-17 23:51 ` [PATCH v4 2/2] phy: Add Google Tensor SoC USB PHY driver Roy Luo
2025-10-18 8:13 ` Ivaylo Ivanov
2025-10-20 19:55 ` Roy Luo
2025-10-29 21:56 ` Roy Luo
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