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Tue, 7 Jul 2026 17:13:23 +0800 (CST) Received: from kwepemq100003.china.huawei.com (7.202.195.72) by dggemv705-chm.china.huawei.com (10.3.19.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 7 Jul 2026 17:13:23 +0800 Received: from [10.67.113.213] (10.67.113.213) by kwepemq100003.china.huawei.com (7.202.195.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 7 Jul 2026 17:13:22 +0800 Message-ID: <6A4CC332.3000906@hisilicon.com> Date: Tue, 7 Jul 2026 17:13:22 +0800 From: Wei Xu User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 MIME-Version: 1.0 To: Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Subject: Re: [PATCH] arm64: dts: hisilicon: Correct indentation References: <20260706093500.273922-2-krzysztof.kozlowski@oss.qualcomm.com> In-Reply-To: <20260706093500.273922-2-krzysztof.kozlowski@oss.qualcomm.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.113.213] X-ClientProxiedBy: kwepems100001.china.huawei.com (7.221.188.238) To kwepemq100003.china.huawei.com (7.202.195.72) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260707_021330_090131_78C12D02 X-CRM114-Status: GOOD ( 10.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Krzysztof, On 2026/7/6 17:35, Krzysztof Kozlowski wrote: > Correct spaces or mix of tabs+spaces into proper tab-indented lines. > No functional impact (same DTB). > > Signed-off-by: Krzysztof Kozlowski > --- > arch/arm64/boot/dts/hisilicon/hip05.dtsi | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi > index d0912ca5f237..2d376b3d30dd 100644 > --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi > @@ -236,13 +236,13 @@ cluster3_l2: l2-cache3 { > > gic: interrupt-controller@8d000000 { > compatible = "arm,gic-v3"; > - #interrupt-cells = <3>; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > - interrupt-controller; > - #redistributor-regions = <1>; > - redistributor-stride = <0x0 0x30000>; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + interrupt-controller; > + #redistributor-regions = <1>; > + redistributor-stride = <0x0 0x30000>; > reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ > <0x0 0x8d100000 0 0x300000>, /* GICR */ > <0x0 0xfe000000 0 0x10000>, /* GICC */ > Applied to the HiSilicon arm64 dt tree. Thanks! Best Regards, Wei