From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DEF5C77B7F for ; Thu, 29 Aug 2024 06:39:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:MIME-Version:Date:Message-ID:From:References:To: Subject:CC:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=lt9wseLob+kC09nOitNqYDE/ZS0sDhX/BAIHh/tRVLk=; b=w6hVGdYf2DQ0/5Jo65FFlk+sAA f8skzVwM8GwkLkbnNvSoIWX2EY62bedkQAKy94m9lTs0h5Q8XhE32xX1PhLiGE2N2DF/todTcymOP ncs0QDLbe9c9y8IfIkrNk74t20+W9VzECpKeabMtNapBbYBpWxot3plM99/APZPEkIUbEDW2A5Hyq iqw2AzkfnamDLG4E4odKIPyzY81i4Na6SYkqh8tE9dp90OT0pevUyEmlxSkRYVgDxKfLPeEaU8U/L IFtNadvU6ZC1Nq4TTKxc7JyJQ8auOdo8jRVemWHLbklsjvOELTMHXrn0j5PNefJqF25QuL83Dodb2 DbWl3jWw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sjYo6-00000000oKL-1nYY; Thu, 29 Aug 2024 06:38:58 +0000 Received: from szxga06-in.huawei.com ([45.249.212.32]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sjYfR-00000000mVe-40Fy for linux-arm-kernel@lists.infradead.org; Thu, 29 Aug 2024 06:30:04 +0000 Received: from mail.maildlp.com (unknown [172.19.88.214]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4WvWYP741Lz1xwXB; Thu, 29 Aug 2024 14:27:53 +0800 (CST) Received: from kwepemd200014.china.huawei.com (unknown [7.221.188.8]) by mail.maildlp.com (Postfix) with ESMTPS id 021551A016C; Thu, 29 Aug 2024 14:29:52 +0800 (CST) Received: from [10.67.121.177] (10.67.121.177) by kwepemd200014.china.huawei.com (7.221.188.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34; Thu, 29 Aug 2024 14:29:51 +0800 CC: , , , , , , , , , , , , , Subject: Re: [PATCH v2 1/2] arm64: Add support for FEAT_HAFT To: Will Deacon References: <20240814092333.7727-1-yangyicong@huawei.com> <20240814092333.7727-2-yangyicong@huawei.com> <20240820161822.GC28750@willie-the-truck> From: Yicong Yang Message-ID: <6a240d93-f818-c486-2603-05f651658277@huawei.com> Date: Thu, 29 Aug 2024 14:29:41 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.5.1 MIME-Version: 1.0 In-Reply-To: <20240820161822.GC28750@willie-the-truck> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.121.177] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemd200014.china.huawei.com (7.221.188.8) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240828_233002_814746_67A932DF X-CRM114-Status: GOOD ( 33.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2024/8/21 0:18, Will Deacon wrote: > On Wed, Aug 14, 2024 at 05:23:32PM +0800, Yicong Yang wrote: >> From: Yicong Yang >> >> Armv8.9/v9.4 introduces the feature Hardware managed Access Flag >> for Table descriptors (FEAT_HAFT). The feature is indicated by >> ID_AA64MMFR1_EL1.HAFDBS == 0b0011 and can be enabled by >> TCR2_EL1.HAFT so it has a dependency on FEAT_TCR2. >> >> This patch adds the Kconfig for FEAT_HAFT and support detecting >> and enabling the feature. >> >> Signed-off-by: Yicong Yang >> --- >> arch/arm64/Kconfig | 19 +++++++++++++++++++ >> arch/arm64/kernel/cpufeature.c | 26 ++++++++++++++++++++++++++ >> arch/arm64/tools/cpucaps | 1 + >> arch/arm64/tools/sysreg | 1 + >> 4 files changed, 47 insertions(+) >> >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index a2f8ff354ca6..869792458a23 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -2137,6 +2137,25 @@ config ARM64_EPAN >> if the cpu does not implement the feature. >> endmenu # "ARMv8.7 architectural features" >> >> +menu "ARMv8.9 architectural features" >> + >> +config ARM64_HAFT >> + bool "Support for Hardware managed Access Flag for Table Descriptor" >> + depends on ARM64_HW_AFDBM >> + default y >> + help >> + The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access >> + Flag for Table descriptors. When enabled an architectural executed >> + memory access will update the Access Flag in each Table descriptor >> + which is accessed during the translation table walk and for which >> + the Access Flag is 0. The Access Flag of the Table descriptor use >> + the same bit of PTE_AF. >> + >> + The feature will only be enabled if all the CPUs in the system >> + support this feature. If unsure, say Y. >> + >> +endmenu # "ARMv8.9 architectural features" >> + >> config ARM64_SVE >> bool "ARM Scalable Vector Extension support" >> default y >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index 646ecd3069fd..ed4c968be935 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -2044,6 +2044,17 @@ static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, >> >> #endif >> >> +#if CONFIG_ARM64_HAFT >> + >> +static void cpu_enable_haft(struct arm64_cpu_capabilities const *cap) >> +{ >> + sysreg_clear_set_s(SYS_TCR2_EL1, 0, TCR2_EL1x_HAFT); >> + isb(); >> + local_flush_tlb_all(); >> +} > > As this isn't a per-TTBR enable, should we be initialising the kernel > table entries in TTBR1 as YOUNG to avoid potential races with the > hardware update? It looks like the bit is ignored on CPUs without HAFT, > so we can just do this unconditionally. > I'm a bit uncertain about the race here, is it because of the access fault or the inconsistent observation of table entries' AF status when enable the HAFT? and... > At the very least, we should be able to enable HAFT in __cpu_setup(), > like we do for HA. > ...if we enable this in __cpu_setup() as suggested we should have no race problem, since this is enabled before MMU on? >> +#endif >> + >> #ifdef CONFIG_ARM64_AMU_EXTN >> >> /* >> @@ -2580,6 +2591,21 @@ static const struct arm64_cpu_capabilities arm64_features[] = { >> .cpus = &dbm_cpus, >> ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) >> }, >> +#endif >> +#ifdef CONFIG_ARM64_HAFT >> + { >> + .desc = "Hardware managed Access Flag for Table Descriptor", >> + /* >> + * Contrary to the page/block access flag, the table access flag >> + * cannot be emulated in software (no access fault will occur). >> + * Therefore mandate that all CPUs have FEAT_HAFT. >> + */ > > It's a bit of a pity that we can't handle this mismatch. After all, > access flag data is imprecise (unlike the dirty bit) and so you could > envisage a mechanism for falling back to leaf-level AF at runtime rather > than refusing to online a CPU. > ok. I suppose enable this should be ok if no users. So it's possible to just try to enable this at each CPU's startup, but don't advertise this feature to the upper users if not all the CPUs in the system support this. This won't affect leaf-level AF since leaf-level AF has its own detection and enabling and doesn't depend on HAFT. > Of course, it's hard to tell whether this really matters until we see > what people try to glue together. > > Will > . >