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[79.26.252.140]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cdce1a3fesm70391065e9.12.2026.09.01.06.11.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2026 06:11:21 -0700 (PDT) Message-ID: <6a96cef9.1f1211b9.23c693.9e1e@mx.google.com> X-Google-Original-Message-ID: Date: Tue, 1 Sep 2026 15:11:14 +0200 From: Christian Marangi To: Krzysztof Kozlowski Cc: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 1/2] dt-bindings: phy: airoha: Document support for AN7583 Gen3 PCIe PHY References: <20260827122127.18874-1-ansuelsmth@gmail.com> <20260827122127.18874-2-ansuelsmth@gmail.com> <20260831-elastic-turquoise-puma-f032fc@quoll> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260831-elastic-turquoise-puma-f032fc@quoll> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260901_061124_126871_C23F4401 X-CRM114-Status: GOOD ( 18.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Aug 31, 2026 at 08:51:46AM +0200, Krzysztof Kozlowski wrote: > On Thu, Aug 27, 2026 at 02:21:20PM +0200, Christian Marangi wrote: > > + > > +examples: > > + - | > > + #include > > + > > + phy@1fc7f000 { > > + compatible = "airoha,an7583-pcie-gen3-phy"; > > + reg = <0x1fc7f000 0xfff>, > > + <0x1fc7e000 0xfff>, > > Sashiko has a valid point here. > > This should reflect real hardware, not current driver. It is very, very > unlikely that hardware designers designed a block of 0xfff size or 0x4 > Hi for 0xfff yes the block is 0x1000 but I was reporting how it was defined in the original DTS. For the 0x4 is for real a single register for that usage. Documentation is scarce for that single block but this also reflect the same implementation used on EN7581. I updated the example to address the strange block of 0xfff. > > + <0x1fc30044 0x4>, > > + <0x1fc35030 0x4>; > -- Ansuel