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(93-34-90-148.ip49.fastwebnet.it. [93.34.90.148]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4b56f0237aesm3010995e9.9.2026.11.04.10.24.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 10:24:33 -0800 (PST) Message-ID: <6aeb7861.6171b307.11ae12.6b94@mx.google.com> X-Google-Original-Message-ID: Date: Wed, 4 Nov 2026 19:24:28 +0100 From: Christian Marangi To: Andrew Lunn Cc: Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , Joris Vaisvila , Ahmed Naseef , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: Re: [PATCH net-next v4 5/6] net: phy: mediatek: add calibration logic for AN7581 References: <20261103221439.30502-1-ansuelsmth@gmail.com> <20261103221439.30502-6-ansuelsmth@gmail.com> <2b744929-609b-4529-8b6b-30feb3ebbbde@lunn.ch> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2b744929-609b-4529-8b6b-30feb3ebbbde@lunn.ch> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261104_102436_425235_26B9D59F X-CRM114-Status: GOOD ( 19.73 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-2.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Wed, Nov 04, 2026 at 04:47:09AM +0100, Andrew Lunn wrote: > > +static int airoha_cal_cycle(struct phy_device *phydev, int devad, > > + u32 regnum, u16 mask, u16 cal_val) > > +{ > > + struct airoha_socphy_shared *shared = phy_package_get_priv(phydev); > > + struct phy_device *phydev_p0; > > + int ret; > > + > > + phydev_p0 = shared->phydev_p0; > > + > > + phy_modify_mmd(phydev, devad, regnum, mask, cal_val); > > + > > + ret = mtk_cal_cycle_wait(phydev_p0); > > + phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); > > What is the locking scheme here? > > When using PHY packages, the typical usage is: > > phy_lock_mdio_bus(phydev); > > and then use > > val = __phy_package_read(phydev, X, Y); > > All the read/write helpers are __ indicating they assume the bus is > locked. > > Here you are doing something similar, accessing another PHY in the > same package, but without locking. Is that safe? > Hi Andrew, thanks a lot for the review tag. It's safe in the measure that the worst is that link goes down during the calibration... I will rework the function to assign the base address to the default address for port 0 (it's hardcoded by the SoC) and use the lock and read/write helper instead. The main problem of using __phy_package_read is that I have to duplicate the mtk_cal_cycle_wait function in the airoha-ge-soc.c as it would use different helper... is it ok? -- Ansuel