From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1ED98C5B572 for ; Tue, 11 Aug 2026 14:26:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:MIME-Version: Content-Transfer-Encoding:Content-Type:In-Reply-To:From:References:Cc:To: Subject:Date:Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=2lIe5PD7kYFCQLG2Th1SAANT3Q3n6dwSXPufWFRYVC4=; b=cLQ1ej1XG1X+zam+Wgf8S2Sm/S oNSQw9Fx/ayJmGdZWq2Vxd3H2L50V3FnLnsUxjZKnhJhaqwnx1IqRInmIbdcKynXtfdaHV+mmuJU3 jqJ4TvRuI2m1KiDNP1SiOWghSYOTBveEN2piOymyL6QcI8hGwf5Id0LS5TL3ukX/QOloZpxRKg5vJ ECrSekP4k1edpMI623n7qdZnMitVRxNwgdqmA7KZgQmYx9lopZHWqdLMfxm0vHjcieyyNtuUgZ6GK 4Nxok9gFGU+muqSg6SA/GTOYndYmKNqbpIA93ZOPLouP/Zuih4dPP5NsuaTV4+FgfU8Y+Rz0ucCRm /ivNynAA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wtnQj-0000000EDLB-1TGC; Tue, 11 Aug 2026 14:26:15 +0000 Received: from mail-westusazlp170100001.outbound.protection.outlook.com ([2a01:111:f403:c000::1] helo=BYAPR05CU005.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wtnQg-0000000EDKm-0k9M for linux-arm-kernel@lists.infradead.org; Tue, 11 Aug 2026 14:26:11 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=nQ+O0raNhMJvxMXvTNfdQrHHX1/EZGJyOsuvYoZSDfi436iQRoZCifRpSNN7ENtLhp+pFfddaQOaBNG5gAQDsYzE7ZvWIMtp9BMAvxGLNpky+sEPDvQqnS+bOZB7FTCuPv2+AiqxCzj2Cy2FYvnyl8Dekf9yUqgCW2kbT8nhK/bWRFB4vjKai+GMFF/DHoal2rUtzvBsvS7bNpj9xObaSLi3ScbWfePUpB9vvnHYVe55NV0N5jw6iT/DynfiqcMgDqYkMZ2oGaFK3kQjR7A9MIHvea/5WBg9VAJpsNAeC9cqIPX6KGPK8JaZ1ks0h5ddWqDtSIFiBbhcceUIBbf4bA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=2lIe5PD7kYFCQLG2Th1SAANT3Q3n6dwSXPufWFRYVC4=; b=Mt5sASykltXMgu58ltznvFG8okNgYiDli6HSks//fZy6fH86+4cl30rF/N8DI5NJHZz0BwN2qT59fTEa38yRK/DB45VAV5zz2cQvN8jlmI/59fi5JEJ1BwIZ39fuwvHsF9X0mOD0ld+AOHsGDi+ozbcM2FK38s0A7i43US0U3y015S24wHnr/hb3ZM2cBCOro7bYgOqn1YOvbOHha0hZJ6+PrUYRcGHmvO/od5d8y28ZNqn28Yc8+dFrMR2mBLaVbEgJOaPPULDRmcVl3oy3Nn5ThLvNyjDkptKAukfuwrvalUGIGp2Kr7JIR8cFXAd4N8tJGWO0qDNt+x/HJeh7/g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2lIe5PD7kYFCQLG2Th1SAANT3Q3n6dwSXPufWFRYVC4=; b=WBpzkKm2BWGiz74rRlo/0Iv6wIhUlMXovYlxXfll/eRwNkTk+3uWNyUYzaHi/kM9cIF0rC1moE++IivkofTCDMY8drtJN1knFrqNgdx+qVyhsD9p5lpkVC5+45BGUR5wI6T25irIGDYKWejYG/8axtSsniiY2iibn/SaF9g1T20= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from DS0PR12MB9060.namprd12.prod.outlook.com (2603:10b6:8:c4::12) by DS0PR12MB7851.namprd12.prod.outlook.com (2603:10b6:8:14a::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.315.11; Tue, 11 Aug 2026 14:25:55 +0000 Received: from DS0PR12MB9060.namprd12.prod.outlook.com ([fe80::e096:864d:d60a:c83f]) by DS0PR12MB9060.namprd12.prod.outlook.com ([fe80::e096:864d:d60a:c83f%4]) with mapi id 15.21.0292.024; Tue, 11 Aug 2026 14:25:55 +0000 Message-ID: <6cf0791d-902d-4a89-bb57-d4c607991579@amd.com> Date: Tue, 11 Aug 2026 19:55:48 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] firmware: xilinx: ufs: move PHY/SRAM ready polling into the firmware backend To: Michal Simek , linux-kernel@vger.kernel.org, monstr@monstr.eu, git@amd.com Cc: Ajay Neeli , "James E.J. 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Each iteration is a full firmware round-trip > (PM_IOCTL/IOCTL_READ_REG of a protected PMC_IOU_SLCR register), so the > loop can issue up to a million EEMI calls, and it hard-codes the wait > policy inside the controller driver. > > Introduce coarse blocking helpers, zynqmp_pm_wait_mphy_tx_rx_config_ready() > and zynqmp_pm_wait_sram_init_done(), that take a caller-supplied timeout > budget and contain the poll loop. The loop is EEMI-specific (legacy > firmware only exposes the per-read status primitive) so it lives in the > firmware driver, keeping the UFS driver backend-agnostic: a future > backend can offload the wait to the platform in a single call without > touching the controller driver again. The existing per-read primitives stay > exported, so the current EEMI interface is unchanged. > > The timeout budget remains owned by the UFS driver (the consumer that > knows the hardware) and is passed down, so EEMI and any future backend > stay consistent. > > Signed-off-by: Michal Simek Reviewed-by: Sai Krishna Potthuri Regards Sai Krishna > --- > > drivers/firmware/xilinx/zynqmp-ufs.c | 70 ++++++++++++++++++++++-- > drivers/ufs/host/ufs-amd-versal2.c | 46 ++++------------ > include/linux/firmware/xlnx-zynqmp-ufs.h | 8 +-- > 3 files changed, 82 insertions(+), 42 deletions(-) > > diff --git a/drivers/firmware/xilinx/zynqmp-ufs.c b/drivers/firmware/xilinx/zynqmp-ufs.c > index 85da8a822f3a..81ccf61a037c 100644 > --- a/drivers/firmware/xilinx/zynqmp-ufs.c > +++ b/drivers/firmware/xilinx/zynqmp-ufs.c > @@ -5,6 +5,7 @@ > * Copyright (C) 2025 Advanced Micro Devices, Inc. > */ > > +#include > #include > #include > > @@ -33,7 +34,7 @@ > * > * Return: Returns 0 on success or error value on failure. > */ > -int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready) > +static int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready) > { > u32 regval; > int ret; > @@ -53,7 +54,6 @@ int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready) > > return ret; > } > -EXPORT_SYMBOL_GPL(zynqmp_pm_is_mphy_tx_rx_config_ready); > > /** > * zynqmp_pm_is_sram_init_done - check SRAM initialization > @@ -61,7 +61,7 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_is_mphy_tx_rx_config_ready); > * > * Return: Returns 0 on success or error value on failure. > */ > -int zynqmp_pm_is_sram_init_done(bool *is_done) > +static int zynqmp_pm_is_sram_init_done(bool *is_done) > { > u32 regval; > int ret; > @@ -81,7 +81,69 @@ int zynqmp_pm_is_sram_init_done(bool *is_done) > > return ret; > } > -EXPORT_SYMBOL_GPL(zynqmp_pm_is_sram_init_done); > + > +/** > + * zynqmp_pm_wait_mphy_tx_rx_config_ready - wait for M-PHY TX-RX config ready > + * @timeout_us: Caller-supplied timeout budget in microseconds > + * > + * Poll the M-PHY TX-RX configuration-ready status until it settles or the > + * timeout elapses. The poll loop is EEMI-specific (legacy firmware only offers > + * the per-read status primitive), so it lives here in the firmware driver > + * rather than in the UFS controller driver; an SCMI-based backend can instead > + * offload the wait to the platform in a single call. The timeout budget is > + * owned by the caller (UFS driver), keeping the policy with the consumer. > + * > + * Return: Returns 0 once ready, -ETIMEDOUT on timeout, or error value. > + */ > +int zynqmp_pm_wait_mphy_tx_rx_config_ready(u32 timeout_us) > +{ > + bool is_ready; > + int ret; > + > + while (timeout_us--) { > + ret = zynqmp_pm_is_mphy_tx_rx_config_ready(&is_ready); > + if (ret) > + return ret; > + > + if (!is_ready) > + return 0; > + > + usleep_range(1, 5); > + } > + > + return -ETIMEDOUT; > +} > +EXPORT_SYMBOL_GPL(zynqmp_pm_wait_mphy_tx_rx_config_ready); > + > +/** > + * zynqmp_pm_wait_sram_init_done - wait for SRAM initialization to complete > + * @timeout_us: Caller-supplied timeout budget in microseconds > + * > + * Poll the SRAM initialization-done status until it is set or the timeout > + * elapses. As with the M-PHY wait, the poll loop is EEMI-specific and kept in > + * the firmware driver so the UFS controller driver stays backend-agnostic. > + * > + * Return: Returns 0 once done, -ETIMEDOUT on timeout, or error value. > + */ > +int zynqmp_pm_wait_sram_init_done(u32 timeout_us) > +{ > + bool is_done; > + int ret; > + > + while (timeout_us--) { > + ret = zynqmp_pm_is_sram_init_done(&is_done); > + if (ret) > + return ret; > + > + if (is_done) > + return 0; > + > + usleep_range(1, 5); > + } > + > + return -ETIMEDOUT; > +} > +EXPORT_SYMBOL_GPL(zynqmp_pm_wait_sram_init_done); > > /** > * zynqmp_pm_set_sram_bypass - Set SRAM bypass Control > diff --git a/drivers/ufs/host/ufs-amd-versal2.c b/drivers/ufs/host/ufs-amd-versal2.c > index 2154d6286817..dff0c2c95486 100644 > --- a/drivers/ufs/host/ufs-amd-versal2.c > +++ b/drivers/ufs/host/ufs-amd-versal2.c > @@ -225,8 +225,6 @@ static int ufs_versal2_setup_phy(struct ufs_hba *hba) > static int ufs_versal2_phy_init(struct ufs_hba *hba) > { > struct ufs_versal2_host *host = ufshcd_get_variant(hba); > - u32 time_left; > - bool is_ready; > int ret; > static const struct ufshcd_dme_attr_val rmmi_attrs[] = { > { UIC_ARG_MIB(CBREFCLKCTRL2), CBREFREFCLK_GATE_OVR_EN, DME_LOCAL }, > @@ -235,23 +233,15 @@ static int ufs_versal2_phy_init(struct ufs_hba *hba) > { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } > }; > > - /* Wait for Tx/Rx config_rdy */ > - time_left = TIMEOUT_MICROSEC; > - do { > - time_left--; > - ret = zynqmp_pm_is_mphy_tx_rx_config_ready(&is_ready); > - if (ret) > - return ret; > - > - if (!is_ready) > - break; > - > - usleep_range(1, 5); > - } while (time_left); > - > - if (!time_left) { > + /* > + * Wait for Tx/Rx config_rdy. The poll loop lives in the firmware > + * backend (EEMI today, SCMI in future) so this driver stays > + * backend-agnostic; the timeout budget stays here with the consumer. > + */ > + ret = zynqmp_pm_wait_mphy_tx_rx_config_ready(TIMEOUT_MICROSEC); > + if (ret) { > dev_err(hba->dev, "Tx/Rx configuration signal busy.\n"); > - return -ETIMEDOUT; > + return ret; > } > > ret = ufshcd_dwc_dme_set_attrs(hba, rmmi_attrs, ARRAY_SIZE(rmmi_attrs)); > @@ -264,23 +254,11 @@ static int ufs_versal2_phy_init(struct ufs_hba *hba) > return ret; > } > > - /* Wait for SRAM init done */ > - time_left = TIMEOUT_MICROSEC; > - do { > - time_left--; > - ret = zynqmp_pm_is_sram_init_done(&is_ready); > - if (ret) > - return ret; > - > - if (is_ready) > - break; > - > - usleep_range(1, 5); > - } while (time_left); > - > - if (!time_left) { > + /* Wait for SRAM init done (poll handled by the firmware backend). */ > + ret = zynqmp_pm_wait_sram_init_done(TIMEOUT_MICROSEC); > + if (ret) { > dev_err(hba->dev, "SRAM initialization failed.\n"); > - return -ETIMEDOUT; > + return ret; > } > > ret = ufs_versal2_setup_phy(hba); > diff --git a/include/linux/firmware/xlnx-zynqmp-ufs.h b/include/linux/firmware/xlnx-zynqmp-ufs.h > index d3538dd5822a..00383dd835f2 100644 > --- a/include/linux/firmware/xlnx-zynqmp-ufs.h > +++ b/include/linux/firmware/xlnx-zynqmp-ufs.h > @@ -9,17 +9,17 @@ > #define __FIRMWARE_XLNX_ZYNQMP_UFS_H__ > > #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE) > -int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready); > -int zynqmp_pm_is_sram_init_done(bool *is_done); > +int zynqmp_pm_wait_mphy_tx_rx_config_ready(u32 timeout_us); > +int zynqmp_pm_wait_sram_init_done(u32 timeout_us); > int zynqmp_pm_set_sram_bypass(void); > int zynqmp_pm_get_ufs_calibration_values(u32 *val); > #else > -static inline int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready) > +static inline int zynqmp_pm_wait_mphy_tx_rx_config_ready(u32 timeout_us) > { > return -ENODEV; > } > > -static inline int zynqmp_pm_is_sram_init_done(bool *is_done) > +static inline int zynqmp_pm_wait_sram_init_done(u32 timeout_us) > { > return -ENODEV; > } > --- > base-commit: 848acc8ffe1b7cd5f1bf427b93069becfebc2c9d > branch: xnext/ufs >