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Mon, 17 Nov 2025 18:05:01 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface MIME-Version: 1.0 X-ThreadId: A5NgtTiaP10B Date: Tue, 18 Nov 2025 00:04:40 +0100 From: "Arnd Bergmann" To: "Mark Rutland" Cc: "Ryan Roberts" , "Kees Cook" , "Ard Biesheuvel" , "Jeremy Linton" , "Will Deacon" , "Catalin Marinas" , "linux-arm-kernel@lists.infradead.org" , "Linux Kernel Mailing List" , "Jason A . Donenfeld" Message-Id: <6e868400-5fd7-4239-95c9-7cb6ea6269b5@app.fastmail.com> In-Reply-To: References: <66c4e2a0-c7fb-46c2-acce-8a040a71cd8e@arm.com> Subject: Re: [DISCUSSION] kstack offset randomization: bugs and performance Content-Type: text/plain Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251117_150504_255182_1257E4B3 X-CRM114-Status: GOOD ( 15.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Nov 17, 2025, at 18:46, Mark Rutland wrote: > On Mon, Nov 17, 2025 at 05:47:05PM +0100, Arnd Bergmann wrote: >> As I understand, the other architectures already just use the cycle counter >> because that is random enough, but for arm64 the cntvct runs on an >> unspecified frequency that is often too low. >> >> However, most future machines are ARMv9.1 or higher and require a 1GHz >> timer frequency. I also checked Graviton-3 (Neoverse-V1, ARMv8.4), which >> is running its timer at 1.05GHz. > > Note that 1GHz requirement is for the *effective frequency*, not the > underlying counter resolution. The 1GHz requirement means that the > counter must increment by 10^9 per second, but it doesn't mean that it > actually increments by 1 every 1 ns. > > See ARM DDI 0487 L.b, page D12-6793, which says: > > | Counter resolution > | > | The counter resolution is a representation of how frequently the > | counter is updated. > | > | For example, a counter might have an effective frequency of 1GHz, but > | the actual clock runs at 125MHz and therefore the counter resolution > | is 125Mhz. > | > | From Armv8.6, Arm recommends the counter resolution is not less than > | 50MHz in normal running operation. > > ... and note that (unfortunately) that latter point is a recommendation, > not a requirement. Right, I see. As far as I can tell, the actual resolution on s390, x86 and powerpc is also lower than the effective frequency, but it does indeed seem to be sufficiently higher than this so it's usually above six bits of entropy there per syscall there. Arnd