Re: [PATCH 1/3] KVM: arm64: Stop writing aarch32's CSSELR into ACTLR

[Marc Zyngier <maz@kernel.org>]

On 2020-05-28 12:59, James Morse wrote:
> Hi Marc,
> 
> On 28/05/2020 09:57, Marc Zyngier wrote:
>> On 2020-05-26 17:18, James Morse wrote:
>>> access_csselr() uses the 32bit r->reg value to access the 64bit 
>>> array,
>>> so reads and write the wrong value. sys_regs[4], is ACTLR_EL1, which
>>> is subsequently save/restored when we enter the guest.
> 
>>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>>> index 51db934702b6..2eda539f3281 100644
>>> --- a/arch/arm64/kvm/sys_regs.c
>>> +++ b/arch/arm64/kvm/sys_regs.c
>>> @@ -2060,7 +2060,7 @@ static const struct sys_reg_desc cp15_regs[] = 
>>> {
>>> 
>>>      { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
>>>      { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
>>> -    { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, 
>>> c0_CSSELR },
>>> +    { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr_el1, NULL, 
>>> CSSELR_EL1 },
>>>  };
> 
>> This is a departure from the way we deal with 32bit CP15 registers.
>> We deal with this exact issue in a very different way for other
>> CP15 regs, by adjusting the index in the sys_regs array (see the
>> way we handle the VM regs).
>> 
>> How about something like this (untested):
> 
> [like access_vm_reg() does]
> 
> Sure, I'll give that a test and re-post it.

Thanks!

> 
> 
>> Ideally, I'd like the core sys_reg code to deal with this sort
>> of funnies, but I'm trying to keep the change minimal...
> 
> Roll this '/2' and upper/lower bits stuff into a vcpu_write_cp15_reg()
> that calls
> vcpu_write_sys_reg()? (/me hunts out the todo list)

I was thinking of hiding it differently: in emulate_cp, substitute the
sys_reg_desc structure for a temporary one that represents the 64bit
version, and make it completely transparent.

I'm sure there is a couple of nits around that though...

         M.
-- 
Jazz is not dead. It just smells funny...

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