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Wed, 12 Feb 2025 01:26:32 -0800 (PST) Received: from giga-mm.home ([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5de5ced9758sm8064096a12.76.2025.02.12.01.26.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2025 01:26:32 -0800 (PST) Message-ID: <708cdc497b8474609989395dbf8a0898037a22de.camel@gmail.com> Subject: Re: [PATCH v2 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files From: Alexander Sverdlin To: Inochi Amaoto , soc@lists.linux.dev Cc: Chen Wang , Inochi Amaoto , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Arnd Bergmann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Chao Wei Date: Wed, 12 Feb 2025 10:26:28 +0100 In-Reply-To: References: <20250210220951.1248533-1-alexander.sverdlin@gmail.com> <20250210220951.1248533-2-alexander.sverdlin@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250212_012635_145718_0F39F669 X-CRM114-Status: GOOD ( 23.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Inochi, Krzysztof, On Wed, 2025-02-12 at 08:31 +0800, Inochi Amaoto wrote: > On Mon, Feb 10, 2025 at 11:09:41PM +0100, Alexander Sverdlin wrote: > > Make the peripheral device tree re-usable on ARM64 platform by moving C= PU > > core and interrupt controllers' parts into the respective per-SoC .dtsi > > files. > >=20 > > Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nuberin= g > > into "plic" interrupt-controller numbering. > >=20 > > Have a nice refactoring side-effect that "plic" and "clint" "compatible= " > > property is not specified outside of the corresponding device itself. > >=20 > > Signed-off-by: Alexander Sverdlin > > --- > > Changelog: > > v2: > > - instead of carving out peripherals' part, carve out ARCH-specifics (C= PU > > core, interrupt controllers) and spread them among 3 SoC .dtsi files wh= ich > > included cv18xx.dtsi; > > - define a label for the "soc" node and use it in the newly introduced = DTs; > >=20 > > =C2=A0arch/riscv/boot/dts/sophgo/cv1800b.dtsi=C2=A0=C2=A0=C2=A0 | 64 ++= ++++++++++--- > > =C2=A0arch/riscv/boot/dts/sophgo/cv1812h.dtsi=C2=A0=C2=A0=C2=A0 | 64 ++= ++++++++++--- > > =C2=A0arch/riscv/boot/dts/sophgo/cv181x.dtsi=C2=A0=C2=A0=C2=A0=C2=A0 |= =C2=A0 2 +- > > =C2=A0arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi | 57 ++++++++++++++ > > =C2=A0arch/riscv/boot/dts/sophgo/cv18xx.dtsi=C2=A0=C2=A0=C2=A0=C2=A0 | = 91 ++++++---------------- > > =C2=A0arch/riscv/boot/dts/sophgo/sg2002.dtsi=C2=A0=C2=A0=C2=A0=C2=A0 | = 64 ++++++++++++--- > > =C2=A06 files changed, 240 insertions(+), 102 deletions(-) > > =C2=A0create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi > >=20 > > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/= dts/sophgo/cv1800b.dtsi > > index aa1f5df100f0..eef2884b36f9 100644 > > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > > @@ -3,6 +3,8 @@ > > =C2=A0 * Copyright (C) 2023 Jisheng Zhang > > =C2=A0 */ > > =C2=A0 > > +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) > > + > > =C2=A0#include > > =C2=A0#include "cv18xx.dtsi" > > =C2=A0 > > @@ -14,22 +16,62 @@ memory@80000000 { > > =C2=A0 reg =3D <0x80000000 0x4000000>; > > =C2=A0 }; > > =C2=A0 >=20 > > - soc { > > - pinctrl: pinctrl@3001000 { > > - compatible =3D "sophgo,cv1800b-pinctrl"; > > - reg =3D <0x03001000 0x1000>, > > - =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0x05027000 0x1000>; > > - reg-names =3D "sys", "rtc"; >=20 >=20 > > + cpus: cpus { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + timebase-frequency =3D <25000000>; > > + > > + cpu0: cpu@0 { > > + compatible =3D "thead,c906", "riscv"; > > + device_type =3D "cpu"; > > + reg =3D <0>; > > + d-cache-block-size =3D <64>; > > + d-cache-sets =3D <512>; > > + d-cache-size =3D <65536>; > > + i-cache-block-size =3D <64>; > > + i-cache-sets =3D <128>; > > + i-cache-size =3D <32768>; > > + mmu-type =3D "riscv,sv39"; > > + riscv,isa =3D "rv64imafdc"; > > + riscv,isa-base =3D "rv64i"; > > + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "z= icsr", > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "zifencei", "zihpm"; > > + > > + cpu0_intc: interrupt-controller { > > + compatible =3D "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells =3D <1>; > > + }; > > =C2=A0 }; > > =C2=A0 }; > > =C2=A0}; >=20 > Make all soc definition include the common cpu file.=20 > Not just copy it. I was acting according to Krzysztof's suggestion: https://lore.kernel.org/soc/d3ba0ea5-0491-42d5-a18e-64cf21df696c@kernel.org= / Krzysztof, I can name the file cv18xx-cpu-intc.dtsi and pack CPU core + int= errupt controllers into it. Would it make sense? > > =C2=A0 > > -&plic { > > - compatible =3D "sophgo,cv1800b-plic", "thead,c900-plic"; > > -}; > > +&soc { > > + interrupt-parent =3D <&plic>; > > + dma-noncoherent; > > =C2=A0 > > -&clint { > > - compatible =3D "sophgo,cv1800b-clint", "thead,c900-clint"; > > + pinctrl: pinctrl@3001000 { > > + compatible =3D "sophgo,cv1800b-pinctrl"; > > + reg =3D <0x03001000 0x1000>, > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0x05027000 0x1000>; > > + reg-names =3D "sys", "rtc"; > > + }; > > + > > + plic: interrupt-controller@70000000 { > > + compatible =3D "sophgo,cv1800b-plic", "thead,c900-plic"; > > + reg =3D <0x70000000 0x4000000>; > > + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; > > + interrupt-controller; > > + #address-cells =3D <0>; > > + #interrupt-cells =3D <2>; > > + riscv,ndev =3D <101>; > > + }; > > + > > + clint: timer@74000000 { > > + compatible =3D "sophgo,cv1800b-clint", "thead,c900-clint"; > > + reg =3D <0x74000000 0x10000>; > > + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; > > + }; > > =C2=A0}; > > =C2=A0 > > =C2=A0&clk { > > diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/= dts/sophgo/cv1812h.dtsi > > index 8a1b95c5116b..54f7e229bcd8 100644 > > --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > > +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi > > @@ -3,6 +3,8 @@ > > =C2=A0 * Copyright (C) 2023 Inochi Amaoto > > =C2=A0 */ > > =C2=A0 > > +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) > > + > > =C2=A0#include > > =C2=A0#include > > =C2=A0#include "cv18xx.dtsi" > > @@ -16,22 +18,62 @@ memory@80000000 { > > =C2=A0 reg =3D <0x80000000 0x10000000>; > > =C2=A0 }; > > =C2=A0 > > - soc { > > - pinctrl: pinctrl@3001000 { > > - compatible =3D "sophgo,cv1812h-pinctrl"; > > - reg =3D <0x03001000 0x1000>, > > - =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0x05027000 0x1000>; > > - reg-names =3D "sys", "rtc"; > > + cpus: cpus { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + timebase-frequency =3D <25000000>; > > + > > + cpu0: cpu@0 { > > + compatible =3D "thead,c906", "riscv"; > > + device_type =3D "cpu"; > > + reg =3D <0>; > > + d-cache-block-size =3D <64>; > > + d-cache-sets =3D <512>; > > + d-cache-size =3D <65536>; > > + i-cache-block-size =3D <64>; > > + i-cache-sets =3D <128>; > > + i-cache-size =3D <32768>; > > + mmu-type =3D "riscv,sv39"; > > + riscv,isa =3D "rv64imafdc"; > > + riscv,isa-base =3D "rv64i"; > > + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "z= icsr", > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "zifencei", "zihpm"; > > + > > + cpu0_intc: interrupt-controller { > > + compatible =3D "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells =3D <1>; > > + }; > > =C2=A0 }; > > =C2=A0 }; > > =C2=A0}; > > =C2=A0 > > -&plic { > > - compatible =3D "sophgo,cv1812h-plic", "thead,c900-plic"; > > -}; > > +&soc { > > + interrupt-parent =3D <&plic>; > > + dma-noncoherent; > > =C2=A0 > > -&clint { > > - compatible =3D "sophgo,cv1812h-clint", "thead,c900-clint"; > > + pinctrl: pinctrl@3001000 { > > + compatible =3D "sophgo,cv1812h-pinctrl"; > > + reg =3D <0x03001000 0x1000>, > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0x05027000 0x1000>; > > + reg-names =3D "sys", "rtc"; > > + }; > > + > > + plic: interrupt-controller@70000000 { > > + compatible =3D "sophgo,cv1812h-plic", "thead,c900-plic"; > > + reg =3D <0x70000000 0x4000000>; > > + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; > > + interrupt-controller; > > + #address-cells =3D <0>; > > + #interrupt-cells =3D <2>; > > + riscv,ndev =3D <101>; > > + }; > > + > > + clint: timer@74000000 { > > + compatible =3D "sophgo,cv1812h-clint", "thead,c900-clint"; > > + reg =3D <0x74000000 0x10000>; > > + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; > > + }; > > =C2=A0}; > > =C2=A0 > > =C2=A0&clk { > > diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/d= ts/sophgo/cv181x.dtsi > > index 5fd14dd1b14f..bbdb30653e9a 100644 > > --- a/arch/riscv/boot/dts/sophgo/cv181x.dtsi > > +++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi > > @@ -11,7 +11,7 @@ soc { > > =C2=A0 emmc: mmc@4300000 { > > =C2=A0 compatible =3D "sophgo,cv1800b-dwcmshc"; > > =C2=A0 reg =3D <0x4300000 0x1000>; > > - interrupts =3D <34 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 clocks =3D <&clk CLK_AXI4_EMMC>, > > =C2=A0 <&clk CLK_EMMC>; > > =C2=A0 clock-names =3D "core", "bus"; > > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi b/arch/riscv/bo= ot/dts/sophgo/cv18xx-cpu.dtsi > > new file mode 100644 > > index 000000000000..a68d61131efb > > --- /dev/null > > +++ b/arch/riscv/boot/dts/sophgo/cv18xx-cpu.dtsi > > @@ -0,0 +1,57 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* > > + * Copyright (C) 2023 Jisheng Zhang > > + * Copyright (C) 2023 Inochi Amaoto > > + */ > > + > > +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) > > + > > +/ { > > + cpus: cpus { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + timebase-frequency =3D <25000000>; > > + > > + cpu0: cpu@0 { > > + compatible =3D "thead,c906", "riscv"; > > + device_type =3D "cpu"; > > + reg =3D <0>; > > + d-cache-block-size =3D <64>; > > + d-cache-sets =3D <512>; > > + d-cache-size =3D <65536>; > > + i-cache-block-size =3D <64>; > > + i-cache-sets =3D <128>; > > + i-cache-size =3D <32768>; > > + mmu-type =3D "riscv,sv39"; > > + riscv,isa =3D "rv64imafdc"; > > + riscv,isa-base =3D "rv64i"; > > + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "z= icsr", > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "zifencei", "zihpm"; > > + > > + cpu0_intc: interrupt-controller { > > + compatible =3D "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells =3D <1>; > > + }; > > + }; > > + }; > > +}; > > + > > +&soc { > > + interrupt-parent =3D <&plic>; > > + dma-noncoherent; > > + > > + plic: interrupt-controller@70000000 { > > + reg =3D <0x70000000 0x4000000>; > > + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; > > + interrupt-controller; > > + #address-cells =3D <0>; > > + #interrupt-cells =3D <2>; > > + riscv,ndev =3D <101>; > > + }; > > + > > + clint: timer@74000000 { > > + reg =3D <0x74000000 0x10000>; > > + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; > > + }; > > +}; > > diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/d= ts/sophgo/cv18xx.dtsi > > index c18822ec849f..62c1464a0490 100644 > > --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > > +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > > @@ -12,47 +12,16 @@ / { > > =C2=A0 #address-cells =3D <1>; > > =C2=A0 #size-cells =3D <1>; > > =C2=A0 > > - cpus: cpus { > > - #address-cells =3D <1>; > > - #size-cells =3D <0>; > > - timebase-frequency =3D <25000000>; > > - > > - cpu0: cpu@0 { > > - compatible =3D "thead,c906", "riscv"; > > - device_type =3D "cpu"; > > - reg =3D <0>; > > - d-cache-block-size =3D <64>; > > - d-cache-sets =3D <512>; > > - d-cache-size =3D <65536>; > > - i-cache-block-size =3D <64>; > > - i-cache-sets =3D <128>; > > - i-cache-size =3D <32768>; > > - mmu-type =3D "riscv,sv39"; > > - riscv,isa =3D "rv64imafdc"; > > - riscv,isa-base =3D "rv64i"; > > - riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "z= icsr", > > - =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "zifencei", "zihpm"; > > - > > - cpu0_intc: interrupt-controller { > > - compatible =3D "riscv,cpu-intc"; > > - interrupt-controller; > > - #interrupt-cells =3D <1>; > > - }; > > - }; > > - }; > > - > > =C2=A0 osc: oscillator { > > =C2=A0 compatible =3D "fixed-clock"; > > =C2=A0 clock-output-names =3D "osc_25m"; > > =C2=A0 #clock-cells =3D <0>; > > =C2=A0 }; > > =C2=A0 > > - soc { > > + soc: soc { > > =C2=A0 compatible =3D "simple-bus"; > > - interrupt-parent =3D <&plic>; > > =C2=A0 #address-cells =3D <1>; > > =C2=A0 #size-cells =3D <1>; > > - dma-noncoherent; > > =C2=A0 ranges; > > =C2=A0 > > =C2=A0 clk: clock-controller@3002000 { > > @@ -75,7 +44,7 @@ porta: gpio-controller@0 { > > =C2=A0 reg =3D <0>; > > =C2=A0 interrupt-controller; > > =C2=A0 #interrupt-cells =3D <2>; > > - interrupts =3D <60 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 }; > > =C2=A0 }; > > =C2=A0 > > @@ -93,7 +62,7 @@ portb: gpio-controller@0 { > > =C2=A0 reg =3D <0>; > > =C2=A0 interrupt-controller; > > =C2=A0 #interrupt-cells =3D <2>; > > - interrupts =3D <61 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 }; > > =C2=A0 }; > > =C2=A0 > > @@ -111,7 +80,7 @@ portc: gpio-controller@0 { > > =C2=A0 reg =3D <0>; > > =C2=A0 interrupt-controller; > > =C2=A0 #interrupt-cells =3D <2>; > > - interrupts =3D <62 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 }; > > =C2=A0 }; > > =C2=A0 > > @@ -129,7 +98,7 @@ portd: gpio-controller@0 { > > =C2=A0 reg =3D <0>; > > =C2=A0 interrupt-controller; > > =C2=A0 #interrupt-cells =3D <2>; > > - interrupts =3D <63 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 }; > > =C2=A0 }; > > =C2=A0 > > @@ -137,7 +106,7 @@ saradc: adc@30f0000 { > > =C2=A0 compatible =3D "sophgo,cv1800b-saradc"; > > =C2=A0 reg =3D <0x030f0000 0x1000>; > > =C2=A0 clocks =3D <&clk CLK_SARADC>; > > - interrupts =3D <100 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 #address-cells =3D <1>; > > =C2=A0 #size-cells =3D <0>; > > =C2=A0 status =3D "disabled"; > > @@ -162,7 +131,7 @@ i2c0: i2c@4000000 { > > =C2=A0 #size-cells =3D <0>; > > =C2=A0 clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; > > =C2=A0 clock-names =3D "ref", "pclk"; > > - interrupts =3D <49 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 status =3D "disabled"; > > =C2=A0 }; > > =C2=A0 > > @@ -173,7 +142,7 @@ i2c1: i2c@4010000 { > > =C2=A0 #size-cells =3D <0>; > > =C2=A0 clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; > > =C2=A0 clock-names =3D "ref", "pclk"; > > - interrupts =3D <50 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 status =3D "disabled"; > > =C2=A0 }; > > =C2=A0 > > @@ -184,7 +153,7 @@ i2c2: i2c@4020000 { > > =C2=A0 #size-cells =3D <0>; > > =C2=A0 clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; > > =C2=A0 clock-names =3D "ref", "pclk"; > > - interrupts =3D <51 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 status =3D "disabled"; > > =C2=A0 }; > > =C2=A0 > > @@ -195,7 +164,7 @@ i2c3: i2c@4030000 { > > =C2=A0 #size-cells =3D <0>; > > =C2=A0 clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; > > =C2=A0 clock-names =3D "ref", "pclk"; > > - interrupts =3D <52 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 status =3D "disabled"; > > =C2=A0 }; > > =C2=A0 > > @@ -206,14 +175,14 @@ i2c4: i2c@4040000 { > > =C2=A0 #size-cells =3D <0>; > > =C2=A0 clocks =3D <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; > > =C2=A0 clock-names =3D "ref", "pclk"; > > - interrupts =3D <53 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 status =3D "disabled"; > > =C2=A0 }; > > =C2=A0 > > =C2=A0 uart0: serial@4140000 { > > =C2=A0 compatible =3D "snps,dw-apb-uart"; > > =C2=A0 reg =3D <0x04140000 0x100>; > > - interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 clocks =3D <&clk CLK_UART0>, <&clk CLK_APB_UART0>; > > =C2=A0 clock-names =3D "baudclk", "apb_pclk"; > > =C2=A0 reg-shift =3D <2>; > > @@ -224,7 +193,7 @@ uart0: serial@4140000 { > > =C2=A0 uart1: serial@4150000 { > > =C2=A0 compatible =3D "snps,dw-apb-uart"; > > =C2=A0 reg =3D <0x04150000 0x100>; > > - interrupts =3D <45 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 clocks =3D <&clk CLK_UART1>, <&clk CLK_APB_UART1>; > > =C2=A0 clock-names =3D "baudclk", "apb_pclk"; > > =C2=A0 reg-shift =3D <2>; > > @@ -235,7 +204,7 @@ uart1: serial@4150000 { > > =C2=A0 uart2: serial@4160000 { > > =C2=A0 compatible =3D "snps,dw-apb-uart"; > > =C2=A0 reg =3D <0x04160000 0x100>; > > - interrupts =3D <46 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 clocks =3D <&clk CLK_UART2>, <&clk CLK_APB_UART2>; > > =C2=A0 clock-names =3D "baudclk", "apb_pclk"; > > =C2=A0 reg-shift =3D <2>; > > @@ -246,7 +215,7 @@ uart2: serial@4160000 { > > =C2=A0 uart3: serial@4170000 { > > =C2=A0 compatible =3D "snps,dw-apb-uart"; > > =C2=A0 reg =3D <0x04170000 0x100>; > > - interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 clocks =3D <&clk CLK_UART3>, <&clk CLK_APB_UART3>; > > =C2=A0 clock-names =3D "baudclk", "apb_pclk"; > > =C2=A0 reg-shift =3D <2>; > > @@ -261,7 +230,7 @@ spi0: spi@4180000 { > > =C2=A0 #size-cells =3D <0>; > > =C2=A0 clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; > > =C2=A0 clock-names =3D "ssi_clk", "pclk"; > > - interrupts =3D <54 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 status =3D "disabled"; > > =C2=A0 }; > > =C2=A0 > > @@ -272,7 +241,7 @@ spi1: spi@4190000 { > > =C2=A0 #size-cells =3D <0>; > > =C2=A0 clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; > > =C2=A0 clock-names =3D "ssi_clk", "pclk"; > > - interrupts =3D <55 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 status =3D "disabled"; > > =C2=A0 }; > > =C2=A0 > > @@ -283,7 +252,7 @@ spi2: spi@41a0000 { > > =C2=A0 #size-cells =3D <0>; > > =C2=A0 clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; > > =C2=A0 clock-names =3D "ssi_clk", "pclk"; > > - interrupts =3D <56 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 status =3D "disabled"; > > =C2=A0 }; > > =C2=A0 > > @@ -294,14 +263,14 @@ spi3: spi@41b0000 { > > =C2=A0 #size-cells =3D <0>; > > =C2=A0 clocks =3D <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; > > =C2=A0 clock-names =3D "ssi_clk", "pclk"; > > - interrupts =3D <57 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 status =3D "disabled"; > > =C2=A0 }; > > =C2=A0 > > =C2=A0 uart4: serial@41c0000 { > > =C2=A0 compatible =3D "snps,dw-apb-uart"; > > =C2=A0 reg =3D <0x041c0000 0x100>; > > - interrupts =3D <48 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 clocks =3D <&clk CLK_UART4>, <&clk CLK_APB_UART4>; > > =C2=A0 clock-names =3D "baudclk", "apb_pclk"; > > =C2=A0 reg-shift =3D <2>; > > @@ -312,7 +281,7 @@ uart4: serial@41c0000 { > > =C2=A0 sdhci0: mmc@4310000 { > > =C2=A0 compatible =3D "sophgo,cv1800b-dwcmshc"; > > =C2=A0 reg =3D <0x4310000 0x1000>; > > - interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 clocks =3D <&clk CLK_AXI4_SD0>, > > =C2=A0 <&clk CLK_SD0>; > > =C2=A0 clock-names =3D "core", "bus"; > > @@ -322,7 +291,7 @@ sdhci0: mmc@4310000 { > > =C2=A0 sdhci1: mmc@4320000 { > > =C2=A0 compatible =3D "sophgo,cv1800b-dwcmshc"; > > =C2=A0 reg =3D <0x4320000 0x1000>; > > - interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 clocks =3D <&clk CLK_AXI4_SD1>, > > =C2=A0 <&clk CLK_SD1>; > > =C2=A0 clock-names =3D "core", "bus"; > > @@ -332,7 +301,7 @@ sdhci1: mmc@4320000 { > > =C2=A0 dmac: dma-controller@4330000 { > > =C2=A0 compatible =3D "snps,axi-dma-1.01a"; > > =C2=A0 reg =3D <0x04330000 0x1000>; > > - interrupts =3D <29 IRQ_TYPE_LEVEL_HIGH>; > > + interrupts =3D ; > > =C2=A0 clocks =3D <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>; > > =C2=A0 clock-names =3D "core-clk", "cfgr-clk"; > > =C2=A0 #dma-cells =3D <1>; > > @@ -344,19 +313,5 @@ dmac: dma-controller@4330000 { > > =C2=A0 snps,data-width =3D <4>; > > =C2=A0 status =3D "disabled"; > > =C2=A0 }; > > - > > - plic: interrupt-controller@70000000 { > > - reg =3D <0x70000000 0x4000000>; > > - interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; > > - interrupt-controller; > > - #address-cells =3D <0>; > > - #interrupt-cells =3D <2>; > > - riscv,ndev =3D <101>; > > - }; > > - > > - clint: timer@74000000 { > > - reg =3D <0x74000000 0x10000>; > > - interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; > > - }; > > =C2=A0 }; > > =C2=A0}; > > diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/d= ts/sophgo/sg2002.dtsi > > index 7f79de33163c..732d0e72cf13 100644 > > --- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi > > +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi > > @@ -3,6 +3,8 @@ > > =C2=A0 * Copyright (C) 2024 Thomas Bonnefille > > =C2=A0 */ > > =C2=A0 > > +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) > > + > > =C2=A0#include > > =C2=A0#include > > =C2=A0#include "cv18xx.dtsi" > > @@ -16,22 +18,62 @@ memory@80000000 { > > =C2=A0 reg =3D <0x80000000 0x10000000>; > > =C2=A0 }; > > =C2=A0 > > - soc { > > - pinctrl: pinctrl@3001000 { > > - compatible =3D "sophgo,sg2002-pinctrl"; > > - reg =3D <0x03001000 0x1000>, > > - =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0x05027000 0x1000>; > > - reg-names =3D "sys", "rtc"; > > + cpus: cpus { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + timebase-frequency =3D <25000000>; > > + > > + cpu0: cpu@0 { > > + compatible =3D "thead,c906", "riscv"; > > + device_type =3D "cpu"; > > + reg =3D <0>; > > + d-cache-block-size =3D <64>; > > + d-cache-sets =3D <512>; > > + d-cache-size =3D <65536>; > > + i-cache-block-size =3D <64>; > > + i-cache-sets =3D <128>; > > + i-cache-size =3D <32768>; > > + mmu-type =3D "riscv,sv39"; > > + riscv,isa =3D "rv64imafdc"; > > + riscv,isa-base =3D "rv64i"; > > + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "z= icsr", > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "zifencei", "zihpm"; > > + > > + cpu0_intc: interrupt-controller { > > + compatible =3D "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells =3D <1>; > > + }; > > =C2=A0 }; > > =C2=A0 }; > > =C2=A0}; > > =C2=A0 > > -&plic { > > - compatible =3D "sophgo,sg2002-plic", "thead,c900-plic"; > > -}; > > +&soc { > > + interrupt-parent =3D <&plic>; > > + dma-noncoherent; > > =C2=A0 > > -&clint { > > - compatible =3D "sophgo,sg2002-clint", "thead,c900-clint"; > > + pinctrl: pinctrl@3001000 { > > + compatible =3D "sophgo,sg2002-pinctrl"; > > + reg =3D <0x03001000 0x1000>, > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0x05027000 0x1000>; > > + reg-names =3D "sys", "rtc"; > > + }; > > + > > + plic: interrupt-controller@70000000 { > > + compatible =3D "sophgo,sg2002-plic", "thead,c900-plic"; > > + reg =3D <0x70000000 0x4000000>; > > + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>; > > + interrupt-controller; > > + #address-cells =3D <0>; > > + #interrupt-cells =3D <2>; > > + riscv,ndev =3D <101>; > > + }; > > + > > + clint: timer@74000000 { > > + compatible =3D "sophgo,sg2002-clint", "thead,c900-clint"; > > + reg =3D <0x74000000 0x10000>; > > + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>; > > + }; > > =C2=A0}; > > =C2=A0 > > =C2=A0&clk { > > --=20 > > 2.48.1 > >=20 --=20 Alexander Sverdlin.