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From: Matthias Brugger <matthias.bgg@gmail.com>
To: Weiyi Lu <weiyi.lu@mediatek.com>,
	Nicolas Boichat <drinkcat@chromium.org>,
	Rob Herring <robh@kernel.org>
Cc: James Liao <jamesjj.liao@mediatek.com>,
	srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org,
	Fan Chen <fan.chen@mediatek.com>,
	linux-mediatek@lists.infradead.org,
	Yong Wu <yong.wu@mediatek.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v7 05/13] soc: mediatek: Refactor clock control
Date: Wed, 28 Aug 2019 11:46:39 +0200	[thread overview]
Message-ID: <71bc2521-5005-0711-57ff-b32f3a150ee6@gmail.com> (raw)
In-Reply-To: <1566983506-26598-6-git-send-email-weiyi.lu@mediatek.com>



On 28/08/2019 11:11, Weiyi Lu wrote:
> Put clock enable and disable control in separate function.
> 
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>

Applied, thanks!

> ---
>  drivers/soc/mediatek/mtk-scpsys.c | 45 ++++++++++++++++++++++++---------------
>  1 file changed, 28 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> index aed540d..73e4a1a 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -207,6 +207,29 @@ static int scpsys_regulator_disable(struct scp_domain *scpd)
>  	return regulator_disable(scpd->supply);
>  }
>  
> +static void scpsys_clk_disable(struct clk *clk[], int max_num)
> +{
> +	int i;
> +
> +	for (i = max_num - 1; i >= 0; i--)
> +		clk_disable_unprepare(clk[i]);
> +}
> +
> +static int scpsys_clk_enable(struct clk *clk[], int max_num)
> +{
> +	int i, ret = 0;
> +
> +	for (i = 0; i < max_num && clk[i]; i++) {
> +		ret = clk_prepare_enable(clk[i]);
> +		if (ret) {
> +			scpsys_clk_disable(clk, i);
> +			break;
> +		}
> +	}
> +
> +	return ret;
> +}
> +
>  static int scpsys_power_on(struct generic_pm_domain *genpd)
>  {
>  	struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
> @@ -215,21 +238,14 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
>  	u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
>  	u32 val;
>  	int ret, tmp;
> -	int i;
>  
>  	ret = scpsys_regulator_enable(scpd);
>  	if (ret < 0)
>  		return ret;
>  
> -	for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++) {
> -		ret = clk_prepare_enable(scpd->clk[i]);
> -		if (ret) {
> -			for (--i; i >= 0; i--)
> -				clk_disable_unprepare(scpd->clk[i]);
> -
> -			goto err_clk;
> -		}
> -	}
> +	ret = scpsys_clk_enable(scpd->clk, MAX_CLKS);
> +	if (ret)
> +		goto err_clk;
>  
>  	val = readl(ctl_addr);
>  	val |= PWR_ON_BIT;
> @@ -282,10 +298,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
>  	return 0;
>  
>  err_pwr_ack:
> -	for (i = MAX_CLKS - 1; i >= 0; i--) {
> -		if (scpd->clk[i])
> -			clk_disable_unprepare(scpd->clk[i]);
> -	}
> +	scpsys_clk_disable(scpd->clk, MAX_CLKS);
>  err_clk:
>  	scpsys_regulator_disable(scpd);
>  
> @@ -302,7 +315,6 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
>  	u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
>  	u32 val;
>  	int ret, tmp;
> -	int i;
>  
>  	if (scpd->data->bus_prot_mask) {
>  		ret = mtk_infracfg_set_bus_protection(scp->infracfg,
> @@ -343,8 +355,7 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
>  	if (ret < 0)
>  		goto out;
>  
> -	for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++)
> -		clk_disable_unprepare(scpd->clk[i]);
> +	scpsys_clk_disable(scpd->clk, MAX_CLKS);
>  
>  	ret = scpsys_regulator_disable(scpd);
>  	if (ret < 0)
> 

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  reply	other threads:[~2019-08-28  9:46 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-28  9:11 [PATCH v7 00/13] Mediatek MT8183 scpsys support Weiyi Lu
2019-08-28  9:11 ` [PATCH v7 01/13] dt-bindings: mediatek: Add property to mt8183 smi-common Weiyi Lu
2019-08-28  9:11 ` [PATCH v7 02/13] dt-bindings: soc: Add MT8183 power dt-bindings Weiyi Lu
2019-08-28  9:39   ` Matthias Brugger
2019-10-08  1:25     ` Weiyi Lu
2019-08-28  9:11 ` [PATCH v7 03/13] soc: mediatek: Refactor polling timeout and documentation Weiyi Lu
2019-08-28  9:43   ` Matthias Brugger
2019-08-28  9:11 ` [PATCH v7 04/13] soc: mediatek: Refactor regulator control Weiyi Lu
2019-08-28  9:44   ` Matthias Brugger
2019-08-28  9:11 ` [PATCH v7 05/13] soc: mediatek: Refactor clock control Weiyi Lu
2019-08-28  9:46   ` Matthias Brugger [this message]
2019-08-28  9:11 ` [PATCH v7 06/13] soc: mediatek: Refactor sram control Weiyi Lu
2019-08-28 10:22   ` Matthias Brugger
2019-08-28  9:11 ` [PATCH v7 07/13] soc: mediatek: Refactor bus protection control Weiyi Lu
2019-08-28 10:28   ` Matthias Brugger
2019-08-28  9:11 ` [PATCH v7 08/13] soc: mediatek: Add basic_clk_id to scp_power_data Weiyi Lu
2019-08-28  9:11 ` [PATCH v7 09/13] soc: mediatek: Add multiple step bus protection control Weiyi Lu
2019-08-28  9:11 ` [PATCH v7 10/13] soc: mediatek: Add subsys clock control for bus protection Weiyi Lu
2019-08-28  9:11 ` [PATCH v7 11/13] soc: mediatek: Add extra sram control Weiyi Lu
2019-08-28  9:11 ` [PATCH v7 12/13] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2019-08-28  9:11 ` [PATCH v7 13/13] arm64: dts: Add power controller device node of MT8183 Weiyi Lu
2019-08-29  5:15   ` CK Hu

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