From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 931F5C433EF for ; Tue, 17 May 2022 03:58:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:CC:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=lyJupxIKNHzdqtaC8JLxyeIsC/peHBp5FI88qKPS2II=; b=K097SV4qnrTLuDtWo0saHVXOLr QIhFT9TrwixlAdE6cMBhHYY4Pg612S91kckWflgFc/Yyt5xmnfv4Xu+FuM8AAvETwIC+HgDsulgNw VtrqTkFhZYOVB47w/J8B+gZnc4/9T+RrKuP483vNN8rQMeZXA+k+Y/QVQ2ltemKpc63VrUZcf/khU VpP+zlmUFeuQXhiKWQc7N7Aglp3d4EPhABd+Cz0rUtzkMTuMjX1Hv7aNujdpNqjKLs+ZLj3KATGv3 Q+hXecWOjrxk1X/q0zzNGIqoN1aQJ/mvuH7k7jBjcGEleVoBfHAfU8BVf5E4ATJf4F+WkWuX1NOPv Rr2S9ICQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nqoKK-00BXAg-4u; Tue, 17 May 2022 03:56:52 +0000 Received: from szxga08-in.huawei.com ([45.249.212.255]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nqoKG-00BX91-J2 for linux-arm-kernel@lists.infradead.org; Tue, 17 May 2022 03:56:50 +0000 Received: from kwepemi500022.china.huawei.com (unknown [172.30.72.57]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4L2Mhs2tGsz1JCVx; Tue, 17 May 2022 11:55:25 +0800 (CST) Received: from kwepemm600003.china.huawei.com (7.193.23.202) by kwepemi500022.china.huawei.com (7.221.188.64) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Tue, 17 May 2022 11:56:44 +0800 Received: from [10.67.101.67] (10.67.101.67) by kwepemm600003.china.huawei.com (7.193.23.202) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Tue, 17 May 2022 11:56:44 +0800 Subject: Re: [PATCH 08/10] coresight: Remove legacy Trace ID allocation mechanism To: Mike Leach , , , , CC: , , , , , References: <20220308205000.27646-1-mike.leach@linaro.org> <20220308205000.27646-9-mike.leach@linaro.org> From: "liuqi (BA)" Message-ID: <71c11820-433d-755d-0eb4-797313d693f9@huawei.com> Date: Tue, 17 May 2022 11:56:44 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <20220308205000.27646-9-mike.leach@linaro.org> Content-Language: en-GB X-Originating-IP: [10.67.101.67] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemm600003.china.huawei.com (7.193.23.202) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220516_205648_836832_CB8DB074 X-CRM114-Status: GOOD ( 15.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mike, On 2022/3/9 4:49, Mike Leach wrote: > This static 'cpu * 2 + seed' was outdated and broken for systems with high > core counts (>46). > > This has been replaced by a dynamic allocation system. > > Signed-off-by: Mike Leach > --- > include/linux/coresight-pmu.h | 12 ------------ > 1 file changed, 12 deletions(-) Seems coresight_get_trace_id() in tools/include/linux/coresight-pmu.h need to be deleted too. Thanks, Qi > > diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h > index 4ac5c081af93..bb4eb4de3c77 100644 > --- a/include/linux/coresight-pmu.h > +++ b/include/linux/coresight-pmu.h > @@ -8,7 +8,6 @@ > #define _LINUX_CORESIGHT_PMU_H > > #define CORESIGHT_ETM_PMU_NAME "cs_etm" > -#define CORESIGHT_ETM_PMU_SEED 0x10 > > /* > * Below are the definition of bit offsets for perf option, and works as > @@ -32,15 +31,4 @@ > #define ETM4_CFG_BIT_RETSTK 12 > #define ETM4_CFG_BIT_VMID_OPT 15 > > -static inline int coresight_get_trace_id(int cpu) > -{ > - /* > - * A trace ID of value 0 is invalid, so let's start at some > - * random value that fits in 7 bits and go from there. Since > - * the common convention is to have data trace IDs be I(N) + 1, > - * set instruction trace IDs as a function of the CPU number. > - */ > - return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); > -} > - > #endif > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel