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Wed, 11 Nov 2026 08:16:09 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface X-Archived-By: MIME-Version: 1.0 X-ThreadId: Ant3Zsh03RDg Date: Wed, 11 Nov 2026 14:15:49 +0100 From: "Ard Biesheuvel" To: "Dmitry Baryshkov" , "Ard Biesheuvel" Cc: linux-arm-kernel@lists.infradead.org, "Bjorn Andersson" , "Konrad Dybcio" , "Abel Vesa" , "Dmitry Baryshkov" , linux-arm-msm@vger.kernel.org Message-Id: <71d569ee-a939-4c41-b32f-985d7db4040f@app.fastmail.com> In-Reply-To: References: <20261111115303.3749380-9-ardb+git@google.com> <20261111115303.3749380-11-ardb+git@google.com> Subject: Re: [PATCH 2/7] arm64: dts: qcom: c630: Use LN_BB_CLK2 as the eDP bridge reference clock Content-Type: text/plain Content-Transfer-Encoding: 7bit X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-5.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Wed, 11 Nov 2026, at 13:43, Dmitry Baryshkov wrote: > On Wed, Nov 11, 2026 at 12:53:06PM +0100, Ard Biesheuvel wrote: >> From: Ard Biesheuvel >> >> The SN65DSI86 eDP bridge on the Yoga C630 is described as being clocked by >> an always-on fixed 19.2 MHz reference clock. However, as on the SDM845 >> reference design (Cheza), its REFCLK appears to be fed by the LN_BB_CLK2 >> output of the PMIC, which also serves as the master clock of the WCD9340 >> audio codec. >> >> As nothing tells Linux that the bridge depends on LN_BB_CLK2, the clock >> only runs when the codec happens to have it enabled, and the WCD934x >> driver only enables it on demand. If the bridge is brought up while >> LN_BB_CLK2 is off or being toggled, e.g., when the display stack probes >> before the codec, or while the codec is being initialized, all AUX >> transfers fail and the DP PLL does not lock, leaving the panel dark: >> >> ti_sn65dsi86 10-002c: Can't read lane count (-110); assuming 4 >> ti_sn65dsi86 10-002c: Can't read eDP rev (-110), assuming 1.1 >> ti_sn65dsi86 10-002c: Can't read max rate (-110); assuming 5.4 GHz >> ti_sn65dsi86 10-002c: DP_PLL_LOCK polling failed (-110) >> >> So describe the actual clock instead, so that the bridge driver keeps it >> enabled for as long as the bridge is powered up. > > According to the schematics the actual clock is a divider clock coming > from the GPIO16 of the PMIC. > Which is always powered, I suppose? So I suppose that means just the arbitrary stall resulting from the clock enable is sufficient to make this issue go away? Any clue what else it might be waiting for?