From: Michal Simek <michal.simek@amd.com>
To: <linux-kernel@vger.kernel.org>, <monstr@monstr.eu>,
<michal.simek@xilinx.com>, <git@xilinx.com>
Cc: Conor Dooley <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Parth Gajjar <parth.gajjar@amd.com>,
Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>,
Rob Herring <robh+dt@kernel.org>,
Tanmay Shah <tanmay.shah@amd.com>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH 6/6] arm64: xilinx: Remove address/size-cells from gem nodes
Date: Mon, 18 Sep 2023 14:41:17 +0200 [thread overview]
Message-ID: <7252203d52af3ca8867764c8514affc4828e530d.1695040866.git.michal.simek@amd.com> (raw)
In-Reply-To: <cover.1695040866.git.michal.simek@amd.com>
Some boards are using one mdio bus which holds multiple phys and also
boards are using mdio node for bus description. That's why there are cases
where address/size-cells are unnecessary which is also reported by make W=1
dtbs. That's why remove them from zynqmp.dtsi and let board DTSes to handle
it based on used description.
Error log:
/axi/ethernet@ff0e0000: unnecessary #address-cells/#size-cells without
"ranges" or child "reg" property
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 --------
1 file changed, 8 deletions(-)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index e50e95cbe817..f5e1eb8cb3b7 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -584,8 +584,6 @@ gem0: ethernet@ff0b0000 {
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0b0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- #address-cells = <1>;
- #size-cells = <0>;
iommus = <&smmu 0x874>;
power-domains = <&zynqmp_firmware PD_ETH_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
@@ -600,8 +598,6 @@ gem1: ethernet@ff0c0000 {
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0c0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- #address-cells = <1>;
- #size-cells = <0>;
iommus = <&smmu 0x875>;
power-domains = <&zynqmp_firmware PD_ETH_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
@@ -616,8 +612,6 @@ gem2: ethernet@ff0d0000 {
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0d0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- #address-cells = <1>;
- #size-cells = <0>;
iommus = <&smmu 0x876>;
power-domains = <&zynqmp_firmware PD_ETH_2>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
@@ -632,8 +626,6 @@ gem3: ethernet@ff0e0000 {
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0e0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
- #address-cells = <1>;
- #size-cells = <0>;
iommus = <&smmu 0x877>;
power-domains = <&zynqmp_firmware PD_ETH_3>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
--
2.36.1
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next prev parent reply other threads:[~2023-09-18 12:42 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-18 12:41 [PATCH 0/6] arm64: xilinx: Tune DTSes to remove warnings from make W=1 dtbs Michal Simek
2023-09-18 12:41 ` [PATCH 1/6] arm64: xilinx: Do not use '_' in DT node names Michal Simek
2023-09-18 14:56 ` Laurent Pinchart
2023-09-19 7:47 ` Michal Simek
2023-09-19 7:56 ` Laurent Pinchart
2023-09-18 12:41 ` [PATCH 2/6] arm64: xilinx: Use lower case for partition address Michal Simek
2023-09-18 14:58 ` Laurent Pinchart
2023-09-18 12:41 ` [PATCH 3/6] arm64: xilinx: Remove mt25qu512a compatible string from SOM Michal Simek
2023-09-18 15:01 ` Laurent Pinchart
2023-09-19 7:06 ` Michal Simek
2023-09-18 12:41 ` [PATCH 4/6] arm64: xilinx: Put ethernet phys to mdio node Michal Simek
2023-09-18 12:41 ` [PATCH 5/6] arm64: xilinx: Remove address/size-cells from flash node Michal Simek
2023-09-18 12:41 ` Michal Simek [this message]
2023-10-16 10:07 ` [PATCH 0/6] arm64: xilinx: Tune DTSes to remove warnings from make W=1 dtbs Michal Simek
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