From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECF54D2E015 for ; Wed, 23 Oct 2024 06:14:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=BSIaD4BkUIQReRGn212FJT8/QH576I9A6XLaml2XCdU=; b=avkzm3nnHYkC2hlCritC2UWgNA fpkF7MG9sH5t8Y+JyqN6hBhmdLxM05qj1beFnoUUrSkNJPmEzm6/+BxLUW2WHloLXSFRDF1vreSEg lSRxGhZedK6fy41ZlNWftkKjPo2iKLTfpOvc4Tp9lw4Dmi+xIw4gCVlBp6Is/hB5vhfJr29WcBpk4 263LxbuTYB+gkGyH5+wOAIk1LbiFkrO0qGqV5C8tCGXiQgisW1v4oVpR+4Fl992AnSjJ/novRvYWr AaFBTR62pj0bkli2mSwLjh9YtTgA/bGStTdQW3esIhHvcDG8Pd7BMgQGsVnEWrC8JCgYcR/y1IIml aM1L1KhA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t3UdP-0000000DA1w-3vP5; Wed, 23 Oct 2024 06:14:20 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t3Ubs-0000000D9pG-2aXE for linux-arm-kernel@lists.infradead.org; Wed, 23 Oct 2024 06:12:46 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 11B83339; Tue, 22 Oct 2024 23:13:12 -0700 (PDT) Received: from [10.163.41.228] (unknown [10.163.41.228]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8ADE93F73B; Tue, 22 Oct 2024 23:12:38 -0700 (PDT) Message-ID: <72700154-cbf4-4a0a-b6e2-6f0709dec0ce@arm.com> Date: Wed, 23 Oct 2024 11:42:37 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9 To: Mark Rutland Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jonathan Corbet , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org References: <20241001043602.1116991-1-anshuman.khandual@arm.com> <20241001043602.1116991-3-anshuman.khandual@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241022_231244_793192_0F99155F X-CRM114-Status: GOOD ( 16.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/22/24 21:40, Mark Rutland wrote: > On Tue, Oct 01, 2024 at 10:06:01AM +0530, Anshuman Khandual wrote: >> Fine grained trap control for MDSELR_EL1 register needs to be configured in >> HDFGRTR2_EL2, and HDFGWTR2_EL2 registers when kernel enters at EL1, but EL2 >> is also present. This adds a new helper __init_el2_fgt2() initializing this >> new FEAT_FGT2 based fine grained registers. >> >> MDCR_EL2.EBWE needs to be enabled for additional (beyond 16) breakpoint and >> watchpoint exceptions when kernel enters at EL1, but EL2 is also present. >> This updates __init_el2_debug() as required for FEAT_Debugv8p9. >> >> While here, also update booting.rst with MDCR_EL3 and SCR_EL3 requirements. > > [...] > >> + For CPUs with FEAT_Debugv8p9 extension present: >> + >> + - If the kernel is entered at EL1 and EL2 is present: >> + >> + - HDFGRTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 >> + - HDFGWTR2_EL2.nMDSELR_EL1 (bit 5) must be initialized to 0b1 >> + - MDCR_EL2.EBWE (bit 43) must be initialized to 0b1 >> + >> + - If EL3 is present: >> + >> + - MDCR_EL3.TDA (bit 9) must be initialized to 0b0 > > AFAICT we need TDA==0 this regardless of FEAT_Debugv8p9 (and e.g. we need That's because MDCR_EL3.TDA=0, enables access to many other debug registers beside FEAT_Debugv8p9, which are currently used and hence this MDCR_EL3.TDA =0 requirement is a not a new one but rather a missing one instead ? > MDCR_EL3.TPM==0 where FEAT_PMUv3 is implemented), so we should probably > check if there's anything else we haven't yet documented in MDCR_EL3. Will scan through MDCR_EL3 register and match it with existing documentation i.e Documentation/arch/arm64/booting.rst. If there are some missing MDCR_EL3 fields which should be mentioned, will add them via a separate pre-requisite patch ? > > [...] > >> .Lskip_trace_\@: >> + mrs x1, id_aa64dfr0_el1 >> + ubfx x1, x1, #ID_AA64DFR0_EL1_DebugVer_SHIFT, #4 >> + cmp x1, #ID_AA64DFR0_EL1_DebugVer_V8P9 >> + b.lt .Lskip_dbg_v8p9_\@ >> + >> + mov x0, #MDCR_EL2_EBWE >> + orr x2, x2, x0 > > That can be: > > orr x2, x2, #MDCR_EL2_EBWE Right, will change. > > Mark.