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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251013_165953_577571_6AA5BF3E X-CRM114-Status: GOOD ( 15.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Le 13/10/2025 à 17:43, Jernej Škrabec a écrit : > Dne ponedeljek, 13. oktober 2025 ob 17:26:45 Srednjeevropski poletni čas je Richard Genoud napisal(a): >> The H616 has a NAND controller quite similar to the A10/A23 ones, but >> with some register differences, more clocks (for ECC and MBUS), more ECC >> strengths, so this requires a new compatible string. >> >> Add the NAND controller node and pins in the device tree. >> >> Signed-off-by: Richard Genoud >> --- >> .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 51 +++++++++++++++++++ >> 1 file changed, 51 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi >> index ceedae9e399b..bb53c6c63836 100644 >> --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi >> @@ -304,6 +304,42 @@ mmc2_pins: mmc2-pins { >> bias-pull-up; >> }; >> >> + /omit-if-no-ref/ >> + nand_pins: nand-pins { >> + pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9", >> + "PC10", "PC11", "PC12", "PC13", "PC14", >> + "PC15", "PC16"; >> + function = "nand0"; >> + }; >> + >> + /omit-if-no-ref/ >> + nand_cs0_pin: nand-cs0-pin { >> + pins = "PC4"; >> + function = "nand0"; >> + bias-pull-up; >> + }; >> + >> + /omit-if-no-ref/ >> + nand_cs1_pin: nand-cs1-pin { >> + pins = "PC3"; >> + function = "nand0"; >> + bias-pull-up; >> + }; >> + >> + /omit-if-no-ref/ >> + nand_rb0_pin: nand-rb0-pin { >> + pins = "PC6"; >> + function = "nand0"; >> + bias-pull-up; >> + }; >> + >> + /omit-if-no-ref/ >> + nand_rb1_pin: nand-rb1-pin { >> + pins = "PC7"; >> + function = "nand0"; >> + bias-pull-up; >> + }; >> + >> /omit-if-no-ref/ >> spi0_pins: spi0-pins { >> pins = "PC0", "PC2", "PC4"; >> @@ -377,6 +413,21 @@ iommu: iommu@30f0000 { >> #iommu-cells = <1>; >> }; >> >> + nfc: nand-controller@4011000 { >> + compatible = "allwinner,sun50i-h616-nand-controller"; >> + reg = <0x04011000 0x1000>; >> + interrupts = ; >> + clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND0>, >> + <&ccu CLK_NAND1>, <&ccu CLK_MBUS_NAND>; >> + clock-names = "ahb", "mod", "ecc", "mbus"; >> + resets = <&ccu RST_BUS_NAND>; >> + reset-names = "ahb"; >> + dmas = <&dma 10>; >> + dma-names = "rxtx"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; > > Sorry, forgot to mention. This should be marked as disabled, as most of > the boards don't have NAND connected. arg! of course, I forgot that. Thanks! > > Best regards, > Jernej > >> + >> mmc0: mmc@4020000 { >> compatible = "allwinner,sun50i-h616-mmc", >> "allwinner,sun50i-a100-mmc"; >> > > > > -- Richard Genoud, Bootlin Embedded Linux and Kernel engineering https://bootlin.com