From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4258C433DB for ; Fri, 12 Feb 2021 15:38:04 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 800F864E74 for ; Fri, 12 Feb 2021 15:38:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 800F864E74 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9gjVTQ9gCzGLQTERr+g4KjXgt1EcDO2+G4SjGgIspjs=; b=jbBmRW4mcJvPH6pr1E1U7ue4i 2poOdA8SJmjfWolK7gKhQ9vVff9HC0R/ZZkspsUem40fqY07GZDUUPVeRq/j7QG0iOpvMUjL2w7Ip i14p9S2tHEtPpqvdoaFLFl0ZH78LDN0ZkaNS2CvFcUULGDpvVI5C8IQnh0RsvuusF4aer5MBiEZcH 8VeRUC0NWjGOb6pFYm4yO4VpcDgM0V3FKTNhGM5hGfkXvS+twg+QquWJm4TslNyeYnagblugfCq6j A+O8CInGle+NTEDM/HH6ZvXOegQYQ1jZBkhhx4iknZk26RQHvfEjWC20lb3KLqpzUFRbU270TSLnG A2tQjWBbw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lAaV5-0003j6-Jy; Fri, 12 Feb 2021 15:36:55 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lAaV2-0003hx-Tp for linux-arm-kernel@lists.infradead.org; Fri, 12 Feb 2021 15:36:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 90C4B1063; Fri, 12 Feb 2021 07:36:47 -0800 (PST) Received: from [10.57.44.108] (unknown [10.57.44.108]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4DD243F73B; Fri, 12 Feb 2021 07:36:45 -0800 (PST) Subject: Re: [PATCH v7 28/28] coresight: Add support for v8.4 SelfHosted tracing To: Mike Leach References: <20210110224850.1880240-1-suzuki.poulose@arm.com> <20210110224850.1880240-29-suzuki.poulose@arm.com> From: Suzuki K Poulose Message-ID: <72f85de4-5b39-c963-78cf-2f8347e21268@arm.com> Date: Fri, 12 Feb 2021 15:36:33 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210212_103653_110057_9FE98117 X-CRM114-Status: GOOD ( 36.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mathieu Poirier , Anshuman Khandual , Catalin Marinas , Coresight ML , Linux Kernel Mailing List , Jonathan Zhou , Leo Yan , Will Deacon , linux-arm-kernel Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mike On 2/12/21 10:34 AM, Mike Leach wrote: > Hi Mathieu, Suzuki, > > Sorry for the really late response on this patch, but I noticed a > problem while doing a review of the ETE / TRBE set. (TRBE specs > mention TRFCR_ELx, so I was confirming a couple of things). > > On Sun, 10 Jan 2021 at 22:49, Suzuki K Poulose wrote: >> >> From: Jonathan Zhou >> >> v8.4 tracing extensions added support for trace filtering controlled >> by TRFCR_ELx. This must be programmed to allow tracing at EL1/EL2 and >> EL0. The timestamp used is the virtual time. Also enable CONTEXIDR_EL2 >> tracing if we are running the kernel at EL2. >> >> Cc: Catalin Marinas >> Cc: Mike Leach >> Cc: Will Deacon >> Reviewed-by: Mathieu Poirier >> Signed-off-by: Jonathan Zhou >> [ Move the trace filtering setup etm_init_arch_data() and >> clean ups] >> Signed-off-by: Suzuki K Poulose >> --- >> .../coresight/coresight-etm4x-core.c | 25 +++++++++++++++++++ >> 1 file changed, 25 insertions(+) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index 3d3165dd09d4..18c1a80abab8 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -859,6 +859,30 @@ static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata, >> return false; >> } >> >> +static void cpu_enable_tracing(void) >> +{ >> + u64 dfr0 = read_sysreg(id_aa64dfr0_el1); >> + u64 trfcr; >> + >> + if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_TRACE_FILT_SHIFT)) >> + return; >> + >> + /* >> + * If the CPU supports v8.4 SelfHosted Tracing, enable >> + * tracing at the kernel EL and EL0, forcing to use the >> + * virtual time as the timestamp. >> + */ >> + trfcr = (TRFCR_ELx_TS_VIRTUAL | >> + TRFCR_ELx_ExTRE | >> + TRFCR_ELx_E0TRE); >> + >> + /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */ >> + if (is_kernel_in_hyp_mode()) >> + trfcr |= TRFCR_EL2_CX; >> + > > This is wrong - CX bit is present on TRFCR_EL2, not TRFCR_EL1. Why is this wrong ? We do this only when we are in EL2. > Moreover, TRFCR_EL2 has a separate enables for tracing at EL0 and EL2. > True, that is for EL0&2 translation regimes. i.e, tracing EL0 with the kernel running at EL2. But bits TRFCR_EL2.E2TRE == TRFCR_EL1.E1TRE If notice, we name the bit TRFCR_ELx_ExTRE. And E0TRE == E0HTRE. So we do the following : 1) When kernel running at EL2: Enable tracing at EL2 and EL0 and context tracking 2) When kernel running at EL1: Enable tracing at EL1 and EL0. > Secondly - is this correct in principal? Should the driver not be > reading the access it is permitted by the kernel, rather than giving > itself unfettered access to trace where it wants to. I dont follow the "access permitted by the kernel" here. What are we referrring to ? > Surely TRFCR_ELx levels should be chosen in KConfig and then should > be set up in kernel initialisation? I disagree with yet another Kconfig. This basic requirement for enabling the trace collection. It is not something that we can optionally use from the architecture. So we should transparently do the right thing for making sure that we set up the system for something that didn't require any other steps. Or in other words, if we add a Kconfig option for TRFCR programming, if someone forgets to select it when they upgraded the kernel they are in for a surprisingly long debugging to find why the trace doesnt work. As for the TRFCR programming, we have two choices. etm4x driver or generic boot up for the CPU. I preferred to do this in the driver as we can enable it only if trace drivers are available. Cheers Suzuki > > Regards > > Mike > > > >> + write_sysreg_s(trfcr, SYS_TRFCR_EL1); >> +} >> + >> static void etm4_init_arch_data(void *info) >> { >> u32 etmidr0; >> @@ -1044,6 +1068,7 @@ static void etm4_init_arch_data(void *info) >> /* NUMCNTR, bits[30:28] number of counters available for tracing */ >> drvdata->nr_cntr = BMVAL(etmidr5, 28, 30); >> etm4_cs_lock(drvdata, csa); >> + cpu_enable_tracing(); >> } >> >> static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config) >> -- >> 2.24.1 >> > > > -- > Mike Leach > Principal Engineer, ARM Ltd. > Manchester Design Centre. UK > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel