* [PATCH 0/3] Add support for MT8189 power controller
@ 2026-02-02 6:48 irving.ch.lin
2026-02-02 6:48 ` [PATCH 1/3] dt-bindings: power: Add MediaTek MT8189 power domain irving.ch.lin
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: irving.ch.lin @ 2026-02-02 6:48 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ulf Hansson,
Matthias Brugger, AngeloGioacchino Del Regno
Cc: Matthias Brugger, devicetree, linux-pm, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, Qiqi Wang,
sirius.wang, vince-wl.liu, jh.hsu, irving-ch.lin
From: Irving-CH Lin <irving-ch.lin@mediatek.com>
This series add support for the power controllers
of MediaTek's new SoC, MT8189. With these changes, other modules
can easily manage power resources using standard Linux APIs,
such as the pm_runtime API on MT8189 platform.
Irving-CH Lin (3):
dt-bindings: power: Add MediaTek MT8189 power domain
pmdomain: mediatek: Add bus protect control flow for MT8189
pmdomain: mediatek: Add power domain driver for MT8189 SoC
.../power/mediatek,power-controller.yaml | 1 +
drivers/pmdomain/mediatek/mt8189-pm-domains.h | 485 ++++++++++++++++++
drivers/pmdomain/mediatek/mtk-pm-domains.c | 36 +-
drivers/pmdomain/mediatek/mtk-pm-domains.h | 5 +
.../dt-bindings/power/mediatek,mt8189-power.h | 38 ++
5 files changed, 560 insertions(+), 5 deletions(-)
create mode 100644 drivers/pmdomain/mediatek/mt8189-pm-domains.h
create mode 100644 include/dt-bindings/power/mediatek,mt8189-power.h
--
2.45.2
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 1/3] dt-bindings: power: Add MediaTek MT8189 power domain 2026-02-02 6:48 [PATCH 0/3] Add support for MT8189 power controller irving.ch.lin @ 2026-02-02 6:48 ` irving.ch.lin 2026-02-02 12:02 ` AngeloGioacchino Del Regno 2026-02-04 17:44 ` Matthias Brugger 2026-02-02 6:48 ` [PATCH 2/3] pmdomain: mediatek: Add bus protect control flow for MT8189 irving.ch.lin ` (2 subsequent siblings) 3 siblings, 2 replies; 11+ messages in thread From: irving.ch.lin @ 2026-02-02 6:48 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ulf Hansson, Matthias Brugger, AngeloGioacchino Del Regno Cc: Matthias Brugger, devicetree, linux-pm, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Qiqi Wang, sirius.wang, vince-wl.liu, jh.hsu, irving-ch.lin From: Irving-CH Lin <irving-ch.lin@mediatek.com> Add dt schema and IDs for the power domain of MediaTek MT8189 SoC. The MT8189 power domain IP provide power domains control function for subsys (eg. MFG, audio, venc/vdec ...). Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com> --- .../power/mediatek,power-controller.yaml | 1 + .../dt-bindings/power/mediatek,mt8189-power.h | 38 +++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 include/dt-bindings/power/mediatek,mt8189-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 9507b342a7ee..07f046277f8a 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -31,6 +31,7 @@ properties: - mediatek,mt8183-power-controller - mediatek,mt8186-power-controller - mediatek,mt8188-power-controller + - mediatek,mt8189-power-controller - mediatek,mt8192-power-controller - mediatek,mt8195-power-controller - mediatek,mt8196-hwv-hfrp-power-controller diff --git a/include/dt-bindings/power/mediatek,mt8189-power.h b/include/dt-bindings/power/mediatek,mt8189-power.h new file mode 100644 index 000000000000..70a8c2113457 --- /dev/null +++ b/include/dt-bindings/power/mediatek,mt8189-power.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang <qiqi.wang@mediatek.com> + */ + +#ifndef _DT_BINDINGS_POWER_MT8189_POWER_H +#define _DT_BINDINGS_POWER_MT8189_POWER_H + +/* SPM */ +#define MT8189_POWER_DOMAIN_CONN 0 +#define MT8189_POWER_DOMAIN_AUDIO 1 +#define MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT 2 +#define MT8189_POWER_DOMAIN_ADSP_INFRA 3 +#define MT8189_POWER_DOMAIN_ADSP_AO 4 +#define MT8189_POWER_DOMAIN_MM_INFRA 5 +#define MT8189_POWER_DOMAIN_ISP_IMG1 6 +#define MT8189_POWER_DOMAIN_ISP_IMG2 7 +#define MT8189_POWER_DOMAIN_ISP_IPE 8 +#define MT8189_POWER_DOMAIN_VDE0 9 +#define MT8189_POWER_DOMAIN_VEN0 10 +#define MT8189_POWER_DOMAIN_CAM_MAIN 11 +#define MT8189_POWER_DOMAIN_CAM_SUBA 12 +#define MT8189_POWER_DOMAIN_CAM_SUBB 13 +#define MT8189_POWER_DOMAIN_MDP0 14 +#define MT8189_POWER_DOMAIN_DISP 15 +#define MT8189_POWER_DOMAIN_DP_TX 16 +#define MT8189_POWER_DOMAIN_CSI_RX 17 +#define MT8189_POWER_DOMAIN_SSUSB 18 +#define MT8189_POWER_DOMAIN_MFG0 19 +#define MT8189_POWER_DOMAIN_MFG1 20 +#define MT8189_POWER_DOMAIN_MFG2 21 +#define MT8189_POWER_DOMAIN_MFG3 22 +#define MT8189_POWER_DOMAIN_EDP_TX_DORMANT 23 +#define MT8189_POWER_DOMAIN_PCIE 24 +#define MT8189_POWER_DOMAIN_PCIE_PHY 25 + +#endif /* _DT_BINDINGS_POWER_MT8189_POWER_H */ -- 2.45.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] dt-bindings: power: Add MediaTek MT8189 power domain 2026-02-02 6:48 ` [PATCH 1/3] dt-bindings: power: Add MediaTek MT8189 power domain irving.ch.lin @ 2026-02-02 12:02 ` AngeloGioacchino Del Regno 2026-02-04 17:44 ` Matthias Brugger 1 sibling, 0 replies; 11+ messages in thread From: AngeloGioacchino Del Regno @ 2026-02-02 12:02 UTC (permalink / raw) To: irving.ch.lin, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ulf Hansson, Matthias Brugger Cc: Matthias Brugger, devicetree, linux-pm, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Qiqi Wang, sirius.wang, vince-wl.liu, jh.hsu Il 02/02/26 07:48, irving.ch.lin ha scritto: > From: Irving-CH Lin <irving-ch.lin@mediatek.com> > > Add dt schema and IDs for the power domain of MediaTek MT8189 SoC. > The MT8189 power domain IP provide power domains control function > for subsys (eg. MFG, audio, venc/vdec ...). > > Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] dt-bindings: power: Add MediaTek MT8189 power domain 2026-02-02 6:48 ` [PATCH 1/3] dt-bindings: power: Add MediaTek MT8189 power domain irving.ch.lin 2026-02-02 12:02 ` AngeloGioacchino Del Regno @ 2026-02-04 17:44 ` Matthias Brugger 1 sibling, 0 replies; 11+ messages in thread From: Matthias Brugger @ 2026-02-04 17:44 UTC (permalink / raw) To: irving.ch.lin, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ulf Hansson, Matthias Brugger, AngeloGioacchino Del Regno Cc: devicetree, linux-pm, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Qiqi Wang, sirius.wang, vince-wl.liu, jh.hsu On 02/02/2026 07:48, irving.ch.lin wrote: > From: Irving-CH Lin <irving-ch.lin@mediatek.com> > > Add dt schema and IDs for the power domain of MediaTek MT8189 SoC. > The MT8189 power domain IP provide power domains control function > for subsys (eg. MFG, audio, venc/vdec ...). > > Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > .../power/mediatek,power-controller.yaml | 1 + > .../dt-bindings/power/mediatek,mt8189-power.h | 38 +++++++++++++++++++ > 2 files changed, 39 insertions(+) > create mode 100644 include/dt-bindings/power/mediatek,mt8189-power.h > > diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > index 9507b342a7ee..07f046277f8a 100644 > --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > @@ -31,6 +31,7 @@ properties: > - mediatek,mt8183-power-controller > - mediatek,mt8186-power-controller > - mediatek,mt8188-power-controller > + - mediatek,mt8189-power-controller > - mediatek,mt8192-power-controller > - mediatek,mt8195-power-controller > - mediatek,mt8196-hwv-hfrp-power-controller > diff --git a/include/dt-bindings/power/mediatek,mt8189-power.h b/include/dt-bindings/power/mediatek,mt8189-power.h > new file mode 100644 > index 000000000000..70a8c2113457 > --- /dev/null > +++ b/include/dt-bindings/power/mediatek,mt8189-power.h > @@ -0,0 +1,38 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2025 MediaTek Inc. > + * Author: Qiqi Wang <qiqi.wang@mediatek.com> > + */ > + > +#ifndef _DT_BINDINGS_POWER_MT8189_POWER_H > +#define _DT_BINDINGS_POWER_MT8189_POWER_H > + > +/* SPM */ > +#define MT8189_POWER_DOMAIN_CONN 0 > +#define MT8189_POWER_DOMAIN_AUDIO 1 > +#define MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT 2 > +#define MT8189_POWER_DOMAIN_ADSP_INFRA 3 > +#define MT8189_POWER_DOMAIN_ADSP_AO 4 > +#define MT8189_POWER_DOMAIN_MM_INFRA 5 > +#define MT8189_POWER_DOMAIN_ISP_IMG1 6 > +#define MT8189_POWER_DOMAIN_ISP_IMG2 7 > +#define MT8189_POWER_DOMAIN_ISP_IPE 8 > +#define MT8189_POWER_DOMAIN_VDE0 9 > +#define MT8189_POWER_DOMAIN_VEN0 10 > +#define MT8189_POWER_DOMAIN_CAM_MAIN 11 > +#define MT8189_POWER_DOMAIN_CAM_SUBA 12 > +#define MT8189_POWER_DOMAIN_CAM_SUBB 13 > +#define MT8189_POWER_DOMAIN_MDP0 14 > +#define MT8189_POWER_DOMAIN_DISP 15 > +#define MT8189_POWER_DOMAIN_DP_TX 16 > +#define MT8189_POWER_DOMAIN_CSI_RX 17 > +#define MT8189_POWER_DOMAIN_SSUSB 18 > +#define MT8189_POWER_DOMAIN_MFG0 19 > +#define MT8189_POWER_DOMAIN_MFG1 20 > +#define MT8189_POWER_DOMAIN_MFG2 21 > +#define MT8189_POWER_DOMAIN_MFG3 22 > +#define MT8189_POWER_DOMAIN_EDP_TX_DORMANT 23 > +#define MT8189_POWER_DOMAIN_PCIE 24 > +#define MT8189_POWER_DOMAIN_PCIE_PHY 25 > + > +#endif /* _DT_BINDINGS_POWER_MT8189_POWER_H */ ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/3] pmdomain: mediatek: Add bus protect control flow for MT8189 2026-02-02 6:48 [PATCH 0/3] Add support for MT8189 power controller irving.ch.lin 2026-02-02 6:48 ` [PATCH 1/3] dt-bindings: power: Add MediaTek MT8189 power domain irving.ch.lin @ 2026-02-02 6:48 ` irving.ch.lin 2026-02-02 12:02 ` AngeloGioacchino Del Regno 2026-02-04 17:46 ` Matthias Brugger 2026-02-02 6:48 ` [PATCH 3/3] pmdomain: mediatek: Add power domain driver for MT8189 SoC irving.ch.lin 2026-02-02 14:59 ` [PATCH 0/3] Add support for MT8189 power controller Ulf Hansson 3 siblings, 2 replies; 11+ messages in thread From: irving.ch.lin @ 2026-02-02 6:48 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ulf Hansson, Matthias Brugger, AngeloGioacchino Del Regno Cc: Matthias Brugger, devicetree, linux-pm, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Qiqi Wang, sirius.wang, vince-wl.liu, jh.hsu, irving-ch.lin From: Irving-CH Lin <irving-ch.lin@mediatek.com> In MT8189 mminfra power domain, the bus protect policy separates into two parts, one is set before subsys clocks enabled, and another need to enable after subsys clocks enable. Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com> --- drivers/pmdomain/mediatek/mtk-pm-domains.c | 31 ++++++++++++++++++---- drivers/pmdomain/mediatek/mtk-pm-domains.h | 5 ++++ 2 files changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c index 0f0662676c07..3eeb0dabf7d7 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -250,7 +250,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain *pd, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } -static int scpsys_bus_protect_enable(struct scpsys_domain *pd) +static int scpsys_bus_protect_enable(struct scpsys_domain *pd, u8 flags) { for (int i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) { const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i]; @@ -259,6 +259,10 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd) if (!bpd->bus_prot_set_clr_mask) break; + if ((bpd->flags & BUS_PROT_IGNORE_SUBCLK) != + (flags & BUS_PROT_IGNORE_SUBCLK)) + continue; + if (bpd->flags & BUS_PROT_INVERTED) ret = scpsys_bus_protect_clear(pd, bpd); else @@ -270,7 +274,7 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd) return 0; } -static int scpsys_bus_protect_disable(struct scpsys_domain *pd) +static int scpsys_bus_protect_disable(struct scpsys_domain *pd, u8 flags) { for (int i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) { const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i]; @@ -279,6 +283,10 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd) if (!bpd->bus_prot_set_clr_mask) continue; + if ((bpd->flags & BUS_PROT_IGNORE_SUBCLK) != + (flags & BUS_PROT_IGNORE_SUBCLK)) + continue; + if (bpd->flags & BUS_PROT_INVERTED) ret = scpsys_bus_protect_set(pd, bpd); else @@ -632,6 +640,15 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) if (ret) goto err_pwr_ack; + /* + * In MT8189 mminfra power domain, the bus protect policy separates + * into two parts, one is set before subsys clocks enabled, and another + * need to enable after subsys clocks enable. + */ + ret = scpsys_bus_protect_disable(pd, BUS_PROT_IGNORE_SUBCLK); + if (ret < 0) + goto err_pwr_ack; + /* * In few Mediatek platforms(e.g. MT6779), the bus protect policy is * stricter, which leads to bus protect release must be prior to bus @@ -648,7 +665,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) if (ret < 0) goto err_disable_subsys_clks; - ret = scpsys_bus_protect_disable(pd); + ret = scpsys_bus_protect_disable(pd, 0); if (ret < 0) goto err_disable_sram; @@ -662,7 +679,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) return 0; err_enable_bus_protect: - scpsys_bus_protect_enable(pd); + scpsys_bus_protect_enable(pd, 0); err_disable_sram: scpsys_sram_disable(pd); err_disable_subsys_clks: @@ -683,7 +700,7 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) bool tmp; int ret; - ret = scpsys_bus_protect_enable(pd); + ret = scpsys_bus_protect_enable(pd, 0); if (ret < 0) return ret; @@ -697,6 +714,10 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); + ret = scpsys_bus_protect_enable(pd, BUS_PROT_IGNORE_SUBCLK); + if (ret < 0) + return ret; + if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_PWRSEQ)) scpsys_modem_pwrseq_off(pd); else diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h index f608e6ec4744..a5dca24cbc2f 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h @@ -56,6 +56,7 @@ enum scpsys_bus_prot_flags { BUS_PROT_REG_UPDATE = BIT(1), BUS_PROT_IGNORE_CLR_ACK = BIT(2), BUS_PROT_INVERTED = BIT(3), + BUS_PROT_IGNORE_SUBCLK = BIT(4), }; enum scpsys_bus_prot_block { @@ -95,6 +96,10 @@ enum scpsys_bus_prot_block { _BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \ BUS_PROT_REG_UPDATE) +#define BUS_PROT_WR_IGN_SUBCLK(_hwip, _mask, _set, _clr, _sta) \ + _BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \ + BUS_PROT_IGNORE_CLR_ACK | BUS_PROT_IGNORE_SUBCLK) + #define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \ BUS_PROT_UPDATE(INFRA, _mask, \ INFRA_TOPAXI_PROTECTEN, \ -- 2.45.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] pmdomain: mediatek: Add bus protect control flow for MT8189 2026-02-02 6:48 ` [PATCH 2/3] pmdomain: mediatek: Add bus protect control flow for MT8189 irving.ch.lin @ 2026-02-02 12:02 ` AngeloGioacchino Del Regno 2026-02-04 17:46 ` Matthias Brugger 1 sibling, 0 replies; 11+ messages in thread From: AngeloGioacchino Del Regno @ 2026-02-02 12:02 UTC (permalink / raw) To: irving.ch.lin, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ulf Hansson, Matthias Brugger Cc: Matthias Brugger, devicetree, linux-pm, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Qiqi Wang, sirius.wang, vince-wl.liu, jh.hsu Il 02/02/26 07:48, irving.ch.lin ha scritto: > From: Irving-CH Lin <irving-ch.lin@mediatek.com> > > In MT8189 mminfra power domain, the bus protect policy separates > into two parts, one is set before subsys clocks enabled, and another > need to enable after subsys clocks enable. > > Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] pmdomain: mediatek: Add bus protect control flow for MT8189 2026-02-02 6:48 ` [PATCH 2/3] pmdomain: mediatek: Add bus protect control flow for MT8189 irving.ch.lin 2026-02-02 12:02 ` AngeloGioacchino Del Regno @ 2026-02-04 17:46 ` Matthias Brugger 1 sibling, 0 replies; 11+ messages in thread From: Matthias Brugger @ 2026-02-04 17:46 UTC (permalink / raw) To: irving.ch.lin, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ulf Hansson, Matthias Brugger, AngeloGioacchino Del Regno Cc: devicetree, linux-pm, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Qiqi Wang, sirius.wang, vince-wl.liu, jh.hsu On 02/02/2026 07:48, irving.ch.lin wrote: > From: Irving-CH Lin <irving-ch.lin@mediatek.com> > > In MT8189 mminfra power domain, the bus protect policy separates > into two parts, one is set before subsys clocks enabled, and another > need to enable after subsys clocks enable. > > Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > drivers/pmdomain/mediatek/mtk-pm-domains.c | 31 ++++++++++++++++++---- > drivers/pmdomain/mediatek/mtk-pm-domains.h | 5 ++++ > 2 files changed, 31 insertions(+), 5 deletions(-) > > diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c > index 0f0662676c07..3eeb0dabf7d7 100644 > --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c > +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c > @@ -250,7 +250,7 @@ static int scpsys_bus_protect_set(struct scpsys_domain *pd, > MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); > } > > -static int scpsys_bus_protect_enable(struct scpsys_domain *pd) > +static int scpsys_bus_protect_enable(struct scpsys_domain *pd, u8 flags) > { > for (int i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) { > const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i]; > @@ -259,6 +259,10 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd) > if (!bpd->bus_prot_set_clr_mask) > break; > > + if ((bpd->flags & BUS_PROT_IGNORE_SUBCLK) != > + (flags & BUS_PROT_IGNORE_SUBCLK)) > + continue; > + > if (bpd->flags & BUS_PROT_INVERTED) > ret = scpsys_bus_protect_clear(pd, bpd); > else > @@ -270,7 +274,7 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd) > return 0; > } > > -static int scpsys_bus_protect_disable(struct scpsys_domain *pd) > +static int scpsys_bus_protect_disable(struct scpsys_domain *pd, u8 flags) > { > for (int i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) { > const struct scpsys_bus_prot_data *bpd = &pd->data->bp_cfg[i]; > @@ -279,6 +283,10 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd) > if (!bpd->bus_prot_set_clr_mask) > continue; > > + if ((bpd->flags & BUS_PROT_IGNORE_SUBCLK) != > + (flags & BUS_PROT_IGNORE_SUBCLK)) > + continue; > + > if (bpd->flags & BUS_PROT_INVERTED) > ret = scpsys_bus_protect_set(pd, bpd); > else > @@ -632,6 +640,15 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) > if (ret) > goto err_pwr_ack; > > + /* > + * In MT8189 mminfra power domain, the bus protect policy separates > + * into two parts, one is set before subsys clocks enabled, and another > + * need to enable after subsys clocks enable. > + */ > + ret = scpsys_bus_protect_disable(pd, BUS_PROT_IGNORE_SUBCLK); > + if (ret < 0) > + goto err_pwr_ack; > + > /* > * In few Mediatek platforms(e.g. MT6779), the bus protect policy is > * stricter, which leads to bus protect release must be prior to bus > @@ -648,7 +665,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) > if (ret < 0) > goto err_disable_subsys_clks; > > - ret = scpsys_bus_protect_disable(pd); > + ret = scpsys_bus_protect_disable(pd, 0); > if (ret < 0) > goto err_disable_sram; > > @@ -662,7 +679,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) > return 0; > > err_enable_bus_protect: > - scpsys_bus_protect_enable(pd); > + scpsys_bus_protect_enable(pd, 0); > err_disable_sram: > scpsys_sram_disable(pd); > err_disable_subsys_clks: > @@ -683,7 +700,7 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) > bool tmp; > int ret; > > - ret = scpsys_bus_protect_enable(pd); > + ret = scpsys_bus_protect_enable(pd, 0); > if (ret < 0) > return ret; > > @@ -697,6 +714,10 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) > > clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); > > + ret = scpsys_bus_protect_enable(pd, BUS_PROT_IGNORE_SUBCLK); > + if (ret < 0) > + return ret; > + > if (MTK_SCPD_CAPS(pd, MTK_SCPD_MODEM_PWRSEQ)) > scpsys_modem_pwrseq_off(pd); > else > diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h > index f608e6ec4744..a5dca24cbc2f 100644 > --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h > +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h > @@ -56,6 +56,7 @@ enum scpsys_bus_prot_flags { > BUS_PROT_REG_UPDATE = BIT(1), > BUS_PROT_IGNORE_CLR_ACK = BIT(2), > BUS_PROT_INVERTED = BIT(3), > + BUS_PROT_IGNORE_SUBCLK = BIT(4), > }; > > enum scpsys_bus_prot_block { > @@ -95,6 +96,10 @@ enum scpsys_bus_prot_block { > _BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \ > BUS_PROT_REG_UPDATE) > > +#define BUS_PROT_WR_IGN_SUBCLK(_hwip, _mask, _set, _clr, _sta) \ > + _BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \ > + BUS_PROT_IGNORE_CLR_ACK | BUS_PROT_IGNORE_SUBCLK) > + > #define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \ > BUS_PROT_UPDATE(INFRA, _mask, \ > INFRA_TOPAXI_PROTECTEN, \ ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/3] pmdomain: mediatek: Add power domain driver for MT8189 SoC 2026-02-02 6:48 [PATCH 0/3] Add support for MT8189 power controller irving.ch.lin 2026-02-02 6:48 ` [PATCH 1/3] dt-bindings: power: Add MediaTek MT8189 power domain irving.ch.lin 2026-02-02 6:48 ` [PATCH 2/3] pmdomain: mediatek: Add bus protect control flow for MT8189 irving.ch.lin @ 2026-02-02 6:48 ` irving.ch.lin 2026-02-02 12:02 ` AngeloGioacchino Del Regno 2026-02-04 17:47 ` Matthias Brugger 2026-02-02 14:59 ` [PATCH 0/3] Add support for MT8189 power controller Ulf Hansson 3 siblings, 2 replies; 11+ messages in thread From: irving.ch.lin @ 2026-02-02 6:48 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ulf Hansson, Matthias Brugger, AngeloGioacchino Del Regno Cc: Matthias Brugger, devicetree, linux-pm, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Qiqi Wang, sirius.wang, vince-wl.liu, jh.hsu, irving-ch.lin From: Irving-CH Lin <irving-ch.lin@mediatek.com> Introduce a new power domain (pmd) driver for the MediaTek mt8189 SoC. This driver ports and refines the power domain framework, dividing hardware blocks (CPU, GPU, peripherals, etc.) into independent power domains for precise and energy-efficient power management. Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com> --- drivers/pmdomain/mediatek/mt8189-pm-domains.h | 485 ++++++++++++++++++ drivers/pmdomain/mediatek/mtk-pm-domains.c | 5 + 2 files changed, 490 insertions(+) create mode 100644 drivers/pmdomain/mediatek/mt8189-pm-domains.h diff --git a/drivers/pmdomain/mediatek/mt8189-pm-domains.h b/drivers/pmdomain/mediatek/mt8189-pm-domains.h new file mode 100644 index 000000000000..c28b9460c074 --- /dev/null +++ b/drivers/pmdomain/mediatek/mt8189-pm-domains.h @@ -0,0 +1,485 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang <qiqi.wang@mediatek.com> + */ + +#ifndef __SOC_MEDIATEK_MT8189_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8189_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include <dt-bindings/power/mediatek,mt8189-power.h> + +/* + * MT8189 power domain support + */ + +#define MT8189_SPM_PWR_STATUS 0x0f40 +#define MT8189_SPM_PWR_STATUS_2ND 0x0f44 +#define MT8189_SPM_PWR_STATUS_MSB 0x0f48 +#define MT8189_SPM_PWR_STATUS_MSB_2ND 0x0f4c +#define MT8189_SPM_XPU_PWR_STATUS 0x0f50 +#define MT8189_SPM_XPU_PWR_STATUS_2ND 0x0f54 + +#define MT8189_PROT_EN_EMICFG_GALS_SLP_SET 0x0084 +#define MT8189_PROT_EN_EMICFG_GALS_SLP_CLR 0x0088 +#define MT8189_PROT_EN_EMICFG_GALS_SLP_RDY 0x008c +#define MT8189_PROT_EN_MMSYS_STA_0_SET 0x0c14 +#define MT8189_PROT_EN_MMSYS_STA_0_CLR 0x0c18 +#define MT8189_PROT_EN_MMSYS_STA_0_RDY 0x0c1c +#define MT8189_PROT_EN_MMSYS_STA_1_SET 0x0c24 +#define MT8189_PROT_EN_MMSYS_STA_1_CLR 0x0c28 +#define MT8189_PROT_EN_MMSYS_STA_1_RDY 0x0c2c +#define MT8189_PROT_EN_INFRASYS_STA_0_SET 0x0c44 +#define MT8189_PROT_EN_INFRASYS_STA_0_CLR 0x0c48 +#define MT8189_PROT_EN_INFRASYS_STA_0_RDY 0x0c4c +#define MT8189_PROT_EN_INFRASYS_STA_1_SET 0x0c54 +#define MT8189_PROT_EN_INFRASYS_STA_1_CLR 0x0c58 +#define MT8189_PROT_EN_INFRASYS_STA_1_RDY 0x0c5c +#define MT8189_PROT_EN_PERISYS_STA_0_SET 0x0c84 +#define MT8189_PROT_EN_PERISYS_STA_0_CLR 0x0c88 +#define MT8189_PROT_EN_PERISYS_STA_0_RDY 0x0c8c +#define MT8189_PROT_EN_MCU_STA_0_SET 0x0c94 +#define MT8189_PROT_EN_MCU_STA_0_CLR 0x0c98 +#define MT8189_PROT_EN_MCU_STA_0_RDY 0x0c9c +#define MT8189_PROT_EN_MD_STA_0_SET 0x0ca4 +#define MT8189_PROT_EN_MD_STA_0_CLR 0x0ca8 +#define MT8189_PROT_EN_MD_STA_0_RDY 0x0cac + +#define MT8189_PROT_EN_EMISYS_STA_0_MM_INFRA (GENMASK(21, 20)) +#define MT8189_PROT_EN_INFRASYS_STA_0_CONN (BIT(8)) +#define MT8189_PROT_EN_INFRASYS_STA_1_CONN (BIT(12)) +#define MT8189_PROT_EN_INFRASYS_STA_0_MM_INFRA (BIT(16)) +#define MT8189_PROT_EN_INFRASYS_STA_1_MM_INFRA (BIT(11)) +#define MT8189_PROT_EN_INFRASYS_STA_1_MFG1 (BIT(20)) +#define MT8189_PROT_EN_MCU_STA_0_CONN (BIT(1)) +#define MT8189_PROT_EN_MCU_STA_0_CONN_2ND (BIT(0)) +#define MT8189_PROT_EN_MD_STA_0_MFG1 (BIT(0) | BIT(2)) +#define MT8189_PROT_EN_MD_STA_0_MFG1_2ND (BIT(4)) +#define MT8189_PROT_EN_MM_INFRA_IGN (BIT(1)) +#define MT8189_PROT_EN_MM_INFRA_2_IGN (BIT(0)) +#define MT8189_PROT_EN_MMSYS_STA_0_CAM_MAIN (GENMASK(31, 30)) +#define MT8189_PROT_EN_MMSYS_STA_1_CAM_MAIN (GENMASK(10, 9)) +#define MT8189_PROT_EN_MMSYS_STA_0_DISP (GENMASK(1, 0)) +#define MT8189_PROT_EN_MMSYS_STA_0_ISP_IMG1 (BIT(3)) +#define MT8189_PROT_EN_MMSYS_STA_1_ISP_IMG1 (BIT(7)) +#define MT8189_PROT_EN_MMSYS_STA_0_ISP_IPE (BIT(2)) +#define MT8189_PROT_EN_MMSYS_STA_1_ISP_IPE (BIT(8)) +#define MT8189_PROT_EN_MMSYS_STA_0_MDP0 (BIT(18)) +#define MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA (GENMASK(3, 2)) +#define MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND (GENMASK(15, 7)) +#define MT8189_PROT_EN_MMSYS_STA_0_VDE0 (BIT(20)) +#define MT8189_PROT_EN_MMSYS_STA_1_VDE0 (BIT(13)) +#define MT8189_PROT_EN_MMSYS_STA_0_VEN0 (BIT(12)) +#define MT8189_PROT_EN_MMSYS_STA_1_VEN0 (BIT(12)) +#define MT8189_PROT_EN_PERISYS_STA_0_AUDIO (BIT(6)) +#define MT8189_PROT_EN_PERISYS_STA_0_SSUSB (BIT(7)) +#define MT8189_PROT_EN_EMICFG_GALS_SLP_MFG1 (GENMASK(5, 4)) + +static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8189[] = { + BUS_PROT_BLOCK_INFRA, BUS_PROT_BLOCK_SMI +}; + +static const struct scpsys_domain_data scpsys_domain_data_mt8189[] = { + [MT8189_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = BIT(1), + .ctl_offs = 0xe04, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MCU_STA_0_CONN, + MT8189_PROT_EN_MCU_STA_0_SET, + MT8189_PROT_EN_MCU_STA_0_CLR, + MT8189_PROT_EN_MCU_STA_0_RDY), + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_INFRASYS_STA_1_CONN, + MT8189_PROT_EN_INFRASYS_STA_1_SET, + MT8189_PROT_EN_INFRASYS_STA_1_CLR, + MT8189_PROT_EN_INFRASYS_STA_1_RDY), + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MCU_STA_0_CONN_2ND, + MT8189_PROT_EN_MCU_STA_0_SET, + MT8189_PROT_EN_MCU_STA_0_CLR, + MT8189_PROT_EN_MCU_STA_0_RDY), + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_INFRASYS_STA_0_CONN, + MT8189_PROT_EN_INFRASYS_STA_0_SET, + MT8189_PROT_EN_INFRASYS_STA_0_CLR, + MT8189_PROT_EN_INFRASYS_STA_0_RDY), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8189_POWER_DOMAIN_AUDIO] = { + .name = "audio", + .sta_mask = BIT(6), + .ctl_offs = 0xe18, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_PERISYS_STA_0_AUDIO, + MT8189_PROT_EN_PERISYS_STA_0_SET, + MT8189_PROT_EN_PERISYS_STA_0_CLR, + MT8189_PROT_EN_PERISYS_STA_0_RDY), + }, + }, + [MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT] = { + .name = "adsp-top-dormant", + .sta_mask = BIT(7), + .ctl_offs = 0xe1c, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(9), + .sram_pdn_ack_bits = BIT(13), + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_PDN_INVERTED | + MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8189_POWER_DOMAIN_ADSP_INFRA] = { + .name = "adsp-infra", + .sta_mask = BIT(8), + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, + .ctl_offs = 0xe20, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8189_POWER_DOMAIN_ADSP_AO] = { + .name = "adsp-ao", + .sta_mask = BIT(9), + .ctl_offs = 0xe24, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, + }, + [MT8189_POWER_DOMAIN_ISP_IMG1] = { + .name = "isp-img1", + .sta_mask = BIT(10), + .ctl_offs = 0xe28, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MMSYS_STA_0_ISP_IMG1, + MT8189_PROT_EN_MMSYS_STA_0_SET, + MT8189_PROT_EN_MMSYS_STA_0_CLR, + MT8189_PROT_EN_MMSYS_STA_0_RDY), + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MMSYS_STA_1_ISP_IMG1, + MT8189_PROT_EN_MMSYS_STA_1_SET, + MT8189_PROT_EN_MMSYS_STA_1_CLR, + MT8189_PROT_EN_MMSYS_STA_1_RDY), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8189_POWER_DOMAIN_ISP_IMG2] = { + .name = "isp-img2", + .sta_mask = BIT(11), + .ctl_offs = 0xe2c, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8189_POWER_DOMAIN_ISP_IPE] = { + .name = "isp-ipe", + .sta_mask = BIT(12), + .ctl_offs = 0xe30, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MMSYS_STA_0_ISP_IPE, + MT8189_PROT_EN_MMSYS_STA_0_SET, + MT8189_PROT_EN_MMSYS_STA_0_CLR, + MT8189_PROT_EN_MMSYS_STA_0_RDY), + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MMSYS_STA_1_ISP_IPE, + MT8189_PROT_EN_MMSYS_STA_1_SET, + MT8189_PROT_EN_MMSYS_STA_1_CLR, + MT8189_PROT_EN_MMSYS_STA_1_RDY), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8189_POWER_DOMAIN_VDE0] = { + .name = "vde0", + .sta_mask = BIT(14), + .ctl_offs = 0xe38, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MMSYS_STA_0_VDE0, + MT8189_PROT_EN_MMSYS_STA_0_SET, + MT8189_PROT_EN_MMSYS_STA_0_CLR, + MT8189_PROT_EN_MMSYS_STA_0_RDY), + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MMSYS_STA_1_VDE0, + MT8189_PROT_EN_MMSYS_STA_1_SET, + MT8189_PROT_EN_MMSYS_STA_1_CLR, + MT8189_PROT_EN_MMSYS_STA_1_RDY), + }, + }, + [MT8189_POWER_DOMAIN_VEN0] = { + .name = "ven0", + .sta_mask = BIT(16), + .ctl_offs = 0xe40, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MMSYS_STA_0_VEN0, + MT8189_PROT_EN_MMSYS_STA_0_SET, + MT8189_PROT_EN_MMSYS_STA_0_CLR, + MT8189_PROT_EN_MMSYS_STA_0_RDY), + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MMSYS_STA_1_VEN0, + MT8189_PROT_EN_MMSYS_STA_1_SET, + MT8189_PROT_EN_MMSYS_STA_1_CLR, + MT8189_PROT_EN_MMSYS_STA_1_RDY), + }, + }, + [MT8189_POWER_DOMAIN_CAM_MAIN] = { + .name = "cam-main", + .sta_mask = BIT(18), + .ctl_offs = 0xe48, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MMSYS_STA_0_CAM_MAIN, + MT8189_PROT_EN_MMSYS_STA_0_SET, + MT8189_PROT_EN_MMSYS_STA_0_CLR, + MT8189_PROT_EN_MMSYS_STA_0_RDY), + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MMSYS_STA_1_CAM_MAIN, + MT8189_PROT_EN_MMSYS_STA_1_SET, + MT8189_PROT_EN_MMSYS_STA_1_CLR, + MT8189_PROT_EN_MMSYS_STA_1_RDY), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8189_POWER_DOMAIN_CAM_SUBA] = { + .name = "cam-suba", + .sta_mask = BIT(20), + .ctl_offs = 0xe50, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8189_POWER_DOMAIN_CAM_SUBB] = { + .name = "cam-subb", + .sta_mask = BIT(21), + .ctl_offs = 0xe54, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8189_POWER_DOMAIN_MDP0] = { + .name = "mdp0", + .sta_mask = BIT(26), + .ctl_offs = 0xe68, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MMSYS_STA_0_MDP0, + MT8189_PROT_EN_MMSYS_STA_0_SET, + MT8189_PROT_EN_MMSYS_STA_0_CLR, + MT8189_PROT_EN_MMSYS_STA_0_RDY), + }, + }, + [MT8189_POWER_DOMAIN_DISP] = { + .name = "disp", + .sta_mask = BIT(28), + .ctl_offs = 0xe70, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MMSYS_STA_0_DISP, + MT8189_PROT_EN_MMSYS_STA_0_SET, + MT8189_PROT_EN_MMSYS_STA_0_CLR, + MT8189_PROT_EN_MMSYS_STA_0_RDY), + }, + }, + [MT8189_POWER_DOMAIN_MM_INFRA] = { + .name = "mm-infra", + .sta_mask = BIT(30), + .ctl_offs = 0xe78, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA, + MT8189_PROT_EN_MMSYS_STA_1_SET, + MT8189_PROT_EN_MMSYS_STA_1_CLR, + MT8189_PROT_EN_MMSYS_STA_1_RDY), + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND, + MT8189_PROT_EN_MMSYS_STA_1_SET, + MT8189_PROT_EN_MMSYS_STA_1_CLR, + MT8189_PROT_EN_MMSYS_STA_1_RDY), + BUS_PROT_WR_IGN_SUBCLK(INFRA, + MT8189_PROT_EN_MM_INFRA_IGN, + MT8189_PROT_EN_MMSYS_STA_1_SET, + MT8189_PROT_EN_MMSYS_STA_1_CLR, + MT8189_PROT_EN_MMSYS_STA_1_RDY), + BUS_PROT_WR_IGN_SUBCLK(INFRA, + MT8189_PROT_EN_MM_INFRA_2_IGN, + MT8189_PROT_EN_MMSYS_STA_1_SET, + MT8189_PROT_EN_MMSYS_STA_1_CLR, + MT8189_PROT_EN_MMSYS_STA_1_RDY), + }, + }, + [MT8189_POWER_DOMAIN_DP_TX] = { + .name = "dp-tx", + .sta_mask = BIT(0), + .ctl_offs = 0xe80, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + }, + [MT8189_POWER_DOMAIN_CSI_RX] = { + .name = "csi-rx", + .sta_mask = BIT(7), + .ctl_offs = 0xe9c, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8189_POWER_DOMAIN_SSUSB] = { + .name = "ssusb", + .sta_mask = BIT(10), + .ctl_offs = 0xea8, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_PERISYS_STA_0_SSUSB, + MT8189_PROT_EN_PERISYS_STA_0_SET, + MT8189_PROT_EN_PERISYS_STA_0_CLR, + MT8189_PROT_EN_PERISYS_STA_0_RDY), + }, + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8189_POWER_DOMAIN_MFG0] = { + .name = "mfg0", + .sta_mask = BIT(1), + .ctl_offs = 0xeb4, + .pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND, + .caps = MTK_SCPD_DOMAIN_SUPPLY, + }, + [MT8189_POWER_DOMAIN_MFG1] = { + .name = "mfg1", + .sta_mask = BIT(2), + .ctl_offs = 0xeb8, + .pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_cfg = { + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_INFRASYS_STA_1_MFG1, + MT8189_PROT_EN_INFRASYS_STA_1_SET, + MT8189_PROT_EN_INFRASYS_STA_1_CLR, + MT8189_PROT_EN_INFRASYS_STA_1_RDY), + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MD_STA_0_MFG1, + MT8189_PROT_EN_MD_STA_0_SET, + MT8189_PROT_EN_MD_STA_0_CLR, + MT8189_PROT_EN_MD_STA_0_RDY), + BUS_PROT_WR_IGN(INFRA, + MT8189_PROT_EN_MD_STA_0_MFG1_2ND, + MT8189_PROT_EN_MD_STA_0_SET, + MT8189_PROT_EN_MD_STA_0_CLR, + MT8189_PROT_EN_MD_STA_0_RDY), + BUS_PROT_WR_IGN(SMI, + MT8189_PROT_EN_EMICFG_GALS_SLP_MFG1, + MT8189_PROT_EN_EMICFG_GALS_SLP_SET, + MT8189_PROT_EN_EMICFG_GALS_SLP_CLR, + MT8189_PROT_EN_EMICFG_GALS_SLP_RDY), + }, + .caps = MTK_SCPD_DOMAIN_SUPPLY, + }, + [MT8189_POWER_DOMAIN_MFG2] = { + .name = "mfg2", + .sta_mask = BIT(3), + .ctl_offs = 0xebc, + .pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + }, + [MT8189_POWER_DOMAIN_MFG3] = { + .name = "mfg3", + .sta_mask = BIT(4), + .ctl_offs = 0xec0, + .pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS, + .pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + }, + [MT8189_POWER_DOMAIN_EDP_TX_DORMANT] = { + .name = "edp-tx-dormant", + .sta_mask = BIT(12), + .ctl_offs = 0xf70, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, + .sram_pdn_bits = BIT(9), + .sram_pdn_ack_bits = 0, + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_PDN_INVERTED, + }, + [MT8189_POWER_DOMAIN_PCIE] = { + .name = "pcie", + .sta_mask = BIT(13), + .ctl_offs = 0xf74, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8189_POWER_DOMAIN_PCIE_PHY] = { + .name = "pcie-phy", + .sta_mask = BIT(14), + .ctl_offs = 0xf78, + .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, + }, +}; + +static const struct scpsys_soc_data mt8189_scpsys_data = { + .domains_data = scpsys_domain_data_mt8189, + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8189), + .bus_prot_blocks = scpsys_bus_prot_blocks_mt8189, + .num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt8189), +}; + +#endif /* __SOC_MEDIATEK_MT8189_PM_DOMAINS_H */ diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c index 3eeb0dabf7d7..58648f4f689b 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -26,6 +26,7 @@ #include "mt8183-pm-domains.h" #include "mt8186-pm-domains.h" #include "mt8188-pm-domains.h" +#include "mt8189-pm-domains.h" #include "mt8192-pm-domains.h" #include "mt8195-pm-domains.h" #include "mt8196-pm-domains.h" @@ -1171,6 +1172,10 @@ static const struct of_device_id scpsys_of_match[] = { .compatible = "mediatek,mt8188-power-controller", .data = &mt8188_scpsys_data, }, + { + .compatible = "mediatek,mt8189-power-controller", + .data = &mt8189_scpsys_data, + }, { .compatible = "mediatek,mt8192-power-controller", .data = &mt8192_scpsys_data, -- 2.45.2 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] pmdomain: mediatek: Add power domain driver for MT8189 SoC 2026-02-02 6:48 ` [PATCH 3/3] pmdomain: mediatek: Add power domain driver for MT8189 SoC irving.ch.lin @ 2026-02-02 12:02 ` AngeloGioacchino Del Regno 2026-02-04 17:47 ` Matthias Brugger 1 sibling, 0 replies; 11+ messages in thread From: AngeloGioacchino Del Regno @ 2026-02-02 12:02 UTC (permalink / raw) To: irving.ch.lin, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ulf Hansson, Matthias Brugger Cc: Matthias Brugger, devicetree, linux-pm, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Qiqi Wang, sirius.wang, vince-wl.liu, jh.hsu Il 02/02/26 07:48, irving.ch.lin ha scritto: > From: Irving-CH Lin <irving-ch.lin@mediatek.com> > > Introduce a new power domain (pmd) driver for the MediaTek mt8189 SoC. > This driver ports and refines the power domain framework, dividing > hardware blocks (CPU, GPU, peripherals, etc.) into independent power > domains for precise and energy-efficient power management. > > Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] pmdomain: mediatek: Add power domain driver for MT8189 SoC 2026-02-02 6:48 ` [PATCH 3/3] pmdomain: mediatek: Add power domain driver for MT8189 SoC irving.ch.lin 2026-02-02 12:02 ` AngeloGioacchino Del Regno @ 2026-02-04 17:47 ` Matthias Brugger 1 sibling, 0 replies; 11+ messages in thread From: Matthias Brugger @ 2026-02-04 17:47 UTC (permalink / raw) To: irving.ch.lin, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ulf Hansson, Matthias Brugger, AngeloGioacchino Del Regno Cc: devicetree, linux-pm, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Qiqi Wang, sirius.wang, vince-wl.liu, jh.hsu On 02/02/2026 07:48, irving.ch.lin wrote: > From: Irving-CH Lin <irving-ch.lin@mediatek.com> > > Introduce a new power domain (pmd) driver for the MediaTek mt8189 SoC. > This driver ports and refines the power domain framework, dividing > hardware blocks (CPU, GPU, peripherals, etc.) into independent power > domains for precise and energy-efficient power management. > > Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > drivers/pmdomain/mediatek/mt8189-pm-domains.h | 485 ++++++++++++++++++ > drivers/pmdomain/mediatek/mtk-pm-domains.c | 5 + > 2 files changed, 490 insertions(+) > create mode 100644 drivers/pmdomain/mediatek/mt8189-pm-domains.h > > diff --git a/drivers/pmdomain/mediatek/mt8189-pm-domains.h b/drivers/pmdomain/mediatek/mt8189-pm-domains.h > new file mode 100644 > index 000000000000..c28b9460c074 > --- /dev/null > +++ b/drivers/pmdomain/mediatek/mt8189-pm-domains.h > @@ -0,0 +1,485 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2025 MediaTek Inc. > + * Author: Qiqi Wang <qiqi.wang@mediatek.com> > + */ > + > +#ifndef __SOC_MEDIATEK_MT8189_PM_DOMAINS_H > +#define __SOC_MEDIATEK_MT8189_PM_DOMAINS_H > + > +#include "mtk-pm-domains.h" > +#include <dt-bindings/power/mediatek,mt8189-power.h> > + > +/* > + * MT8189 power domain support > + */ > + > +#define MT8189_SPM_PWR_STATUS 0x0f40 > +#define MT8189_SPM_PWR_STATUS_2ND 0x0f44 > +#define MT8189_SPM_PWR_STATUS_MSB 0x0f48 > +#define MT8189_SPM_PWR_STATUS_MSB_2ND 0x0f4c > +#define MT8189_SPM_XPU_PWR_STATUS 0x0f50 > +#define MT8189_SPM_XPU_PWR_STATUS_2ND 0x0f54 > + > +#define MT8189_PROT_EN_EMICFG_GALS_SLP_SET 0x0084 > +#define MT8189_PROT_EN_EMICFG_GALS_SLP_CLR 0x0088 > +#define MT8189_PROT_EN_EMICFG_GALS_SLP_RDY 0x008c > +#define MT8189_PROT_EN_MMSYS_STA_0_SET 0x0c14 > +#define MT8189_PROT_EN_MMSYS_STA_0_CLR 0x0c18 > +#define MT8189_PROT_EN_MMSYS_STA_0_RDY 0x0c1c > +#define MT8189_PROT_EN_MMSYS_STA_1_SET 0x0c24 > +#define MT8189_PROT_EN_MMSYS_STA_1_CLR 0x0c28 > +#define MT8189_PROT_EN_MMSYS_STA_1_RDY 0x0c2c > +#define MT8189_PROT_EN_INFRASYS_STA_0_SET 0x0c44 > +#define MT8189_PROT_EN_INFRASYS_STA_0_CLR 0x0c48 > +#define MT8189_PROT_EN_INFRASYS_STA_0_RDY 0x0c4c > +#define MT8189_PROT_EN_INFRASYS_STA_1_SET 0x0c54 > +#define MT8189_PROT_EN_INFRASYS_STA_1_CLR 0x0c58 > +#define MT8189_PROT_EN_INFRASYS_STA_1_RDY 0x0c5c > +#define MT8189_PROT_EN_PERISYS_STA_0_SET 0x0c84 > +#define MT8189_PROT_EN_PERISYS_STA_0_CLR 0x0c88 > +#define MT8189_PROT_EN_PERISYS_STA_0_RDY 0x0c8c > +#define MT8189_PROT_EN_MCU_STA_0_SET 0x0c94 > +#define MT8189_PROT_EN_MCU_STA_0_CLR 0x0c98 > +#define MT8189_PROT_EN_MCU_STA_0_RDY 0x0c9c > +#define MT8189_PROT_EN_MD_STA_0_SET 0x0ca4 > +#define MT8189_PROT_EN_MD_STA_0_CLR 0x0ca8 > +#define MT8189_PROT_EN_MD_STA_0_RDY 0x0cac > + > +#define MT8189_PROT_EN_EMISYS_STA_0_MM_INFRA (GENMASK(21, 20)) > +#define MT8189_PROT_EN_INFRASYS_STA_0_CONN (BIT(8)) > +#define MT8189_PROT_EN_INFRASYS_STA_1_CONN (BIT(12)) > +#define MT8189_PROT_EN_INFRASYS_STA_0_MM_INFRA (BIT(16)) > +#define MT8189_PROT_EN_INFRASYS_STA_1_MM_INFRA (BIT(11)) > +#define MT8189_PROT_EN_INFRASYS_STA_1_MFG1 (BIT(20)) > +#define MT8189_PROT_EN_MCU_STA_0_CONN (BIT(1)) > +#define MT8189_PROT_EN_MCU_STA_0_CONN_2ND (BIT(0)) > +#define MT8189_PROT_EN_MD_STA_0_MFG1 (BIT(0) | BIT(2)) > +#define MT8189_PROT_EN_MD_STA_0_MFG1_2ND (BIT(4)) > +#define MT8189_PROT_EN_MM_INFRA_IGN (BIT(1)) > +#define MT8189_PROT_EN_MM_INFRA_2_IGN (BIT(0)) > +#define MT8189_PROT_EN_MMSYS_STA_0_CAM_MAIN (GENMASK(31, 30)) > +#define MT8189_PROT_EN_MMSYS_STA_1_CAM_MAIN (GENMASK(10, 9)) > +#define MT8189_PROT_EN_MMSYS_STA_0_DISP (GENMASK(1, 0)) > +#define MT8189_PROT_EN_MMSYS_STA_0_ISP_IMG1 (BIT(3)) > +#define MT8189_PROT_EN_MMSYS_STA_1_ISP_IMG1 (BIT(7)) > +#define MT8189_PROT_EN_MMSYS_STA_0_ISP_IPE (BIT(2)) > +#define MT8189_PROT_EN_MMSYS_STA_1_ISP_IPE (BIT(8)) > +#define MT8189_PROT_EN_MMSYS_STA_0_MDP0 (BIT(18)) > +#define MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA (GENMASK(3, 2)) > +#define MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND (GENMASK(15, 7)) > +#define MT8189_PROT_EN_MMSYS_STA_0_VDE0 (BIT(20)) > +#define MT8189_PROT_EN_MMSYS_STA_1_VDE0 (BIT(13)) > +#define MT8189_PROT_EN_MMSYS_STA_0_VEN0 (BIT(12)) > +#define MT8189_PROT_EN_MMSYS_STA_1_VEN0 (BIT(12)) > +#define MT8189_PROT_EN_PERISYS_STA_0_AUDIO (BIT(6)) > +#define MT8189_PROT_EN_PERISYS_STA_0_SSUSB (BIT(7)) > +#define MT8189_PROT_EN_EMICFG_GALS_SLP_MFG1 (GENMASK(5, 4)) > + > +static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8189[] = { > + BUS_PROT_BLOCK_INFRA, BUS_PROT_BLOCK_SMI > +}; > + > +static const struct scpsys_domain_data scpsys_domain_data_mt8189[] = { > + [MT8189_POWER_DOMAIN_CONN] = { > + .name = "conn", > + .sta_mask = BIT(1), > + .ctl_offs = 0xe04, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, > + .bp_cfg = { > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MCU_STA_0_CONN, > + MT8189_PROT_EN_MCU_STA_0_SET, > + MT8189_PROT_EN_MCU_STA_0_CLR, > + MT8189_PROT_EN_MCU_STA_0_RDY), > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_INFRASYS_STA_1_CONN, > + MT8189_PROT_EN_INFRASYS_STA_1_SET, > + MT8189_PROT_EN_INFRASYS_STA_1_CLR, > + MT8189_PROT_EN_INFRASYS_STA_1_RDY), > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MCU_STA_0_CONN_2ND, > + MT8189_PROT_EN_MCU_STA_0_SET, > + MT8189_PROT_EN_MCU_STA_0_CLR, > + MT8189_PROT_EN_MCU_STA_0_RDY), > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_INFRASYS_STA_0_CONN, > + MT8189_PROT_EN_INFRASYS_STA_0_SET, > + MT8189_PROT_EN_INFRASYS_STA_0_CLR, > + MT8189_PROT_EN_INFRASYS_STA_0_RDY), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8189_POWER_DOMAIN_AUDIO] = { > + .name = "audio", > + .sta_mask = BIT(6), > + .ctl_offs = 0xe18, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_PERISYS_STA_0_AUDIO, > + MT8189_PROT_EN_PERISYS_STA_0_SET, > + MT8189_PROT_EN_PERISYS_STA_0_CLR, > + MT8189_PROT_EN_PERISYS_STA_0_RDY), > + }, > + }, > + [MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT] = { > + .name = "adsp-top-dormant", > + .sta_mask = BIT(7), > + .ctl_offs = 0xe1c, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, > + .sram_pdn_bits = BIT(9), > + .sram_pdn_ack_bits = BIT(13), > + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_PDN_INVERTED | > + MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8189_POWER_DOMAIN_ADSP_INFRA] = { > + .name = "adsp-infra", > + .sta_mask = BIT(8), > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, > + .ctl_offs = 0xe20, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8189_POWER_DOMAIN_ADSP_AO] = { > + .name = "adsp-ao", > + .sta_mask = BIT(9), > + .ctl_offs = 0xe24, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, > + }, > + [MT8189_POWER_DOMAIN_ISP_IMG1] = { > + .name = "isp-img1", > + .sta_mask = BIT(10), > + .ctl_offs = 0xe28, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MMSYS_STA_0_ISP_IMG1, > + MT8189_PROT_EN_MMSYS_STA_0_SET, > + MT8189_PROT_EN_MMSYS_STA_0_CLR, > + MT8189_PROT_EN_MMSYS_STA_0_RDY), > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MMSYS_STA_1_ISP_IMG1, > + MT8189_PROT_EN_MMSYS_STA_1_SET, > + MT8189_PROT_EN_MMSYS_STA_1_CLR, > + MT8189_PROT_EN_MMSYS_STA_1_RDY), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8189_POWER_DOMAIN_ISP_IMG2] = { > + .name = "isp-img2", > + .sta_mask = BIT(11), > + .ctl_offs = 0xe2c, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8189_POWER_DOMAIN_ISP_IPE] = { > + .name = "isp-ipe", > + .sta_mask = BIT(12), > + .ctl_offs = 0xe30, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MMSYS_STA_0_ISP_IPE, > + MT8189_PROT_EN_MMSYS_STA_0_SET, > + MT8189_PROT_EN_MMSYS_STA_0_CLR, > + MT8189_PROT_EN_MMSYS_STA_0_RDY), > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MMSYS_STA_1_ISP_IPE, > + MT8189_PROT_EN_MMSYS_STA_1_SET, > + MT8189_PROT_EN_MMSYS_STA_1_CLR, > + MT8189_PROT_EN_MMSYS_STA_1_RDY), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8189_POWER_DOMAIN_VDE0] = { > + .name = "vde0", > + .sta_mask = BIT(14), > + .ctl_offs = 0xe38, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MMSYS_STA_0_VDE0, > + MT8189_PROT_EN_MMSYS_STA_0_SET, > + MT8189_PROT_EN_MMSYS_STA_0_CLR, > + MT8189_PROT_EN_MMSYS_STA_0_RDY), > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MMSYS_STA_1_VDE0, > + MT8189_PROT_EN_MMSYS_STA_1_SET, > + MT8189_PROT_EN_MMSYS_STA_1_CLR, > + MT8189_PROT_EN_MMSYS_STA_1_RDY), > + }, > + }, > + [MT8189_POWER_DOMAIN_VEN0] = { > + .name = "ven0", > + .sta_mask = BIT(16), > + .ctl_offs = 0xe40, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MMSYS_STA_0_VEN0, > + MT8189_PROT_EN_MMSYS_STA_0_SET, > + MT8189_PROT_EN_MMSYS_STA_0_CLR, > + MT8189_PROT_EN_MMSYS_STA_0_RDY), > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MMSYS_STA_1_VEN0, > + MT8189_PROT_EN_MMSYS_STA_1_SET, > + MT8189_PROT_EN_MMSYS_STA_1_CLR, > + MT8189_PROT_EN_MMSYS_STA_1_RDY), > + }, > + }, > + [MT8189_POWER_DOMAIN_CAM_MAIN] = { > + .name = "cam-main", > + .sta_mask = BIT(18), > + .ctl_offs = 0xe48, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MMSYS_STA_0_CAM_MAIN, > + MT8189_PROT_EN_MMSYS_STA_0_SET, > + MT8189_PROT_EN_MMSYS_STA_0_CLR, > + MT8189_PROT_EN_MMSYS_STA_0_RDY), > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MMSYS_STA_1_CAM_MAIN, > + MT8189_PROT_EN_MMSYS_STA_1_SET, > + MT8189_PROT_EN_MMSYS_STA_1_CLR, > + MT8189_PROT_EN_MMSYS_STA_1_RDY), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8189_POWER_DOMAIN_CAM_SUBA] = { > + .name = "cam-suba", > + .sta_mask = BIT(20), > + .ctl_offs = 0xe50, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8189_POWER_DOMAIN_CAM_SUBB] = { > + .name = "cam-subb", > + .sta_mask = BIT(21), > + .ctl_offs = 0xe54, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8189_POWER_DOMAIN_MDP0] = { > + .name = "mdp0", > + .sta_mask = BIT(26), > + .ctl_offs = 0xe68, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MMSYS_STA_0_MDP0, > + MT8189_PROT_EN_MMSYS_STA_0_SET, > + MT8189_PROT_EN_MMSYS_STA_0_CLR, > + MT8189_PROT_EN_MMSYS_STA_0_RDY), > + }, > + }, > + [MT8189_POWER_DOMAIN_DISP] = { > + .name = "disp", > + .sta_mask = BIT(28), > + .ctl_offs = 0xe70, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MMSYS_STA_0_DISP, > + MT8189_PROT_EN_MMSYS_STA_0_SET, > + MT8189_PROT_EN_MMSYS_STA_0_CLR, > + MT8189_PROT_EN_MMSYS_STA_0_RDY), > + }, > + }, > + [MT8189_POWER_DOMAIN_MM_INFRA] = { > + .name = "mm-infra", > + .sta_mask = BIT(30), > + .ctl_offs = 0xe78, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA, > + MT8189_PROT_EN_MMSYS_STA_1_SET, > + MT8189_PROT_EN_MMSYS_STA_1_CLR, > + MT8189_PROT_EN_MMSYS_STA_1_RDY), > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MMSYS_STA_1_MM_INFRA_2ND, > + MT8189_PROT_EN_MMSYS_STA_1_SET, > + MT8189_PROT_EN_MMSYS_STA_1_CLR, > + MT8189_PROT_EN_MMSYS_STA_1_RDY), > + BUS_PROT_WR_IGN_SUBCLK(INFRA, > + MT8189_PROT_EN_MM_INFRA_IGN, > + MT8189_PROT_EN_MMSYS_STA_1_SET, > + MT8189_PROT_EN_MMSYS_STA_1_CLR, > + MT8189_PROT_EN_MMSYS_STA_1_RDY), > + BUS_PROT_WR_IGN_SUBCLK(INFRA, > + MT8189_PROT_EN_MM_INFRA_2_IGN, > + MT8189_PROT_EN_MMSYS_STA_1_SET, > + MT8189_PROT_EN_MMSYS_STA_1_CLR, > + MT8189_PROT_EN_MMSYS_STA_1_RDY), > + }, > + }, > + [MT8189_POWER_DOMAIN_DP_TX] = { > + .name = "dp-tx", > + .sta_mask = BIT(0), > + .ctl_offs = 0xe80, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + }, > + [MT8189_POWER_DOMAIN_CSI_RX] = { > + .name = "csi-rx", > + .sta_mask = BIT(7), > + .ctl_offs = 0xe9c, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8189_POWER_DOMAIN_SSUSB] = { > + .name = "ssusb", > + .sta_mask = BIT(10), > + .ctl_offs = 0xea8, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_PERISYS_STA_0_SSUSB, > + MT8189_PROT_EN_PERISYS_STA_0_SET, > + MT8189_PROT_EN_PERISYS_STA_0_CLR, > + MT8189_PROT_EN_PERISYS_STA_0_RDY), > + }, > + .caps = MTK_SCPD_ACTIVE_WAKEUP, > + }, > + [MT8189_POWER_DOMAIN_MFG0] = { > + .name = "mfg0", > + .sta_mask = BIT(1), > + .ctl_offs = 0xeb4, > + .pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND, > + .caps = MTK_SCPD_DOMAIN_SUPPLY, > + }, > + [MT8189_POWER_DOMAIN_MFG1] = { > + .name = "mfg1", > + .sta_mask = BIT(2), > + .ctl_offs = 0xeb8, > + .pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .bp_cfg = { > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_INFRASYS_STA_1_MFG1, > + MT8189_PROT_EN_INFRASYS_STA_1_SET, > + MT8189_PROT_EN_INFRASYS_STA_1_CLR, > + MT8189_PROT_EN_INFRASYS_STA_1_RDY), > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MD_STA_0_MFG1, > + MT8189_PROT_EN_MD_STA_0_SET, > + MT8189_PROT_EN_MD_STA_0_CLR, > + MT8189_PROT_EN_MD_STA_0_RDY), > + BUS_PROT_WR_IGN(INFRA, > + MT8189_PROT_EN_MD_STA_0_MFG1_2ND, > + MT8189_PROT_EN_MD_STA_0_SET, > + MT8189_PROT_EN_MD_STA_0_CLR, > + MT8189_PROT_EN_MD_STA_0_RDY), > + BUS_PROT_WR_IGN(SMI, > + MT8189_PROT_EN_EMICFG_GALS_SLP_MFG1, > + MT8189_PROT_EN_EMICFG_GALS_SLP_SET, > + MT8189_PROT_EN_EMICFG_GALS_SLP_CLR, > + MT8189_PROT_EN_EMICFG_GALS_SLP_RDY), > + }, > + .caps = MTK_SCPD_DOMAIN_SUPPLY, > + }, > + [MT8189_POWER_DOMAIN_MFG2] = { > + .name = "mfg2", > + .sta_mask = BIT(3), > + .ctl_offs = 0xebc, > + .pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + }, > + [MT8189_POWER_DOMAIN_MFG3] = { > + .name = "mfg3", > + .sta_mask = BIT(4), > + .ctl_offs = 0xec0, > + .pwr_sta_offs = MT8189_SPM_XPU_PWR_STATUS, > + .pwr_sta2nd_offs = MT8189_SPM_XPU_PWR_STATUS_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + }, > + [MT8189_POWER_DOMAIN_EDP_TX_DORMANT] = { > + .name = "edp-tx-dormant", > + .sta_mask = BIT(12), > + .ctl_offs = 0xf70, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, > + .sram_pdn_bits = BIT(9), > + .sram_pdn_ack_bits = 0, > + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_PDN_INVERTED, > + }, > + [MT8189_POWER_DOMAIN_PCIE] = { > + .name = "pcie", > + .sta_mask = BIT(13), > + .ctl_offs = 0xf74, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, > + .sram_pdn_bits = BIT(8), > + .sram_pdn_ack_bits = BIT(12), > + .caps = MTK_SCPD_ACTIVE_WAKEUP, > + }, > + [MT8189_POWER_DOMAIN_PCIE_PHY] = { > + .name = "pcie-phy", > + .sta_mask = BIT(14), > + .ctl_offs = 0xf78, > + .pwr_sta_offs = MT8189_SPM_PWR_STATUS_MSB, > + .pwr_sta2nd_offs = MT8189_SPM_PWR_STATUS_MSB_2ND, > + }, > +}; > + > +static const struct scpsys_soc_data mt8189_scpsys_data = { > + .domains_data = scpsys_domain_data_mt8189, > + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8189), > + .bus_prot_blocks = scpsys_bus_prot_blocks_mt8189, > + .num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt8189), > +}; > + > +#endif /* __SOC_MEDIATEK_MT8189_PM_DOMAINS_H */ > diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c > index 3eeb0dabf7d7..58648f4f689b 100644 > --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c > +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c > @@ -26,6 +26,7 @@ > #include "mt8183-pm-domains.h" > #include "mt8186-pm-domains.h" > #include "mt8188-pm-domains.h" > +#include "mt8189-pm-domains.h" > #include "mt8192-pm-domains.h" > #include "mt8195-pm-domains.h" > #include "mt8196-pm-domains.h" > @@ -1171,6 +1172,10 @@ static const struct of_device_id scpsys_of_match[] = { > .compatible = "mediatek,mt8188-power-controller", > .data = &mt8188_scpsys_data, > }, > + { > + .compatible = "mediatek,mt8189-power-controller", > + .data = &mt8189_scpsys_data, > + }, > { > .compatible = "mediatek,mt8192-power-controller", > .data = &mt8192_scpsys_data, ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 0/3] Add support for MT8189 power controller 2026-02-02 6:48 [PATCH 0/3] Add support for MT8189 power controller irving.ch.lin ` (2 preceding siblings ...) 2026-02-02 6:48 ` [PATCH 3/3] pmdomain: mediatek: Add power domain driver for MT8189 SoC irving.ch.lin @ 2026-02-02 14:59 ` Ulf Hansson 3 siblings, 0 replies; 11+ messages in thread From: Ulf Hansson @ 2026-02-02 14:59 UTC (permalink / raw) To: irving.ch.lin Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, Matthias Brugger, devicetree, linux-pm, linux-arm-kernel, linux-mediatek, Project_Global_Chrome_Upstream_Group, Qiqi Wang, sirius.wang, vince-wl.liu, jh.hsu On Mon, 2 Feb 2026 at 07:48, irving.ch.lin <irving-ch.lin@mediatek.com> wrote: > > From: Irving-CH Lin <irving-ch.lin@mediatek.com> > > This series add support for the power controllers > of MediaTek's new SoC, MT8189. With these changes, other modules > can easily manage power resources using standard Linux APIs, > such as the pm_runtime API on MT8189 platform. > > Irving-CH Lin (3): > dt-bindings: power: Add MediaTek MT8189 power domain > pmdomain: mediatek: Add bus protect control flow for MT8189 > pmdomain: mediatek: Add power domain driver for MT8189 SoC > > .../power/mediatek,power-controller.yaml | 1 + > drivers/pmdomain/mediatek/mt8189-pm-domains.h | 485 ++++++++++++++++++ > drivers/pmdomain/mediatek/mtk-pm-domains.c | 36 +- > drivers/pmdomain/mediatek/mtk-pm-domains.h | 5 + > .../dt-bindings/power/mediatek,mt8189-power.h | 38 ++ > 5 files changed, 560 insertions(+), 5 deletions(-) > create mode 100644 drivers/pmdomain/mediatek/mt8189-pm-domains.h > create mode 100644 include/dt-bindings/power/mediatek,mt8189-power.h > > -- > 2.45.2 > The series applied for next, thanks! Kind regards Uffe ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2026-02-04 17:47 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-02-02 6:48 [PATCH 0/3] Add support for MT8189 power controller irving.ch.lin 2026-02-02 6:48 ` [PATCH 1/3] dt-bindings: power: Add MediaTek MT8189 power domain irving.ch.lin 2026-02-02 12:02 ` AngeloGioacchino Del Regno 2026-02-04 17:44 ` Matthias Brugger 2026-02-02 6:48 ` [PATCH 2/3] pmdomain: mediatek: Add bus protect control flow for MT8189 irving.ch.lin 2026-02-02 12:02 ` AngeloGioacchino Del Regno 2026-02-04 17:46 ` Matthias Brugger 2026-02-02 6:48 ` [PATCH 3/3] pmdomain: mediatek: Add power domain driver for MT8189 SoC irving.ch.lin 2026-02-02 12:02 ` AngeloGioacchino Del Regno 2026-02-04 17:47 ` Matthias Brugger 2026-02-02 14:59 ` [PATCH 0/3] Add support for MT8189 power controller Ulf Hansson
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox