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dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=yOjAahhpnsE340VHBy3n0bIYYx8Drjf3jKQ8mUW19vc=; b=Xe5uyd8y3pltlBgMmvhH3CPjB 3VBmmBX7l71RlD2uzfR9wmA+xcKG6nBWySp18x3Zoif8SNwax/LCMHf+FnmLhw2xplGrXgGBnMR7i zPD57t3YYL8yKpUQJ+l7Vm0gYbrgb5+aot3zAAQBy210Nk9H6nR1E9lSma7DaaKLbgv1G6hCY07EA cfxYaJGk6mwcllShll9onBbXTrE8oVixaOL6lmvqlGRWREEsBQn/OHZLuQjGZDYuMqQqkeBbA+yNd W5wYGhs9BDDd2Je74Ao3aLt6D2h10XsATgy/8vPhVPJaIDsIFzeJR2B6kukoYfcLx8qK6zMhhtAkS lNH5ZeEKQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kcQck-0001Ya-SU; Tue, 10 Nov 2020 10:11:38 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kcQci-0001X1-7t for linux-arm-kernel@lists.infradead.org; Tue, 10 Nov 2020 10:11:37 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 61C3C11D4; Tue, 10 Nov 2020 02:11:31 -0800 (PST) Received: from [10.57.23.123] (unknown [10.57.23.123]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 58AC53F6CF; Tue, 10 Nov 2020 02:11:30 -0800 (PST) Subject: Re: [PATCH v3 22/26] coresight: etm4x: Add necessary synchronization for sysreg access To: Mathieu Poirier References: <20201028220945.3826358-1-suzuki.poulose@arm.com> <20201028220945.3826358-24-suzuki.poulose@arm.com> <20201109183255.GA3396611@xps15> From: Suzuki K Poulose Message-ID: <7370dc60-ca9c-7b58-0b56-6fcef628304f@arm.com> Date: Tue, 10 Nov 2020 10:11:23 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.1 MIME-Version: 1.0 In-Reply-To: <20201109183255.GA3396611@xps15> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201110_051136_373487_FA3E9330 X-CRM114-Status: GOOD ( 25.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: coresight@lists.linaro.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 11/9/20 6:32 PM, Mathieu Poirier wrote: > On Wed, Oct 28, 2020 at 10:09:41PM +0000, Suzuki K Poulose wrote: >> As per the specification any update to the TRCPRGCTLR must be synchronized >> by a context synchronization event (in our case an explicist ISB) before >> the TRCSTATR is checked. >> >> Cc: Mike Leach >> Cc: Mathieu Poirier >> Signed-off-by: Suzuki K Poulose >> --- >> drivers/hwtracing/coresight/coresight-etm4x-core.c | 13 +++++++++++++ >> 1 file changed, 13 insertions(+) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index e36bc1c722c7..4bc2f15b6332 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -178,6 +178,15 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) >> /* Disable the trace unit before programming trace registers */ >> etm4x_relaxed_write32(csa, 0, TRCPRGCTLR); >> >> + /* >> + * If we use system instructions, we need to synchronize the >> + * write to the TRCPRGCTLR, before accessing the TRCSTATR. >> + * See ARM IHI0064F, section >> + * "4.3.7 Synchronization of register updates" >> + */ >> + if (!csa->io_mem) >> + isb(); >> + > > When I first read the documentation on system instruction section 4.3.7 really > got me thinking... > > At the very top, right after the title "Synchronization of register updates" one > can read "Software running on the PE...". Later in the text, when specifying > the synchronisation rules, the term "trace analyzer" is used. _Typically_ a trace > analyzer is an external box. > Very good point. The trace analyzer could still use the system register to program the ETM and causing a context synchronization event is tricky from within the trace analyzer. And I agree that there is a bit of confusion around the synchronization from a self-hosted point of view. I believe this is true for the self-hosted case too and should be clarified in the TRM. > Arm documentation is precise and usually doesn't overlook that kind of detail. > The question is to understand if a context synchronisation event is also needed > when programming is done on the PE. If so I think the documentation should be > amended. > > In that case: > > Reviewed-by: Mathieu Poirier > Thanks Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel